Countdown Timer

Rohit Timmagi, Syed Hussain, Tala Fakhouri, Matthew Buffa

Electrical and Computer Engineering Department

School of Engineering and Computer Science
Oakland University, Rochester, MI
e-mails: [email protected], [email protected], [email protected], [email protected]

​ Abstract— ​The design’s purpose is to count backwards from a logic high upon reaching this upper bound would provide a
user defined time, which could be employed to notify the user signal acted as a one second clock pulse. This one second
after that specific amount of time has passed. VHDL code for clock pulse was then connected to each of the BCD and
the design includes an implementation of both combinational modulo-6 counters. This generic counter was only active so
and synchronous circuitry. The design includes 5 counters: two
long as the pause and reset buttons were not actuated.
modulo-6 counters, two BCD counters, and one generic
counter. The BCD and modulo-6 counters count back from the B. BCD and Modulo-6 Counters
entered time when their enable input is high. In order for the
BCD and modulo-6 counters to update every second, a generic BCD counters can be used to count between zero
counter was used to slow the master clock signal, providing a and nine with every rising edge of a clock signal. Modulo-6
signal that would enable of the BCD and modulo-6 counters counters are used to count between zero and five. The BCD
every second. A serializer was also used to display different counters were used to count the least precise values of
values on the seven-segment displays. Additionally, a series of minutes and seconds (i.e. the boldface values - 5​9​:5​9​).
13 switches serve as the time input, allowing a user to set the Modulo-6 counters are used to count the tens place of the
amount of time from which the circuit counts down. Finally, a
minutes and seconds (i.e. the boldface values - ​5​9:​5​9​)​. Each
reset and load button were used to reset the display, and to
load the user’s desired time respectively. of the BCD and modulo-6 counter’s are enabled only when
the previous counter reaches its minimum value and when
I. INTRODUCTION the generic counter outputs its one second clock pulse.
Additionally, the counters output a logic high when reaching
Two drag racers awaiting launch, microwaving a frozen
their minimum values, thereby enabling the next counters to
dinner, and watching the ball descend in New York to
change their values. These four counters each have “load”
welcome the New Year all have one common theme: they
and “start time” inputs which allows the counters to start
necessitate the use of a countdown timer. The countdown
counting from the user specified value. Finally, each of the
timer’s use is extremely broad. Given such a simple concept
counter’s value is outputted to the inputs of the serializer.
as counting down, it is easy to underestimate the complexity
of a countdown timer’s circuitry. This document will C. Serializer
explore each facet of the design, including discussion on Because the the seven-segment displays are wired
how the serializer, BCD, modulo-6 and generic counters in such a way that allows only one value to be displayed at a
each function in unison to create such a useful circuit that is time, a serializer must be used to create the appearance of
often taken for granted. four different values being displayed simultaneously. The
value from each of the four counters are inputted into the
II. METHODOLOGY serializer. These four values are multiplexed, fed through a
hex decoder and then outputted to four seven-segment
A. Generic Counter displays. These values change so quickly that the display
A generic counter is not only useful to generate appears to show four different continuously lit numbers.
pulses of different frequencies, but can also count to D. Switches, Buttons and LEDs
arbitrary bounds. This generic counter was used to decrease
the master clock signal to provide a logic high every one In order to maximize the usefulness of the circuit,
second, which allowed the BCD and modulo-6 counter to is important to make its design user friendly. A series of 13
decrease their values every second. This was done by switches are used to input the desired amount of time from
modifying the generic counter to count an upper bound of which the circuit counts down. Switches 0-3 are used to
10​8​. With a master clock frequency of 100MHz, outputting a change the first digit i.e. the second’s ones place. Switches
4-6 are used to change the second digit i.e. the second’s tens
place. Switches 7-10 are used to change the third digit i.e. IV. RESULTS
the minute’s one place. Switches 11-13 are used to change The design successfully counts down from the user’s
the fourth digit i.e. the minute’s tens place. The switches inputted values.. The design notifies the user when the time
values are only loaded into the BCD and modulo-6 has expired, pauses when the pause button is pressed, and
counter’s when the user actuates the the load push button. resets when the reset button is pressed. All inputs and
Two additional push buttons are used to pause the timer, and outputs function as desired. Attached below is a video of the
reset the time. Pressing the pause button disables the generic design functioning.
counter, thereby also disabling the BCD and modulo-6
counters. The reset button is wired to all counters and the https://www.youtube.com/watch?v=wEenC2-6kbc
serializer. Finally, LEDs are illuminated when the time has
reached zero, effectively alerting the user of the time’s
expiration. CONCLUSIONS
Through the use of BCD, modulo-6 and generic
III. EXPERIMENTAL SETUP counters, the task of creating a countdown timer was
The software that was used to create this timer was achieved. This was no simple feat, as pausing the time once
Xlinx ISE Design Suite 14.7. The hardware that was used to the time expired, proved to be quite the challenge. This
implement the design was the Nexus 4 DDR board. The reinforced the importance of drawing the circuit, and using a
specific inputs and outputs of the board can be seen in the karnaugh map to derive the boolean expression needed to
constraints file, which includes: four seven-segment pause the time. Improvements to the design that could be
displays, a button to pause time, a button to reset time, made include flashing the notification LED thereby drawing
switches to input time, and LEDs to notify the time has more attention to the board when the time has expired.
expired. The design’s functionality was tested by loading
onto the Nexus board. The device’s accuracy was tested
through its comparison to a smartphone timer. It was found REFERENCES
that the design functions just as well as the smartphone, as
their times remained synchronized through the course of [1] Llmocca D VHDL Coding for FPGAs. In: VHDL Coding for FPGAs.
their countdown. http://www.secs.oakland.edu/~llamocca/vhdlforfpgas.html. Accessed
2 Nov 2016