Practice

Address Instruction
0 Addi r0, r1, 2
1 Addi r3, r0, 2
2 BEQ r2, r3, 3
3 SW r0, 2(r2)
4 JAL r5, 8
5 LW r3, 2(r2)
6 Add r6, r3, r3
7 JALR r1, r6, -4
8 Add r6, r5, r0
9 BEQ r0, r0,-5
10 Addi r6, r6, 2

Draw the timing diagram for one iteration then answer the following questions:

1. How many cycles it will take to execute the given code? ⇐

2. How many forwarding? 5

forwarding
3. How many stalls? 2 stalls

4. How many flushes? 3 flush

5. By referring to the previous code, identify the data forwarding cases if any. ( Inst.
Writes RF/Stage, Inst. Reads RF/stage, registers)

6. By referring to the previous code, identify the stalling cases if any. ( Inst. Writes
RF/Stage, Inst. Reads RF/stage, registers)

7. The figure below shows part of the pipelined data path with the forwarding muxes
and the forwarding and hazard detection unit. In addition, the table below lists the
instructions and their opcodes.

Modify the forwarding and hazard detection unit to handle the hazard conditions in the
previous code. Make sure to write comments to describe the Verilog code.

Run and simulate the output.

 step Is

O .
add i

I . add i

2 .
Beef not .

taken
3 . SW
→
4 .
gal ( PC = 8 )
5 . LW ( flush )
8. add

g
a .
Beer taken
, -
is )
5

to .
add i C flush )
L W
5
.

6 . add

7. Jal R rt ,
r 6
,
-4

Go
8. add C flush )

addict
interfering
.
 ro 2

!
's ro ,
r2 2 =
,

Ig Fwd 2

1. addi r3 VO 2 r3= 4
, ,

↳ Fwdz
not taken
2. Bley r2
,r3 ,
3

3. Sw ro
,
zcrz )
M
[2-1%2] =

4. Jal r 5,8 r5=pc -11 5

PC

)
= 8
5. Lw r 3,242 ) flush

[email protected]
fwdz

8. r6.rs add ro r 6=7

,

9. Beer ro.ro ,
- S taken ,pc=pc -12+65 )
pc= S

to . addi flush

g.
LW r3,2( V2 ) r3=M[ 2-1%1=2
6. add VG
\\Fwd4
,r3,r3 r6=4
↳ Fwd 5

7. Jahr rt ,
VG -4
r2=pc -11=8

:3?
,

PEE
.÷
:c
Go
" "
 Time
Step 3 Hpl
diagram

CC I 4 6 7 13 14 17
2 3 5 8 9 10 4 12 1516 18

O addi IF ID Ex M WB
to
.

1. addi IF ID Ex M WB
to
IF ID ID Ex M WB
2. Beef stall

if 86N Ex M WB
3. Sw lb
statement
4. Jal IF ID E x M WB

sew

8. add
' '

?!°
?: M WB

9. Beef If ID Ex M WB

to .
addi is .
Of OD O

5. Lw IF ID Ex M WB
£

&
6. add IF Ex M
thus ID
WB

7.
jar ¥6 - ex m WB

IF 0 O co
statement
8. add
 Fwd case I

⇐
write addi M rd
stage reg

.
.

sins
÷÷÷
( opcode M = = 2 off rd M = = RSI Ex )

pinst
egrsz
A -
Ex -
fwd =L ; YALU out

sina.am
Fwd case 2

@iniY.cop7Yae7I.s
t write addi
stage
'm
M

'D
neg
Td

,
if C M 44 rdM==rS2 I D)
opcode = 2
-
-

B -
ID -
Fwd =L ; HALO out

Fwd case 3

:Pp%
.IE
Cfi
!
write WB
t
gal stage reg rd
read add EX
inst
stage neg
rsz

: see rdwrs-e-rssc.is

A EX fwd 2 X WB data
- -
=
;
 Fwd Y
case

inst write Lw WB rd
stage neg
add rst

ears
read Ex rs 2

&÷÷÷÷÷
inst
stage neg
,

pins
&÷:÷
.
. . . . . . . . . .

A - Ex -
fwd =
2
j DWB data

rays ,g ;
)
if (
opcode WB = =3 44 rd WB = = rS2 Ex )

B - Ex -
fwd = 2 ;XwBdata
end

Fwd case S

write

:!
t Lw
stage WB rd
reg
" .
'

(
opcode WB = =3
4 A Vd WB = = r SLID )

A - ID fwd = =3
; XWB data

)
-

2.420451M¥ j si si
 -
P

Rsl fits , g. , -6=1 ,

\ IDs ,
mix

① make sure it is 4 to I mvx

=

② WB data wire ( I ! £ s )
copy ,

③ paste the wire at option 3

in A - ID -
fwd mux 8

A - lb -
Fwd