What is a Microprocessor?

 The computer’s Central Processing Unit (CPU) built on a single Integrated Circuit

(IC) is called a microprocessor.

A digital computer with one microprocessor which acts as a CPU is called a

microcomputer.

 It is a programmable, multipurpose, clock-driven, register-based electronic device that

reads binary instructions from a storage device called memory, accepts binary data as
input, & processes data according to those instructions, and provides results as output.

 The microprocessor contains millions of tiny components like transistors, registers, and
diodes that work together.
Block Diagram of a Microcomputer
 Evolution of Microprocessors
 The first generation microprocessors were introduced in the year 1971-1972 by
Intel Corporation. It was named Intel 4004 since it was a 4-bit processor.
 The second generation microprocessors were introduced in 1973 again by Intel. It
was a first 8 - bit microprocessor which could perform arithmetic and logic
operations on 8-bit words. It was Intel 8008, and another improved version was
Intel 8088.
 The third generation microprocessors, introduced in 1978 were represented
by Intel's 8086, Zilog Z800 and 80286, which were 16 - bit processors with a
performance like minicomputers.
 Several different companies introduced the 32-bit microprocessors, but the most
popular one is the Intel 80386.
 Basic Terms used in Microprocessor
 Instruction Set - The group of commands that the microprocessor can
understand is called Instruction set. It is an interface between hardware and
software.
 Bus - Set of conductors intended to transmit data, address or control information
to different elements in a microprocessor. A microprocessor will have three types
of buses, i.e., data bus, address bus, and control bus.
 IPC (Instructions Per Cycle) - It is a measure of how many instructions a CPU
is capable of executing in a single clock.
 Clock Speed - It is the number of operations per second the processor can
perform. It can be expressed in megahertz (MHz) or gigahertz (GHz). It is also
called the Clock Rate.
 Contd…
Bandwidth - The number of bits processed in a single instruction is
called Bandwidth.

Word Length - The number of bits the processor can process at a

time is called the word length of the processor. 8-bit Microprocessor
may process 8 -bit data at a time. The range of word length is from 4
bits to 64 bits depending upon the type of the microcomputer.

Data Types - The microprocessor supports multiple data type

formats like binary, ASCII, signed and unsigned numbers.
Working of Microprocessor
 The microprocessor follows a sequence to execute the
instruction: Fetch, Decode, and then Execute.

 The instructions are stored in the storage memory of the

computer in sequential order.

 The microprocessor fetches those instructions from the

stored area (memory), then decodes it and executes those
instructions till STOP instruction is met.

 Then, it sends the result in binary form to the output port.

Between these processes, the register stores the temporary
data and ALU (Arithmetic and Logic Unit) performs the
computing functions.
 Features of Microprocessor
 Low Cost: Microprocessors are affordable due to advances in manufacturing
technology and economies of scale.
 High Speed: They execute instructions rapidly, enabling quick processing of data and
tasks.
 Small Size: Microprocessors are compact, allowing them to fit into a variety of devices
and systems.
 Versatile: They can be programmed to perform a wide range of functions, making them
suitable for diverse applications.
 Low Power Consumption: Designed to operate efficiently, microprocessors consume
minimal power, extending battery life and reducing energy costs.
 Less Heat Generation: They produce less heat compared to older technologies,
minimizing the need for extensive cooling solutions.
 Reliable: Microprocessors offer consistent performance and durability, contributing to
the overall stability of electronic systems.
 Portable: Their small size and low power requirements make them ideal for use in
portable and mobile devices.
 Microprocessor Architecture
The microprocessor is the CPU (Central Processing Unit) of a
computer. It is the heart of the computer. Here, we will describe Intel
8085 as it is one of the most popular 8-bit microprocessor
 Flag Register…… cont….
Flag Significance
18
C or CY (Carry) CY is set when an arithmetic operation generates a carry out,
otherwise it is 0 (reset)

P (Parity) P= 1; if the result of an ALU operation has an even number of 1’s

in A;
P= 0; if number of 1 is odd.

AC (Auxiliary carry) Similar to CY,

AC= 1 if there is a carry from D3 to D4 Bit
AC= 0 if there is a no carry from D3 to D4 Bit
(not available for user)
Z(zero) Z = 1; if result in A is 00H
0 otherwise

S(Sign) S=1 if D7 bit of the A is 1(indicate the result is -ive)

S= 0 if D7 bit of the A is 0(indicate the result is +ive)
 8085 Architecture …… cont….
 In addition to register MP contains some latches and buffer
19
 The "Increment and Decrement Address Latch" is a 16-bit register that adjusts the values of the
Program Counter (PC) and Stack Pointer (SP). It increases or decreases these values to navigate
through memory or manage the stack.
 Address buffer

 8 bit unidirectional buffer

 Used to drive high order address bus(A8 to A15)

 When it is not used under such as reset, hold and halt etc this buffer is used tristate high order
address bus.

 Data/Address buffer
 8 bit bi-Directional buffer

 Used to drive the low order address (A0 to A7) and data (D0 to D7) bus.

 Under certain conditions such as reset, hold and halt etc this buffer is used tristate low order address bus.
 Features of Microprocessor- 8085
20
 8085 is developed by INTEL

 8 bit microprocessor: can accept 8 bit data simultaneously

 Operates on single +5V D.C. supply.

 Designed using NMOS technology

 6200 transistor on single chip

 It provides on chip clock generator, hence it does not require external clock generator.

 Operates on 3MHz clock frequency.

 8bit multiplexed address/data bus, which reduce the number of pins.

 16 address lines, hence it can address 2^16 = 64 K bytes of memory

 It generates 8 bit I/O addresses, hence it can access 2^8 = 256 I/O ports.

 5 hardware interrupts i.e. TRAP, RST6.5, RST5.5, RST4.5, and INTR

 It provides DMA.
21
8085 Pin Diagram

Functional Pin diagram

Pin Configuration
22
8085 Pin Description
 The 8085 is an 8-bit general purpose microprocessor that can
address 64K Byte of memory.
 It has 40 pins and uses +5V for power. It can run at a maximum
frequency of 3 MHz.
 The pins on the chip can be grouped into 6 groups:
 Address Bus and Data Bus.
 Status Signals.
 Control signal
 Interrupt signal
 Power supply and Clock signal
 Reset Signal
 DMA request Signal
 Serial I/O signal
 Externally Initiated Signals.
 The Address and Data Busses
 Address Bus (Pin 21-28)
23  16 bit address lines A0 to A15
 The address bus has 8 signal lines A8 – A15 which are unidirectional.
 The other 8 address lines A0 to A7 are multiplexed (time shared) with the 8 data bits.

 Data Bus (Pin 19-12)

 To save the number of pins lower order address pin are multiplexed with 8 bit data bus
(bidirectional)
 So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the same time.
 During the execution of the instruction, these lines carry the address bits during the early part
(T1 state), then during the later parts(T2 state) of the execution, they carry the 8 data bits.
 Status Signals
Status Pins – ALE, S1, S0
1. ALE (Address Latch Enable) is a signal pin on a microprocessor.
 Purpose: It helps separate the address and data on the same set of wires (called AD0 – AD7 lines).
 How it works:
 When ALE is high (1), it means the AD lines are carrying address information.
 When ALE is low (0), it means the AD lines are carrying data.
 Latch Function: The ALE signal can be used to enable a latch (a kind of storage) to "catch" and hold
the address from the AD lines when ALE is high.

Operation S1 S0
2. S1 and S0 (Status Signal): (Pin 33 and 29) HALT 0 0
 Status signals to specify the kind of operation being performed . WRITE 0 1
 Usually un-used in small systems. READ 1 0
FETCH 1 1
 Control Signals
Control Pins – RD, WR, IO/M(active low)
1. RD: Read(Active low) (Pin 32)
 Read Memory or I/O device and indicates that data is to be read either from memory or I/P device and
data bus is ready for accepting data from the memory or I/O device.
2. WR: Write(Active low) (Pin 31)
 Write Memory or I/O device indicates that data on the data bus are to be written into selected memory
or I/O device.
3. IO/M: (Input Output/Memory-Active low) (Pin 34)
 Signal specifies that the read/write operation relates to whether memory or I/O device.
 When (IO/M=1) the address on the address bus is for I/O device
 When (IO/M=0) the address on the address bus is for memory
IO/M(active low) RD WR Control Signal Operation
0 0 1 MEMR M/M Read
0 1 0 MEMW M/M write
1 0 1 IOR I/O Read
1 1 0 IOW I/O Write
26
Interrupts
 They are the signals initiated by an external device to request the
microprocessor to do a particular task or work.
 There are five hardware interrupts called, (Pin 6-11)

 On receipt of an interrupt, the microprocessor acknowledges the interrupt by

the active low INTA (Interrupt Acknowledge) signal.
 Power supply and Clock Signal
Vcc (Pin 40) : single +5 volt power supply.
Vss (Pin 20) : Ground

X0 and X1 Pins:

 These are two pins on a microprocessor where you connect components that determine the speed
at which the processor works. CLK (output): (Pin 37) .
 You can connect a crystal (which is a small, precise component that sets the clock frequency).
 Alternatively, you can connect an R/C network (a combination of resistors and capacitors) or an
LC network (a combination of inductors and capacitors).
 The frequency set by these components determines the internal clock speed of the processor.
 Example: If you connect a 6 MHz crystal to X0 and X1, the processor’s internal clock will
effectively run at 3 MHz because it divides the frequency by two.
 Reset Signals
 Reset In (input, active low) (Pin 36)
 This signal is used to reset the microprocessor.
 The program counter inside the microprocessor is set to zero(0000H).
 The buses are tri-stated which means tri-stated means the bus lines can
be actively driving a signal or they can be in a state where they do not
affect the bus, allowing multiple devices to share the same bus.

 Reset Out (Output, Active High) (Pin 3)

 It indicates MP is being reset.
 Used to reset all the connected devices when the microprocessor is
reset.
 DMA Request Signals
 DMA:
 When multiple devices share the same bus, tristate gates are used to disconnect all devices except
the one currently communicating, preventing interference.
 DMA (Direct Memory Access) allows large data transfers between memory and an I/O device
directly, without involving the CPU, which is temporarily disabled by tri-stating its buses.
 HOLD (Pin 38)
 This signal indicates that another device is requesting the use of address and data bus.
 So it relinquish the use of buses as soon as the current machine cycle is completed.
 MP regains the bus after the removal of a HOLD signal
 HLDA (Pin 39)
 On receipt of HOLD signal, the MP acknowledges the request by sending out HLDA signal
and leaves out the control of the buses.
 After the HLDA signal the DMA controller starts the direct transfer of data.
 After the removal of HOLD request HLDA goes low.
 Serial I/O Signals
These pins are used for serial data communication

SID (input) Serial input data (Pin 4)

 It is a data line for serial input
 Used to accept serial data bit by bit from external device
 The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is
executed.

 SOD (output) Serial output data (Pin 5)

 It is a data line for serial output
 Used to transmit serial data bit by bit to the external device
 The 7th bit of the accumulator is outputted on SOD line when SIM instruction is executed.
Programming model of 8085

Accumulator 16-bit
Address Bus
Register Array
ALU

Memory Pointer
Flags Registers 8-bit Data
Bus
Instruction
Decoder

Control Bus
Timing and Control Unit
Accumulator (8-bit) Flag Register (8-bit)
S Z AC P CY

B (8-bit) C (8-bit)
D (8-bit) E (8-bit)
H (8-bit) L (8-bit)
Stack Pointer (SP) (16-bit)
Program Counter (PC) (16-bit)

8- Lines 16- Lines

Bidirectional Unidirectional
Overview: 8085 Programming model

1. Six general-purpose Registers

2. Accumulator Register
3. Flag Register
4. Program Counter Register
5. Stack Pointer Register
1. Six general-purpose registers
 B, C, D, E, H, L
 Can be combined as register pairs to perform 16-bit
operations (BC, DE, HL)

2. Accumulator – identified by name A

 This register is a part of ALU
 8-bit data storage
 Performs arithmetic and logical operations
 Result of an operation is stored in accumulator
3. Flag Register
 This is also a part of ALU
 8085 has five flags named
 Zero flag (Z)
 Carry flag (CY)
 Sign flag (S)
 Parity flag (P)
 Auxiliary Carry flag (AC)
These flags are five flip-flops in flag register
Execution of an arithmetic/logic operation can
set or reset these flags

Condition of flags (set or reset) can be tested

through software instructions
8085 uses these flags in decision-making
process
4.Program Counter (PC)
A 16-bit memory pointer register
Used to sequence execution of program instructions
Stores address of a memory location
where next instruction byte is to be
fetched by the 8085
when 8085 gets busy to fetch current instruction from
memory
PC is incremented by one
PC is now pointing to the address of
next instruction
5. Stack Pointer Register
 a 16-bit memory pointer register
 Points to a location in Stack memory
 Beginning of the stack is defined by loading a 16-bit address in stack
pointer register
 What is instruction?
 An instruction is a binary pattern designed inside a
microprocessor to perform a specific function.

 The entire group of instructions that a microprocessor

supports is called Instruction Set.

 8085 has 246 instructions.

 74 operation codes, e.g. MOV
 Each instruction is represented by an 8-bit binary value.
 These 8-bits of binary value is called Op-Code or Instruction
Byte.
Classification of instruction

1.Accordi
ng to 2.According
addressin to size
g modes

3.According to
operation
 Addressing Modes of 8085
To perform any operation, we have to give the corresponding
instructions to the microprocessor.
In each instruction, programmer has to specify 3 things:
1. Operation to be performed i.e. Opcode
2. Address of source of data i.e. Operands
3. Address of destination of result.
 Definition

 The various ways of specifying operands for an instruction are called the addressing
modes.
 The various addressing modes that are defined in a given instruction set architecture
define how machine language instructions in that architecture identify the operand(s)
of each instruction.
 In any microprocessor instruction, the source and destination operands can be a
 Register
 Memory Location
 8-bit number
The method by which the address of source of data and the address of the destination of the result is
given in the instruction are called the Addressing modes.
 8085 uses the following addressing modes:

1. Implied/Implicit Addressing Mode

2. Immediate Addressing Mode
3. Direct Addressing Mode
4. Register Addressing Mode
5. Register Indirect Addressing Mode
 Implied/Implicit Addressing Mode

 In implied/implicit addressing mode the operand is hidden and the data to be

operated is available in the instruction itself.
 If address of source of data as well as address of destination of result is
fixed, then there is no need to give any operand along with the instruction.
 Examples:

 CMA (complement accumultor )

 RRC (rotate accumulator A right by one bit)
 RLC (rotate accumulator A left by one bit)
 Immediate Addressing Mode
 In this mode, the operand is specified within the instruction itself.
 If the data is 8-bit, then the instruction will be of 2 bytes. The first byte is
opcode followed by an 8-bit data.
 If the data is of 16-bit then the instruction will be of 3 bytes. The first byte is
opcode at memory location N followed by the higher order data byte at
memory location N+1 and lower order data byte at memory location N+2.
 Examples:
 MVI B 45 (move the data 45H immediately to register B)
 LXI H 3050 (load the H-L pair with the operand 3050H immediately)
 JMP address (jump to the operand address immediately)
 Direct Addressing Mode
The data to be operated is available inside a memory
location and that memory location is directly specified as
an operand.
The operand is directly available in the instruction itself.
Examples:
LDA 2050 (load the contents of memory location into
accumulator A)
LHLD address (load contents of 16-bit memory location into H-L
register pair)
 Register Addressing Mode
In this mode, the operand is in general purpose register.
The data to be operated is available inside the register(s) and register(s)
is(are) operands. Therefore the operation is performed within various
registers of the microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)
 Register Indirect Addressing Mode

In this mode, the address of operand is specified by a register pair.

The data to be operated is available inside a memory location and that
memory location is indirectly specified b a register pair.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair
to the accumulator)
LDAX B (move contains of B-C register to the accumulator)
 Data flow between memory and MPU:
First of all the 16-bit address is placed on the address bus from the program
counter.
Let say the address is 2005H where the data is placed.
The higher order address i.e. 20H is placed on the address bus A8-A15 while the
lower order address i.e. 05h is placed on the multiplexed address and data bus
ADO-AD7.
The lower order address continues to remain on this address bus so long as ALE
(Address Latch Enable) remains positive. Once ALE goes low it carries data.
The control unit sends the signal to indicate what type of operation is to be
performed. Since the data is to be read from the memory therefore it sends to
enable the memory chip.
 The byte from the memory location is then placed on the data bus i.e. 4F saved in
location 2005H is placed on the data bus and sent to the instruction decoder.
 The instruction is decoded and accordingly the task is performed by the ALU i.e.
Arithmetic and logic unit.
 Instructions in terms of byte size or
word size

• 1-byte instruction
• 2-byte instruction
• 3-byte instruction
 1.One byte instruction
• A one byte instruction includes the operand and
the op-code in same byte.
• These type of instructions occupy only one
memory location.
• For example:
Opcode Operand Hex Code

MOV C,A 4F
ADD B 80
CMA 2F
 2.Two byte instruction
• A two byte instruction includes the op-code and the 8-bit
data or address.
• This type of instruction occupies 2-memory location.

• For example:

Opcode Operand Hex

Code
MVI A, 07 3E, 07
 3.Three byte instruction
• A 3-byte instruction includes the op-code and 16-bit
address or data.
• This type of instructions occupy three memory location.
• For example:

Opcode Operand Hex Code

JMP 2085 C3, 85, 20
 Instruction Set of 8085
 An instruction is a binary pattern designed inside a microprocessor to perform a
specific function.

 The entire group of instructions that a microprocessor supports is called

Instruction Set.

 8085 has 246 instructions.

 Each instruction is represented by an 8-bit binary value.

 These 8-bits of binary value is called Op-Code or Instruction Byte.

 Classification of Instruction Set

 Data Transfer Instruction

 Arithmetic Instructions

 Logical Instructions
 Branching Instructions

 Control Instructions
 Data Transfer Instructions

These instructions move data between registers, or

between memory and registers.
These instructions copy data from source to destination.
While copying, the contents of source are not modified.
 Data Transfer Instructions
Opcode Operand Description
MOV Rd, Rs Copy from source to destination.
M, Rs
Rd, M

 This instruction copies the contents of the source register into the
destination register.

 The contents of the source register are not altered.

 If one of the operands is a memory location, its location is specified

by the contents of the HL registers.

 Example: MOV B, C or MOV B, M

Example

Instruction: MOV A, B

Register contents Register contents after

before Execution Execution
A 9A h A 89 h

B 89 h B 89 h

Note: No flags are modified during the

execution of data transfer instruction.
 Data Transfer Instructions

Opcode Operand Description

MVI Rd, Data Move immediate 8-bit
M, Data

 The 8-bit data is stored in the destination register or

memory.

 If the operand is a memory location, its location is

specified by the contents of the H-L registers.

 Example: MVI B, 57H or MVI M, 57H

Example

Instruction: MVI B, 18h

Register contents Register contents after

before Execution Execution
B 9A h B 18 h
 Data Transfer Instructions

Opcode Operand Description

LDA 16-bit address Load Accumulator

 The contents of a memory location, specified by a 16-bit

address in the operand, are copied to the accumulator.

 The contents of the source are not altered.

 Example: LDA 2034H

Example

Instruction: LDA 2005h

Register contents Register contents after

before Execution Execution
A 87 h A 45 h

MEMORY MEMORY
2003 7Ah 2003 7Ah
2004 C2h 2004 C2h
2005 45h 2005 45h
2006 F4h 2006 F4h
 Data Transfer Instructions

Opcode Operand Description

LDAX B/D Register Load accumulator indirect
Pair

 The contents of the designated register pair point to a memory

location.
 This instruction copies the contents of that memory location
into the accumulator.
 The contents of either the register pair or the memory location
are not altered.
 Example: LDAX B
Example

Instruction: LDAX D

Register contents Register contents after

before Execution Execution
A 2Bh A C2 h
DE 4020h DE 4020h
MEMORY MEMORY
401F 7Ah 401F 7Ah
4020 C2h 4020 C2h
4021 45h 4021 45h
4022 F4h 4022 F4h
 Data Transfer Instructions

Opcode Operand Description

LXI Reg. pair, 16- Load register pair immediate
bit data

 This instruction loads 16-bit data in the register pair.

 Example: LXI H, 2034 H

Example

Instruction: LXI B, 1122h

Register contents Register contents after

before Execution Execution
BC 76DA h BC 1122 h
 Data Transfer Instructions

Opcode Operand Description

LHLD 16-bit address Load H-L registers direct

 This instruction copies the contents of memory location

pointed out by 16-bit address into register L.

 It copies the contents of next memory location into

register H.

 Example: LHLD 2040 H

 Example

Instruction: LHLD 2005h

Register contents
Register contents after
before Execution
Execution
HL 74F1h HL 45C2h

MEMORY MEMORY
2004 7Ah 2004 7Ah
2005 C2h 2005 C2h
2006 45h 2006 45h

2007 F4h 2007 F4h

 Data Transfer Instructions

Opcode Operand Description

STA 16-bit address Store accumulator direct

 The contents of accumulator are copied into the memory

location specified by the operand.

 Example: STA 2500 H

Example

Instruction: STA 2005h

Register contents Register contents after

before Execution Execution
A 87 h A 87 h

MEMORY MEMORY
2003 7Ah 2003 7Ah
2004 C2h 2004 C2h
2005 45h 2005 87h
2006 F4h 2006 F4h
 Data Transfer Instructions

Opcode Operand Description

STAX Reg. pair Store accumulator indirect

 The contents of accumulator are copied into the memory

location specified by the contents of the register pair.

 Example: STAX B
Example

Instruction: STAX B

Register contents Register contents after

before Execution Execution
A A4h A A4 h

BC 4020h BC 4020h
MEMORY MEMORY
401F 7Ah 401F 7Ah
4020 C2h 4020 A4h
4021 45h 4021 45h
4022 F4h 4022 F4h
 Data Transfer Instructions

Opcode Operand Description

SHLD 16-bit address Store H-L registers direct

 The contents of register L are stored into memory location

specified by the 16-bit address.

 The contents of register H are stored into the next memory

location.

 Example: SHLD 2550 H

 Example

Instruction: SHLD 2005h

Register contents
Register contents after
before Execution
Execution
HL 74F1h HL 74F1h

MEMORY MEMORY
2004 7Ah 2004 7Ah
2005 A4h 2005 F1h
2006 45h 2006 74h

2007 F4h 2007 F4h

 Data Transfer Instructions

Opcode Operand Description

XCHG None Exchange H-L with D-E

 The contents of register H are exchanged with the contents

of register D.

 The contents of register L are exchanged with the contents

of register E.

 Example: XCHG
Example

Instruction: XCHG

Register contents Register contents after

before Execution Execution
HL 1234 h HL 5678 h

DE 5678 h DE 1234 h
 Data Transfer Instructions

Opcode Operand Description

SPHL None Copy H-L pair to the Stack Pointer (SP)

 This instruction loads the contents of H-L pair into SP.

 Example: SPHL
 Data Transfer Instructions

Opcode Operand Description

XTHL None Exchange H–L with top of stack

 The contents of L register are exchanged with the location

pointed out by the contents of the SP.

 The contents of H register are exchanged with the next

location (SP + 1).

 Example: XTHL
 Data Transfer Instructions

Opcode Operand Description

PCHL None Load program counter with H-L contents

 The contents of registers H and L are copied into the

program counter (PC).

 The contents of H are placed as the high-order byte and

the contents of L as the low-order byte.

 Example: PCHL
 Data Transfer Instructions

Opcode Operand Description

PUSH Reg. pair Push register pair onto stack

 The contents of register pair are copied onto stack.

 SP is decremented and the contents of high-order registers (B,

D, H, A) are copied into stack.

 SP is again decremented and the contents of low-order registers

(C, E, L, Flags) are copied into stack.

 Example: PUSH B
 Data Transfer Instructions

Opcode Operand Description

POP Reg. pair Pop stack to register pair

 The contents of top of stack are copied into register pair.

 The contents of location pointed out by SP are copied to the

low-order register (C, E, L, Flags).

 SP is incremented and the contents of location are copied to the

high-order register (B, D, H, A).

 Example: POP H
 Data Transfer Instructions

Opcode Operand Description

OUT 8-bit port Copy data from accumulator to a port
address with 8-bit address

 The contents of accumulator are copied into the I/O port.

 Example: OUT 78 H
 Data Transfer Instructions

Opcode Operand Description

IN 8-bit port Copy data to accumulator from a port
address with 8-bit address

 The contents of I/O port are copied into accumulator.

 Example: IN 8C H
 Arithmetic Instructions

 These instructions perform the operations like:

 Addition

 Subtract

 Increment

 Decrement
 Arithmetic Instructions
ADD
•ADD r or M
•ADC r or M
•ADI 8 bit data
•ACI 8 bit data
•DAD rp
SUB
•SUB r or M
•SBB r or M
•SUI 8 bit data
•SBI 8 bit data
INR r or M
DCR r or M
INX rp
DCX rp
DAA
 Addition

 Any 8-bit number, or the contents of register, or the contents of

memory location can be added to the contents of accumulator.

 The result (sum) is stored in the accumulator.

 No two other 8-bit registers can be added directly.

 Example: The contents of register B cannot be added directly

to the contents of register C.
 Arithmetic Instructions

Opcode Operand Description

ADD R Add register or memory to accumulator
M

 The contents of register or memory are added to the contents of

accumulator.

 The result is stored in accumulator.

 If the operand is memory location, its address is specified by H-L pair.

 All flags are modified to reflect the result of the addition.

 Example: ADD B or ADD M

 Example

Instruction: ADD B

Register contents Register contents after

before Execution Execution

A 9A h A 23 h

B 89 h B 89 h

1001 1010
1000 1001
0010 0011
Flag: S=0, Z=0, AC=1 , P=0 and CY=1

Note: All flags are affected during the execution of arithmetic instruction.
 Arithmetic Instructions

Opcode Operand Description

ADC R Add register or memory to accumulator
M with carry

 The contents of register or memory and Carry Flag (CY) are added to the
contents of accumulator.

 The result is stored in accumulator.

 If the operand is memory location, its address is specified by H-L pair.

 All flags are modified to reflect the result of the addition.

 Example: ADC B or ADC M

 Example

Instruction: ADC B

Register contents Register contents after

before Execution Execution

A 9A h A 24 h

B 89 h B 89 h

Flag: S=0, Z=0, Flag: S=0, Z=0, AC=1

AC=0 , P=0 and C=1 1 0 0 1 1 0 1 0 , P=1 and CY=1
1000 1001
1
0010 0100
 Arithmetic Instructions

Opcode Operand Description

ADI 8-bit data Add immediate to accumulator

 The 8-bit data is added to the contents of accumulator.

 The result is stored in accumulator.

 All flags are modified to reflect the result of the addition.

 Example: ADI 45 H
 Example

Instruction: ADI B2h

Register contents Register contents after

before Execution Execution

A C4 h A 76 h

Flag: S=0, Z=0, Flag: S=0, Z=0, AC=0

AC=0, P=0 and CY=0 , P=0 and CY=1
1100 0100
1011 0010
0111 0110
 Arithmetic Instructions

Opcode Operand Description

ACI 8-bit data Add immediate to accumulator with
carry

 The 8-bit data and the Carry Flag (CY) are added to the
contents of accumulator.

 The result is stored in accumulator.

 All flags are modified to reflect the result of the addition.

 Example: ACI 45 H
 Example

Instruction: ACI 15h

Register contents Register contents after

before Execution Execution

A 38 h A 4E h

Flag: S=0, Z=0, AC=0 ,

Flag: S=0, Z=0, P=1 and CY=0
AC=0 , P=0 and C=1
0011 1000
0001 0101
1
0100 1110
 Arithmetic Instructions

Opcode Operand Description

DAD Reg. pair Add register pair to H-L pair

 The 16-bit contents of the register pair are added to the

contents of H-L pair.
 The result is stored in H-L pair.

 If the result is larger than 16 bits, then CY is set.

 No other flags are changed.

 Example: DAD B
Example

Instruction: DAD B

Register contents Register contents after

before Execution Execution
HL 2233 h HL 3355 h

BC 1122 h BC 1122 h

Note: No flags are affected except Carry Flag.

 Subtraction

 Any 8-bit number, or the contents of register, or the contents of

memory location can be subtracted from the contents of accumulator.

 The result is stored in the accumulator.

 Subtraction is performed in 2’s complement form.

 If the result is negative, it is stored in 2’s complement form.

 No two other 8-bit registers can be subtracted directly.

 Arithmetic Instructions

Opcode Operand Description

SUB R Subtract register or memory from
M accumulator

 The contents of the register or memory location are subtracted from the
contents of the accumulator.

 The result is stored in accumulator.

 If the operand is memory location, its address is specified by H-L pair.

 All flags are modified to reflect the result of subtraction.

 Example: SUB B or SUB M

 Example

Instruction: SUB M

Register contents Register contents after

before Execution Execution
A 20 h A 18 h

HL 8500h HL 8500h
MEMORY
MEMORY
84FF 7Ah
84FF 7Ah
8500 08h
8500 08h
8501 45h 0010 0000
0000 1000 8501 45h
8502 F4h
0001 1000 8502 F4h
Flag: S=0, Z=0,
Flag: S=0, Z=0, AC=1
AC=0 , P=0 and
, P=1 and CY=0
CY=1
 Arithmetic Instructions

Opcode Operand Description

SBB R Subtract register or memory from
M accumulator with borrow

 The contents of the register or memory location and Borrow Flag (i.e. CY)
are subtracted from the contents of the accumulator.

 The result is stored in accumulator.

 If the operand is memory location, its address is specified by H-L pair.

 All flags are modified to reflect the result of subtraction.

 Example: SBB B or SBB M

 Example

Instruction: SBB B

Register contents Register contents after

before instruction Execution

A 40 h A 1F h

B 20 h B 20 h

Flag: S=0, Z=0, Flag: S=0, Z=0,

AC=0 , P=0 and C=1 0 1 0 0 0 0 0 0 AC=1, P=0 and CY=0
0010 0000
1
0001 1111
 Arithmetic Instructions

Opcode Operand Description

SUI 8-bit data Subtract immediate from accumulator

 The 8-bit data is subtracted from the contents of the

accumulator.

 The result is stored in accumulator.

 All flags are modified to reflect the result of subtraction.

 Example: SUI 45 H
 Example

Instruction: SUI 13h

Register contents Register contents after

before Execution Execution

A 05 h A F2 h

Flag: S=0, Z=0, AC=0 Flag: S=1, Z=0,

, P=0 and CY=0 AC=0, P=0 and CY=1
0000 0101
0001 0011
1111 0010
 Arithmetic Instructions

Opcode Operand Description

SBI 8-bit data Subtract immediate from accumulator
with borrow

 The 8-bit data and the Borrow Flag (i.e. CY) is subtracted
from the contents of the accumulator.

 The result is stored in accumulator.

 All flags are modified to reflect the result of subtraction.

 Example: SBI 45 H
 Example

Instruction: SBI 13h

Register contents Register contents after

before Execution Execution

A 18 h A 04 h

Flag: S=0, Z=0,

Flag: S=0, Z=0, AC=0, P=0 and CY=0
AC=0 , P=0 and C=1
0001 1000
0001 0011
1
0000 0100
 Increment / Decrement

 The 8-bit contents of a register or a memory location can be

incremented or decremented by 1.

 The 16-bit contents of a register pair can be incremented or

decremented by 1.

 Increment or decrement can be performed on any register or a

memory location.
 Arithmetic Instructions

Opcode Operand Description

INR R Increment register or memory by 1
M

 The contents of register or memory location are incremented by

1.

 The result is stored in the same place.

 If the operand is a memory location, its address is specified by

the contents of H-L pair.

 Example: INR B or INR M

Example

Instruction: INR E

Register contents Register contents after

before Execution Execution
E 1C h E 1D h

Note: Except Carry Flag, all flags are affected

depend upon the result.
 Arithmetic Instructions

Opcode Operand Description

INX R Increment register pair by 1

 The contents of register pair are incremented by 1.

 The result is stored in the same place.

 Example: INX H
Example

Instruction: INX D

Register contents Register contents after

before Execution Execution
DE A103 h
DE A104 h

Note: No Flags are affected.

 Arithmetic Instructions

Opcode Operand Description

DCR R Decrement register or memory by 1
M

 The contents of register or memory location are decremented

by 1.

 The result is stored in the same place.

 If the operand is a memory location, its address is specified by

the contents of H-L pair.

 Example: DCR B or DCR M

Example

Instruction: DCR M

Register contents Register contents after

before Execution Execution
HL 8500h HL 8500h

MEMORY MEMORY
84FF 7Ah 84FF 7Ah
8500 08h 8500 07h
8501 45h 8501 45h
8502 F4h 8502 F4h

Note: Except Carry Flag, all flags are

affected depend upon the result.
 Arithmetic Instructions

Opcode Operand Description

DCX R Decrement register pair by 1

 The contents of register pair are decremented by 1.

 The result is stored in the same place.

 Example: DCX H
Example

Instruction: DCX H

Register contents Register contents after

before Execution Execution
HL FFFF h HL FFFE h

Note: No Flags are affected.

 Logical Instructions

 These instructions perform logical operations on data stored in registers, memory

and status flags.

 The logical operations are:

 AND
 OR
 XOR
 Rotate
 Compare
 Complement
 AND, OR, XOR

 Any 8-bit data, or the contents of register, or memory location can

logically have
 AND operation

 OR operation

 XOR operation

 with the contents of accumulator.

 The result is stored in accumulator.
 Logical Instructions

Opcode Operand Description

ANA R Logical AND register or memory with
M accumulator

 The contents of the accumulator are logically ANDed with the

contents of register or memory.
 The result is placed in the accumulator.
 If the operand is a memory location, its address is specified by
the contents of H-L pair.
 S, Z, P are modified to reflect the result of the operation.
 CY is reset and AC is set.
 Example: ANA B or ANA M.
 Example

Instruction: ANA C

Register contents Register contents after

before Execution Execution

A 62 h A 42 h

C 4A h C 4A h

Flag: S=0, Z=0, AC=0 , 0 1 1 0 0 0 1 0 Flag: S=0, Z=0, AC=1

P=0 and CY=0 0100 1010 , P=1 and CY=0
0100 0010

Note: S, Z, P flags are affected during the execution

of AND instruction. CY=0 AC = 1
 Logical Instructions

Opcode Operand Description

ANI 8-bit data Logical AND immediate with
accumulator

 The contents of the accumulator are logically

ANDed with the 8-bit data.
 The result is placed in the accumulator.
 S, Z, P are modified to reflect the result.
 CY is reset, AC is set.
 Example: ANI 86H.
 Example

Instruction: ANI 15h

Register contents Register contents after

before Execution Execution
A 62 h A 00 h

Flag: S=0, Z=0, AC=0 , Flag: S=0, Z=1, AC=1 ,

P=0 and CY=0 0110 0010 P=1 and CY=0
0001 0101
0000 0000
 Logical Instructions

Opcode Operand Description

XRA R Exclusive OR register or memory with
M accumulator

 The contents of the accumulator are XORed with the contents of the register or memory.

 The result is placed in the accumulator.

 If the operand is a memory location, its address is specified by the contents of H-L pair.

 S, Z, P are modified to reflect the result of the operation.

 CY and AC are reset.

 Example: XRA B or XRA M.

 Example

Instruction: XRA E

Register contents Register contents after

before Execution Execution

A EE h A B4 h

E 5A h E 5A h

1110 1110
Flag: S=0, Z=0, AC=0
Flag: S=0, Z=0, 0101 1010 , P=1 and CY=0
AC=0 , P=0 and 1011 0100
CY=0

Note: S, Z, P flags are affected during the execution

of XOR instruction. CY=0 AC = 0
 Logical Instructions

Opcode Operand Description

ORA R Logical OR register or memory with
M accumulator

 The contents of the accumulator are logically ORed with the contents of the register or
memory.

 The result is placed in the accumulator.

 If the operand is a memory location, its address is specified by the contents of H-L pair.

 S, Z, P are modified to reflect the result.

 CY and AC are reset.

 Example: ORA B or ORA M.

 Example

Instruction: ORA C

Register contents Register contents after

before Execution Execution

A 62 h A 6A h

C 4A h C 4A h

0110 0010 Flag: S=0, Z=0, AC=0

Flag: S=0, Z=0, AC=0
, P=0 and CY=0
0100 1010 , P=1 and CY=0
0110 1010

Note: S, Z, P flags are affected during the execution

of OR instruction. CY=0 AC = 0
 Logical Instructions

Opcode Operand Description

ORI 8-bit data Logical OR immediate with accumulator

 The contents of the accumulator are logically ORed

with the 8-bit data.
 The result is placed in the accumulator.
 S, Z, P are modified to reflect the result.
 CY and AC are reset.
 Example: ORI 86H.
 Example

Instruction: ORI 15h

Register contents Register contents after

before Execution Execution
A 62 h A 77 h

Flag: S=0, Z=0, AC=0 Flag: S=0, Z=0, AC=0

, P=0 and CY=0 0110 0010 , P=1 and CY=0
0001 0101
0111 0111
 Rotate

 Each bit in the accumulator can be shifted either left or right to

the next position.
 Logical Instructions

Opcode Operand Description

RLC None Rotate accumulator left

 Each binary bit of the accumulator is rotated left by

one position.
 Bit D7 is placed in the position of D0 as well as in the
Carry flag.
 CY is modified according to bit D7.
 S, Z, P, AC are not affected.
 Example: RLC.
Example

Instruction: RLC
Register contents
before Execution

CY A
1 0 1 1 0 1 0 1 1

Register contents after

Execution
CY A
0 1 1 0 1 0 1 1 0
 Logical Instructions

Opcode Operand Description

RRC None Rotate accumulator right

 Each binary bit of the accumulator is rotated right

by one position.
 Bit D0 is placed in the position of D7 as well as in the
Carry flag.
 CY is modified according to bit D0.
 S, Z, P, AC are not affected.
 Example: RRC.
Example

Instruction: RRC
Register contents
before Execution

CY A
1 0 1 1 0 1 0 1 1

Register contents after

Execution
CY A
1 1 0 1 1 0 1 0 1
 Logical Instructions

Opcode Operand Description

RAL None Rotate accumulator left through carry

 Each binary bit of the accumulator is rotated left by

one position through the Carry flag.
 Bit D7 is placed in the Carry flag, and the Carry flag
is placed in the least significant position D0.
 CY is modified according to bit D7.
 S, Z, P, AC are not affected.
 Example: RAL.
Example

Instruction: RAL
Register contents
before Execution

CY A
0 1 1 1 0 0 0 0 1

Register contents after

Execution
CY A
1 1 1 0 0 0 0 1 0
Example

Instruction: RAR
Register contents
before Execution

CY A
0 1 1 1 0 0 0 0 1

Register contents after

Execution
CY A
1 0 1 1 1 0 0 0 0
 Compare

 Any 8-bit data, or the contents of register, or memory location can be

compares for:
 Equality

 Greater Than

 Less Than

with the contents of accumulator.

 The result is reflected in status flags.
 Logical Instructions

Opcode Operand Description

CMP R Compare register or memory with
M accumulator

 The contents of the operand (register or memory) are

compared with the contents of the accumulator.

 Both contents are preserved .

 The result of the comparison is shown by setting the

flags of the PSW as follows:
 Logical Instructions

Opcode Operand Description

CMP R Compare register or memory with
M accumulator

 if (A) < (reg/mem): carry flag is set

 if (A) = (reg/mem): zero flag is set

 if (A) > (reg/mem): carry and zero flags are reset.

 Example: CMP B or CMP M

 Example

Instruction: CMP L

Register contents Register contents after

before Execution Execution

A 45 h A 45 h

L 75 h C 75 h

0100 0101 Flag: Z=0 and CY=1

Flag: Z=0 and CY=0 0111 0101
1101 0000

Note: Besides Z and CY, All other Flags are also

affected.
 Logical Instructions

Opcode Operand Description

CPI 8-bit data Compare immediate with accumulator

 The 8-bit data is compared with the contents of

accumulator.

 The values being compared remain unchanged.

 The result of the comparison is shown by setting the

flags of the PSW as follows:
 Logical Instructions

Opcode Operand Description

CPI 8-bit data Compare immediate with accumulator

 if (A) < data: carry flag is set

 if (A) = data: zero flag is set

 if (A) > data: carry and zero flags are reset

 Example: CPI 89H

 Example

Instruction: CPI 45h

Register contents Register contents after

before Execution Execution
A 62 h A 62 h

Flag: Z=0 and CY=0 Flag: Z=0 and CY=0

0110 0010
0100 0101
0001 1101
 Logical Instructions

Opcode Operand Description

CMA None Complement accumulator

 The contents of the accumulator are complemented.

 No flags are affected.
 Example: CMA.
Example

Instruction: CMA

Register contents Register contents after

before Execution Execution
A 9A h A 65 h

1001 1010
0110 0101

Note: No Flags are affected.

 Logical Instructions

Opcode Operand Description

XRI 8-bit data XOR immediate with accumulator

 The contents of the accumulator are XORed with the

8-bit data.
 The result is placed in the accumulator.
 S, Z, P are modified to reflect the result.
 CY and AC are reset.
 Example: XRI 86H.
 Example

Instruction: XRI 18h

Register contents Register contents after

before Execution Execution
A C3 h A DB h

Flag: S=0, Z=0, AC=0 , Flag: S=0, Z=0, AC=0

P=0 and CY=0 1100 0011 , P=1 and CY=0
0001 1000
1101 1011
 Complement

 The contents of accumulator can be complemented.

 Each 0 is replaced by 1 and each 1 is replaced by 0.

 Logical Instructions

Opcode Operand Description

CMC None Complement carry

 The Carry flag is complemented.

 No other flags are affected.
 Example: CMC.
 Logical Instructions

Opcode Operand Description

STC None Set carry

 The Carry flag is set to 1.

 No other flags are affected.
 Example: STC.
 Branching Instructions

 The branching instruction alter the normal sequential flow.

 These instructions alter either unconditionally or conditionally.

 Branching Instructions

Opcode Operand Description

JMP 16-bit address Jump unconditionally

 The program sequence is transferred to the memory

location specified by the 16-bit address given in the
operand.
 Example: JMP 2034 H.
Example

Instruction: JMP 8500h

Register contents Register contents after

before Execution Execution
PC 8000h PC 8500 h

Note: No Flags are affected.

 Branching Instructions

Opcode Operand Description

Jx 16-bit address Jump conditionally

 The program sequence is transferred to the memory

location specified by the 16-bit address given in the
operand based on the specified flag of the PSW.
 Example: JZ 2034 H.
 Jump Conditionally

Opcode Description Status Flags

JC Jump if Carry CY = 1
JNC Jump if No Carry CY = 0
JP Jump if Positive S=0
JM Jump if Minus S=1
JZ Jump if Zero Z=1
JNZ Jump if No Zero Z=0
JPE Jump if Parity Even P=1
JPO Jump if Parity Odd P=0
 Branching Instructions

Opcode Operand Description

CALL 16-bit address Call unconditionally

 The program sequence is transferred to the memory

location specified by the 16-bit address given in the
operand.
 Before the transfer, the address of the next instruction after
CALL (the contents of the program counter) is pushed onto
the stack.
 Example: CALL 2034 H.
 Example

Instruction: CALL 8500h

Register contents Register contents after

before Execution Execution
PC 8000h PC 8500 h

SP 1001 h
STACK
1000
SP 1001 00h
SP 1002 80h

SP 1003 9Ch

Note: No Flags are affected.

 Branching Instructions

Opcode Operand Description

Cx 16-bit address Call conditionally

 The program sequence is transferred to the memory

location specified by the 16-bit address given in the
operand based on the specified flag of the PSW.
 Before the transfer, the address of the next instruction
after the call (the contents of the program counter) is
pushed onto the stack.
 Example: CZ 2034 H.
 Call Conditionally

Opcode Description Status Flags

CC Call if Carry CY = 1

CNC Call if No Carry CY = 0

CP Call if Positive S=0

CM Call if Minus S=1

CZ Call if Zero Z=1

CNZ Call if No Zero Z=0

CPE Call if Parity Even P=1

CPO Call if Parity Odd P=0

 Branching Instructions

Opcode Operand Description

RET None Return unconditionally

 The program sequence is transferred from the subroutine

to the calling program.
 The two bytes from the top of the stack are copied into the
program counter, and program execution begins at the new
address.
 Example: RET.
Example

Instruction: RET

Register contents Register contents after

before Execution Execution
PC 8000h PC 9000 h

SP 1001 h SP 1003 h
STACK
STACK
1000
1001 1000
00
1001
1002 90h
1002
1003 9Ch
1003 9Ch
Note: No Flags are affected.
 Branching Instructions

Opcode Operand Description

Rx None Call conditionally

 The program sequence is transferred from the

subroutine to the calling program based on the
specified flag of the PSW.
 The two bytes from the top of the stack are copied into
the program counter, and program execution begins at
the new address.
 Example: RZ.
 Return Conditionally

Opcode Description Status Flags

RC Return if Carry CY = 1

RNC Return if No Carry CY = 0

RP Return if Positive S=0

RM Return if Minus S=1

RZ Return if Zero Z=1

RNZ Return if No Zero Z=0

RPE Return if Parity Even P=1

RPO Return if Parity Odd P=0

 Branching Instructions

Opcode Operand Description

RST 0–7 Restart (Software Interrupts)

 The RST instruction jumps the control to one of eight

memory locations depending upon the number.
 These are used as software instructions in a program to
transfer program execution to one of the eight
locations.
 Example: RST 3.
 Restart Address Table

Instructions Restart Address

RST 0 0000 H

RST 1 0008 H

RST 2 0010 H

RST 3 0018 H

RST 4 0020 H

RST 5 0028 H

RST 6 0030 H

RST 7 0038 H
 Control Instructions

The control instructions control the operation

of microprocessor.
 Control Instructions

Opcode Operand Description

NOP None No operation

 No operation is performed.
 The instruction is fetched and decoded but no
operation is executed.
 Example: NOP
 Control Instructions

Opcode Operand Description

HLT None Halt

 The CPU finishes executing the current instruction

and halts any further execution.
 An interrupt or reset is necessary to exit from the halt
state.
 Example: HLT
 Control Instructions

Opcode Operand Description

DI None Disable interrupt

 The interrupt enable flip-flop is reset and all the

interrupts except the TRAP are disabled.
 No flags are affected.
 Example: DI
 Control Instructions

Opcode Operand Description

EI None Enable interrupt

 The interrupt enable flip-flop is set and all interrupts

are enabled.
 No flags are affected.
 This instruction is necessary to re-enable the
interrupts (except TRAP).
 Example: EI
 Control Instructions

Opcode Operand Description

RIM None Read Interrupt Mask

 This is a multipurpose instruction used to read the status of

interrupts 7.5, 6.5, 5.5 and read serial data input bit.
 The instruction loads eight bits in the accumulator with the
following interpretations.
 Example: RIM
RIM Instruction
 Control Instructions

Opcode Operand Description

SIM None Set Interrupt Mask

 This is a multipurpose instruction and used to implement the

8085 interrupts 7.5, 6.5, 5.5, and serial data output.
 The instruction interprets the accumulator contents as
follows.
 Example: SIM
SIM Instruction