V – M – PEOs DOCUMENT ECET/ECE/FT 02

ELURU COLLEGE OF ENGINEERING & TECHNOLOGY

Department of Electronics and Communication Engineering
VISION – MISSION - PEOs

Vision of the Institute To Achieve Excellence in Engineering Education

M-1:- To deliver quality education through good

Mission of the Institute infrastructure, facilities and committed staff.

M-2:- To train students as Proficient, Competent and

Socially responsible Engineers.

M-3:- To promote the Research and Development

activities among faculty and students for
betterment of society
V – M – PEOs DOCUMENT ECET/ECE/FT 02

ELURU COLLEGE OF ENGINEERING & TECHNOLOGY

Department of Electronics and Communication Engineering
VISION – MISSION - PEOs

Developing Technically Competent Electronics and

Vision of the Department Communication Engineers with Academic Excellence,
Leadership Skills and Ethical Values to serve the Society.

DM-1:- To impart adequate fundamental knowledge in all

basic sciences and Electronics and
Communication Engineering to satisfy the stakes holders
Mission of the Department
DM-2:- To mould students as problem-solving individuals
and lifelong learners
DM-3:- To train students on modern technologies through
Research and Industry-Institute Collaboration.
DM-4:- To develop Teamwork, Professional ethics and
Leadership qualities in students for the
betterment of Society

PEO’S :
The Graduates of ECE will be able to :

PEO1. Exhibit Strong Foundation in

Mathematics, Science and Electronics and
Program
Communication Engineering Fundamentals to
Educational
Solve Engineering Problems as Per Industry
Objectives(PEOs)
Needs.

PEO2. Pursue the Higher Education & Research.

PEO3. Communicate Effectively, Demonstrate

Leadership Qualities and Exhibit Professional
Conduct in their Career

PEO4. Adapt Technological Advancements by

Continuous Learning.
V – M – PEOs DOCUMENT ECET/CSE/FT 04

ELURU COLLEGE OF ENGINEERING & TECHNOLOGY

Course Data Sheet

Name of the Program : B.Tech in Electronics & Communication Engineering Academic Year: 2023-
24 Year &Semester : III-II No of Credits : 3
Name of the Course : VLSI Design Code : R2032042
Section : A&B Regulation : R20
Course Area/Module : Core No of students registered : 132
Name of the Faculty : B.Durga Rao Designation: Asst. Professor

Course Syllabus

UNIT I
INTRODUCTIO NAND BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS: VLSI Design Flow,
Introduction to IC technology, Fabrication process: nMOS, pMOS and CMOS. Ids versus Vds Relationships,
Aspects of MOS transistor Threshold Voltage, MOS transistor Trans, Output Conductance and Figure of Merit.
nMOS Inverter, Pull-up to Pulldown Ratio for nMOS inverter driven by another nMOS inverter, and through one
or more pass transistors. Alternative forms of pull-up, The CMOS Inverter, Latch-up in CMOS circuits, Bi-
CMOS Inverter, Comparison between CMOS and BiCMOS technology, MOS Layers, Stick Diagrams, Design
Rules and Layout, Layout Diagrams for MOS circuits

UNIT II
BASIC CIRCUIT CONCEPTS: Sheet Resistance, Sheet Resistance concept applied to MOS transistors and
Inverters, Area Capacitance of Layers, Standard unit of capacitance, some area Capacitance Calculations, The
Delay Unit, Inverter Delays, driving large capacitive loads, Propagation Delays, Wiring Capacitances, Choice of
layers. SCALING OF MOS CIRCUITS: Scaling models and scaling factors, Scaling factors for device
parameters, Limitations of scaling, Limits due to sub threshold currents, Limits on logic levels and supply voltage
due to noise and current density. Switch logic, Gate logic.

UNIT III
BASIC BUILDING BLOCKS OF ANALOG IC DESIGN: Regions of operation of MOSFET, Modelling of
transistor, body bias effect, biasing styles, single stage amplifier with resistive load, single stage amplifier with
diode connected load, Common Source amplifier, Common Drain amplifier, Common Gate amplifier, current
sources and sinks.
.
UNIT IV
CMOS COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUIT DESIGN:
Static CMOS Design: Complementary CMOS, Rationed Logic, Pass-Transistor Logic.
Dynamic CMOS Design: Dynamic Logic-Basic Principles, Speed and Power Dissipation of Dynamic
Logic, Issues in Dynamic Design, Cascading Dynamic Gates, Choosing a Logic Style, Gate Design in
the Ultra Deep-Submicron Era, Latch Versus Register, Latch based design, timing decimation,
positive feedback, in stability, Meta stability, multiplexer based latches, Master-Slave Based Edge
Triggered Register, clock to q delay, setup time, hold time, reduced clock load master slave registers,
Clocked CMOS register. Cross coupled NAND and NOR, SR Master Slave register, Storage
mechanism, pipelining.

UNIT V
FPGA DESIGN: FPGA design flow, Basic FPGA architecture, FPGA Technologies, Introduction to FPGA
Families.
INTRODUCTIONTOADVANCEDTECHNOLOGIES: Giga-scale dilemma, Short channel effects, High–k,
Metal Gate Technology, Fin-FET, TFET.
Textbooks:
1. Essentials of VLSI Circuits and Systems – Kamran Eshraghian, Douglas and A.Pucknell and Sholeh
Eshraghian, Prentice-Hall of India Private Limited, 2005 Edition.
2. Design of Analog CMOS Integrated Circuits by Behzad Razavi, McGraw Hill, 2003
3. Digital Integrated Circuits, Jan M.Rabaey, Anantha Chandrakasan and Borivoje Nikolic, 2nd
edition, 2016.

REFERENCE BOOKS:
1. “Introduction to VLSI Circuits and Systems”, John P.Uyemura, John Wiley&Sons, reprint 2009.
2. Integrated Nano electronics: Nano scale CMOS, Post-CMOS and Allied Nano technologies Vinod
Kumar Khanna, Springer India, 1stedition, 2016.
3. Fin-FETs and other multi-gate transistors, Colinge JP, Editor NewYork, Springer, 2008.
COURSE OBJECTIVES

S.No Course Objectives (Cobs)

To provide the knowledge of basic data structures and their

2032042.1 implementations.
To understand importance of data structures in context of writing
2032042.2 efficient programs.

To develop skills to apply appropriate data structures in problem

2032042.3 solving.

COURSE OUTCOME
At the end of the Course/Subject, the students will be able to :

CO Bloom's Taxonomy
Course Outcomes(COs) POS* PSOs*
Number & Level
Understand the basic electrical
properties of MOS circuits, Understanding
R2032042.1 including Ids vs. Vds relationships, 1 1,2
(BTL2)
threshold voltage, and output
Calculate sheet resistance and area
R2032042.2 capacitance for MOS transistors 1 1,2 Applying(BTL3)
and inverters.

Design and analyze single-stage

R2032042.3 amplifiers with resistive and diode- 2 1,2 Applying(BTL3)
connected loads.

Communicate CMOS circuit

R2032042.4 design principles and analysis 2 1,2 Analyzing(BTL4)
results effectively.

1. Design a digital system using an

Analyzing(BTL4)
R2032042.5 FPGA to meet specified 2 1,2
performance requirements.
 Course Outcome vs POs Mapping:

Course Out
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
Come

R2032042.1 3 - - - - - - - - - - -

R2032042.2 3 - - - - - - - - - - -

- 3 - - - - - - - - - -
R2032042.3

R2032042.4 - 3 - - - - - - - - - -

R2032042.5 - 3 - - - - - - - - - -

Total 3 9 - - - - - - - - - -

Average 3 3 - - - - - - - - - -

Justification of Mapping of Course Outcome with Program Outcomes:

1. R2032042.1 is mapped to PO1 as students can understand the basic concepts of

Abstract data types.
2. R2032042.2 is strongly mapped to PO1 as students can apply searching and sorting
techniques to find out the solutions by calculating time and space complexity.
3. R2032042.3 is strongly mapped to PO2 as students can categorize various linear data
structure algorithms like lists, stacks and queues.
4. R2032042.4 is strongly mapped to PO2 as students can analyze the solutions with
algorithms on trees.
5. R2032042.5 is strongly mapped to PO2 as students can identify the solutions with
various techniques of hash tables.
 Course Outcome vs PSOs Mapping:

Courses Out Comes PSO1 PSO2

R2032042.1 3 3
R2032042.2 3 3
R2032042.3 3 3
R2032042.4 3 3
R2032042.5 3 3
Total 15 12
Average 3 3

Justification of Mapping of Course Outcome with Program Specific Outcomes:

1. PSO1- R2032042.2, R2032042.3, R2032042.4, and R2032042.5 are strongly mapped as
it involves various algorithms and techniques in data structures.
2. PSO2- R2032042.2, R2032042.3, R2032042.4, and R2032042.5 are strongly mapped as
the knowledge of data mining for research & higher education.

Mention Gaps Identified (Missing Content of syllabus / Industry/Profession Requirements) if any:

S No Description Proposed action Mapped CO PO’S & PSO’S

Representation and PPT presentation
1 Applications of with explanation R2032042.4 PO2&PSO1,PSO2
Graphs will be given.

Mention Gaps Identified (POs) if any :

S No Gap identified Relevant to Proposed action

1 NIL

Topics beyond Syllabus/Advanced Topics/Design:

 Regarding Non-linear data structures, Graphs and its applications.

 In Trees, AVL Trees insertion, deletion and rotation.
 Delivery/Instructional Methodologies:

1. Lecture
2. Questioning & Discussion

Handouts:
 Lecture Notes

Assessment Methodologies-Direct
🞜 Assignments
🞜 Tests/Model exams
🞜 Univ. Examination

Course Outcome Learning Assessment Methodologies-Indirect

🞜 Assessment of Course Outcomes (By Feedback, Once)
🞜 Student Feedback on Faculty (Twice)

Innovative Teaching/Learning/Evaluation Processes:

🞜 Adaptive teaching is followed to focus on the whole class
🞜 Tutorial classes are conducted to improve problem solving skills and motivate slow learners
🞜 Conducting remedial classes for slow learners to improve their academic performance
🞜 Standard cognitive tests are conducted regularly on completion of each unit.

Course Attainment Target:

INTERNAL EXTERNAL
Set Target %
55 45
50% or less number of 50% or less number of
students scoring more than students scoring more than
Attainment Level 1
55% marks in internal 45% marks in External
examination examination
51% to 69% of students 51% to 69% of students
Attainment Level 2 scoring more than 55% marks scoring more than 45% marks
in internal examination in External examination
70% & above number of 70% & above number of
students scoring more than students scoring more than
Attainment Level 3
55% marks in internal 45% marks in External
examination examination

Signature of Course Coordinator Head of Department

Date:
 COURSE WORK TIME TABLE ECET/CSE/FT 05

ELURU COLLEGE OF ENGINEERING & TECHNOLOGY

Department of Electronics & Communication Engineering
COURSE WORK TIME TABLE

Name of the Program : B.Tech in Electronics & Communication Engineering

Academic Year: 2023-24
Year & Semester: III Year II Semester Section: A, B
Name of the Course: VLSI Code : R2032042
No of Credits : 03 Regulation : R20
Name of the Course Area/Module: Core No of students registered: 132
Faculty: Mr B.Durga Rao Designation: Asst. Professor

YOUR TIME TABLE OF THIS PARTICULAR COURSE

STAFF B.Durga
NAME Rao SUB: VLSI

DAY 1 2 3 4 5 6

MON IIIA

TUE IIIA IIIB

WED IIIB

THU IIIA IIIB

FRI IIIB IIIA

SAT

Signature of the Course Coordinator/Faculty Signature of Head of the Department

Date: Date: