ADVANCED MICROPROCESSOR (ELECTIVE-I)

16-bit Microprocessor - Intel 80286.

1.1 Salient features, Internal architecture, Register organization

(General purpose register, segment register, status and control
register, instruction pointer, segment descriptor cache register)
1.2 Addressing mode such as Real, Protected Virtual Addressing mode,
Selector, Descriptors and its types, LDT, GDT, IDT, privilege protections
and task switching.
1.3 Operations of 80286 in Real and PVAM.

1.1 Salient Features of 80286

- The 80286 is the first member of the family of advanced microprocessors with memory
management and protection abilities.
- The 80286 CPU, with its 24-bit address bus is able to address 16 Mbytes of physical memory.
Various versions of 80286 are available that runs on 12.5 MHz, 10 MHz and 8 MHz clock
frequencies.

- 80286 is upwardly compatible with 8086 in terms of instruction set.

- 80286 have two operating modes namely real address mode and virtual address mode.
- In real address mode, the 80286 can address up to 1Mb of physical memory address like 8086.
- In virtual address mode, it can address up to 16 Mb of physical memory address space and 1 GB of
virtual memory address space.
- The instruction set of 80286 includes the instructions of 8086 and 80186.
- 80286 has some extra instructions to support operating system and memory management.
- In protected virtual address mode, it is source code compatible with 8086.
The performance of 80286 is five times faster than the standard 8086.
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Internal 80286 architecture.

The 80286 was designed for multi-user systems with multitasking applications, including
communications and real-time process control.
- It had 134,000 transistors and consisted of four independent units: address unit, bus unit, instruction
unit and execution unit.
- These were organized into a pipeline, significantly increasing performance.
- It was produced in a 68-pin package including PLCC (Plastic Leaded Chip Carrier), LCC (Leadless chip
carrier) and PGA (Pin Grid Array) packages.
- The Intel 80286 had a 24-bit address bus and was able to address up to 16 MB of RAM, compared to
1 MB for its predecessor. However cost and initial rarity of software using the memory above 1 MB
meant that 80286 computers were rarely shipped with more than one megabyte of RAM.
- 80286 Architecture contains 4 separate processing units.
(1) Bus Unit (BU)
(2) Instruction Unit (IU)
(3) Address Unit (AU)
(4) Execution Unit (EU)
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Bus Unit (BU):

It has address latches, data transceivers, bus interface and circuitry, instruction pre-fetcher, processor
extension interface and 6 byte instruction queue.
Functions :
- To perform all memory and I/O read and write.
- To pre-fetch the instruction bytes.
- To control the transfer of data to and from processor extension de vices like 80287 math co-
processor.
- Whenever BU is not using the buses for the operation, it pre-fetches the instruction bytes and put
them is a 6 byte pre-fetch queue.
Instruction Unit (IU):
It has 3 decoded instruction queue and instruction decoder.
Functions:
- It fully decodes up to three prefetched instructions and holds them in a queue.
- So that EU can access them.
- It helps the processor to speed up, as pipelining of instruction is done.
Execution Unit (EU):
It includes ALU, registers and the Control unit. Registers are general purpose, index, pointer, flag register
and 16 –bit Machine Status Word (MSW).
Functions:
- To sequentially execute the instructions received from the instruction unit.
- ALU result is either stored in register bank or sent over the data bus.
Address Unit (AU):
It consists of segment registers, offset address and a physical address adder.
Functions:
- Compute the physical address that will be sent out to the memory or I/O by BU.
- 80286 operate in two different modes
1. real address mode
2. Protected virtual address mode.
- When used in Real address mode, AU computes the address with segment base and offset like
8086. Segment register are CS, DS, ES and SS hold base address. IP, BP, SI, DI , SP hold offset.
- Maximum physical space allowed in this mode is 1MB.
- When 80286 operate in protected mode, the address unit acts as MMU.
- All 24 address lines used and can access up to 16MB of physical memory.
- If descriptor table scheme is used it can address up to 1GB of virtual memory.
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Register Organization of 80286

The 80286 CPU contains almost the same set of registers, as in 8086, namely
1. Eight 16-bit general purpose registers (AX, BX, CX, DX)
2. Four 16-bit segment registers (CS, SS, DS, ES)
3. Status and control registers (SP, BP, SI, DI)
4. Instruction Pointer (IP)
5. Two 16-bit register - FLAGS, MSW
6. Two 16-bit register - LDTR and TR
7. Two 48-bit register - GDTR and IDTR
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Flag Register of 80286

SF- Sign Flag: This flag is set, when the result of any computation is negative. For signed computations the sign
flag equals the MSB of the result.

ZF- Zero Flag: This flag is set, if the result of the computation or comparison performed by the previous instruction is
zero.

PF- Parity Flag: This flag is set to 1, if the lower byte of the result contains even number of 1’s.

CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a borrow in case of subtraction.

AF-Auxilary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit three during addition, or borrow
for the lowest nibble, i.e, bit three, during subtraction.

OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large enough to
accommodate in a destination register. The result is of more than 7-bits in size in case of 8-bit signed operation
and more than 15-bits in size in case of 16-bit sign operations, and then the overflow will be set.

TF- Tarp Flag: If this flag is set, the processor enters the single step execution mode. The processor executes
the current instruction and the control is transferred to the Trap interrupt service routine.

IF- Interrupt Flag: If this flag is set, the mask able interrupts are recognized by the CPU, otherwise they are ignored.

D- Direction Flag: This is used by string manipulation instructions. If this flag bit is ‘0’, the string is processed beginning from the lowest
address to the highest address, i.e., auto incrementing mode. Otherwise, the string is processed from the highest
address towards the lowest address, i.e., auto decrementing mode.

IOPL – I/O Privilege Level flag: 2 –bits are used in protected mode. It holds the privilege level from 0 to 3. ‘0’ assigns to
highest privilege whereas ‘3’ assigns to lower privilege level.

NT: Nested Task flag: It is used in protected mode. Bit is set when one task invokes another task.
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1.2 /1.3Operating modes of 80286 microprocessor

80286 operates in two modes:

In real address mode, this microprocessor acts as a version of 8086 which is quite
faster. Also without any special modification, the instruction programmed for 8086 can
be executed in 80286. It offers memory addressability of 1 MB of physical memory.
The protected virtual-address mode of 80286 supports multitasking because multiple
programs can be executed using virtual memory. This mode of 80286 offers memory
addressability of 16 MB of physical memory along with 1 GB of virtual memory.

Real Address Mode (Just act as a fast 8086).

- Instruction set is upwardly compatible
- Because of extra pipelining and other circuit level improvements, in real address mode
also, the 80286 operates at a much faster rate than 8086, although functionally they
work in an identical fashion.
- As in 8086, the physical memory is organized in terms of segments of 64Kbyte
maximum size.
- In the real mode the first 1Kbyte of memory starting from address 0000H to 003FFH is
reserved for interrupt vector table.
- The addresses from FFFF0H to FFFFFH are reserved for system initialization.
- When the 80286 is reset, it always starts the execution in real address mode.
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- In real address mode, it initializes the IP and other registers of 80286.

Protected Virtual Address Mode (PVAM)

- 80286 is the first processor to support the concepts of virtual memory and memory
management.
- The concept of Virtual Memory is implemented using Physical memory that the CPU can
directly access and secondary memory that is used as storage for data and program,
which are stored in secondary memory initially.
- The complete virtual memory is mapped on to the 16Mbyte physical memory.
- If a program larger than 16Mbyte is stored on the hard disk and is to be executed, if it is
fetched in terms of data or program segments of less than 16Mbyte in size into the
program memory by swapping sequentially as per sequence of execution.
- The 80286 is able to address 1 GB (230 bytes) of virtual memory.
- 80286 uses the 16-bit content of a segment register as a selector to address a
descriptor stored in the physical memory.
- The descriptor is a block of contiguous memory locations containing information of a
segment, like segment base address, segment limit, segment type, privilege level,
segment availability in physical memory descriptor type and segment.
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- Hardware reset is the only way to come out of protected mode

Descriptor table
Descriptor is a identifier of a program segment or page.
- A segment cannot be accessed, if its descriptor does not exist in either LDT or GDT.
- Set of descriptor (descriptor table) arranged in a proper sequence describes the complete program.
- The descriptor is a block of contiguous memory location containing information of a segment, like
i. Segment base address
ii. Segment limit
iii. Segment type
iv. Privilege level – prevents unauthorized access
v. Segment availability in physical memory
vi. Descriptor type
vii. Segment use by another task
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Requirement of Descriptor Table:

- The descriptor describes the location, length, and access rights of the segment of memory.
- The selector, located in the segment register, selects one of descriptors from one of two tables of
descriptors.

Global Descriptor Table (GDT):

- The 80286 has a single Global Descriptor Table (GDT) which is shared between all tasks and
addresses up to 512MB of the virtual address space.
- The Global Descriptor Table or GDT is a data structure used by Intel x86-family processors
starting with the 80286 in order to define the characteristics of the various memory areas used
during program execution, including the base address, the size and access privileges like execute -
ability and write-ability.
Local Descriptor Table (LDT):
- Each task will have its own Local Descriptor Table (LDT) which is a private 512MB of address space.
- LDT is essential to implement separate address spaces for multiple processes.
- The operating system will switch the current LDT when scheduling a new process, using the LDT
machine instruction.
Descriptor Table (LDT):
IDT used to store interrupt gates and task gates

- LIDT instruction is used to Load Interrupt Descriptor table.

Differentiate LDT and GDT:

- LDT is actually defined by a descriptor inside the GDT, while the GDT is directly defined by a linear
address.
- The lack of symmetry between both tables is underlined by the fact that the current LDT can be
automatically switched on certain events, notably if TSS-based multitasking is used, while this is
not possible for the GDT.
- The LDT also cannot store certain privileged types of memory segments.
- The LDT is the sibling of the Global Descriptor Table (GDT) and similarly defines up to 8191
memory segments accessible to programs.
- LDT (and GDT) entries which point to identical memory areas are called aliases.
- Instruction to load GDT is LGDT(Load Global Descriptor Table) and instruction to load LDT is
LLDT(Load Global Descriptor Table). Both are privileged instructions.
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Pin Diagram of 80286.

The pin interface diagram of 80286 is as follows:-

Signals/pins are divide into four groups
1. Memory I/O interfaces signals
2. Interrupt interface signals
3. DMA interface signals
4. Co-processor interface signals

Figure: 80286 Interface Diagram

- VCC is the system power supply connection for 10%, +5.0 V.

- VSS is the system ground connection.
- CLK is System Clock.
- RESET the companion reset output pin (goes high for a reset) connects to system peripherals to
initialize them whenever the input goes low.
- NMI is a non-mask able interrupt input. It is positive edge-triggered and always active. When NMI is
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activated, it uses interrupt vector 2.

- A0-A23: Unidirectional Address bus.
- D0- D15: Bidirectional Data bus.
- The bus high enable pin indicates (when a logic 0) that valid data are transferred
through data bus.
- PEREQ and PEACK#: Processor extension/co-processor request and acknowledge.
- PEREQ input request the 80286 to perform data transfer for a processor
extension/co-processor.
- Co-processor cannot transfer the data over the data bus by itself. Whenever it
needs read or write the data from memory, it indicates 80286 to initiate the data
transfer by making PEREQ signal high.
- PEACK# indicates co-processor that data transfer has started.
- Busy# indicates processor extension is busy with allotted job. Busy goes low
indicates 80286 to suspend the execution and wait until busy becomes high.
- Error# signal indicates the error is detected by the co-processor. So when low,
80286 need to perform the processor extension interrupt while executing WAIT
instruction.
- The lock pin is an output controlled by the LOCK prefix. If an instruction is prefixed
with LOCK, the pin becomes a logic 0 for the duration of the locked instruction.
- S0 and S1 are bus cycle status output pin
- M/IO is memory I/O select pin
- COD/INTA# is code interrupt acknowledgement pin
HOLD is bus hold input signal and HLDA/HOLDA is hold acknowledgement output signal