Memory and Programmable Logic

Chapter 7
7-1 Introduction
◼ Memory
◼ information storage
◼ a collection of cells store binary information
◼ RAM – Random-Access Memory
◼ read operation
◼ write operation
◼ ROM – Read-Only Memory
◼ read operation only
◼ a programmable logic device

Digital Circuits 2
 ◼ Programmable Logic Device (PLD)
◼ ROM
◼ PLA – programmable logic array
◼ PAL – programmable array logic
◼ FPGA – field-programmable gate array
◼ programmable logic blocks
◼ programmable interconnects

Fig. 7.1
Conventional and array logic diagrams for OR gates
Digital Circuits 3
 7-2 Random-Access Memory
◼ A memory unit
◼ stores binary information in groups of bits (words)
◼ 8 bits (a byte), 2 bytes, 4 bytes
◼ Block diagram

Fig. 7.2
Block diagrams of a memory unit

Digital Circuits 4
 ◼ A 1024  16 Memory

Fig. 7.3
Contents of a
1024  16
memory
Digital Circuits 5
Write and Read Operations
◼ Write operation
• Apply the binary address to the address lines
• Apply the data bits to the data input lines
• Activate the write input
◼ Read operation
• Apply the binary address to the address lines
• Activate the read input

Digital Circuits 6
Memory Description in HDL
◼ Examples

Digital Circuits 7
HDL Example 7.1

Digital Circuits 8
Timing Waveforms
◼ The operation of the memory unit is
controlled by an external device
◼ The access time
◼ the time required to select a word and read it
◼ The cycle time
◼ the time required to complete a write operation
◼ Read and write operations must synchronized
with an external clock

Digital Circuits 9
 ◼ CPU clock – 50 MHz
◼ The access/cycle time < 50 ns
◼ A write cycle

Fig. 7.4
Memory cycle timing waveforms Digital Circuits 10
 ◼ A read cycle

Fig. 7.4
Memory cycle timing waveforms (cont.)
Digital Circuits 11
Types of Memories
◼ Static
◼ Information are stored in latches
◼ remains valid as long as power is applied
◼ short read/write cycle
◼ Dynamic
◼ Information are stored in the form of charges on
capacitors
◼ the stored charge tends to discharge with time
◼ need to be refreshed (read and write back)
◼ reduced power consumption
◼ Larger memory capacity

Digital Circuits 12
◼ Volatile
◼ lose stored information when power is turned off
◼ SRAM, DRAM
◼ Non-volatile
◼ Retains its stored information after the removal of
power
◼ ROM
◼ EPROM, EEPROM
◼ Flash memory

Digital Circuits 13
 7-3 Memory Decoding
◼ A memory unit
◼ the storage components
◼ the decoding circuits to select the memory word
◼ A memory cell

Fig. 7.5
Memory cell
Digital Circuits 14
Internal Construction
◼ A RAM of m words and n bits per word
◼ m*n binary storage cells
◼ Decoding circuits to select individual words
◼ k-to-2k decoder

Digital Circuits 15
 ◼ A 4  4 RAM

Fig. 7.6
Diagram of a 4  4 RAM
Digital Circuits 16
Coincident Decoding
◼ A two-dimensional selection scheme
◼ reduce the complexity of the decoding circuits

Fig. 7.7
Two-dimensional
decoding structure for
a 1K-word memory

Digital Circuits 17
◼ A 10-to-1024 decoder
◼ 1024 AND gates with 10 inputs per gates
◼ Two 5-to-32 decoders
◼ 2 * (32 AND gates with 5 inputs per gates)
◼ Reduce the circuit complexity and the cycle time

Digital Circuits 18
Address Multiplexing
◼ The reduce the number of pins in the IC
package
◼ consider a 64M1 DRAM
◼ 26-bit address lines
◼ Multiplex the address lines in one set of address
input pins

Digital Circuits 19
◼ An examples
◼ RAS – row address strobe
◼ CAS – column address strobe

Fig. 7.8
Address multiplexing
for a 64K DRAM
Digital Circuits 20
 Random Access Memory 第三版內容，參考用!
RAS, CAS Addressing
Even to read 1 bit, an entire 64-bit row is read!

Separate addressing into two cycles: Row Address, Column Address

Saves on package pins, speeds RAM access for sequential bits!

Addre ss Row Addre ss Col Addres s

RAS
Read Cycle
CAS

Dout Valid
Read Row
Row Address Latched
Read Bit Within Row Tri-state
Column Address Latched Outputs
Digital Circuits 21
 Random Access Memory 第三版內容，參考用!
Write Cycle Timing Addres s Row Addres s Col Address

RAS

(1) Latch Row Address CAS

Read Row
WE

(2) WE low
Din Valid

(3) CAS low: replace data bit

(4) RAS high: write back the modified row

(5) CAS high to complete the memory cycle

Digital Circuits 22
7-4 Error Detection And Correction
◼ Improve the reliability of a memory unit
◼ A simple error detection scheme
◼ a parity bit (Sec. 3-9)
◼ a single bit error can be detected, but cannot be
corrected
◼ An error-correction code
◼ generates multiple parity check bits
◼ the check bits generate a unique pattern, called a
syndrome
◼ the specific bit in error can be identified

Digital Circuits 23
Hamming Code
◼ k parity bits are added to an n-bit data word
◼ (2k –1  n + k)
◼ The bit positions are numbered in sequence from
1 to n + k
◼ Those positions numbered as a power of 2 are
reserved for the parity bits
◼ The remaining bits are the data bits

Digital Circuits 24
◼ Example: 8-bit data word 11000100
◼ Include 4 parity bits and the 8-bit word  12 bits
2k –1  n + k, n = 8  k = 4
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
P1 P2 1 P4 1 0 0 P8 0 1 0 0
◼ Calculate the parity bits: even parity ⎯ assumption
P1 = XOR of bits (3, 5, 7, 9, 11) = 1  1  0  0  0 = 0
P2 = XOR of bits (3, 6, 7, 10, 11) = 1  0  0  1  0 = 0
P4 = XOR of bits (5, 6, 7, 12) = 1  0  0  0 = 1
P8 = XOR of bits (9, 10, 11, 12) = 0  1  0  0 = 1
◼ Store the 12-bit composite word in memory.
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
0 0 1 1 1 0 0 1 0 1 0 0

Digital Circuits 25
◼ When the 12 bits are read from the memory
◼ Check bits are calculated
C1 = XOR of bits (1, 3, 5, 7, 9, 11)
C2 = XOR of bits (2, 3, 6, 7, 10, 11)
C4 = XOR of bits (4, 5, 6, 7, 12)
C8 = XOR of bits (8, 9, 10, 11, 12)

◼ If no error has occurred

Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
0 0 1 1 1 0 0 1 0 1 0 0
 C = C8C4C2C1 = 0000

Digital Circuits 26
◼ One-bit error
◼ error in bit 1
◼ C1 = XOR of bits (1, 3, 5, 7, 9, 11) = 1
◼ C2 = XOR of bits (2, 3, 6, 7, 10, 11) = 0
◼ C4 = XOR of bits (4, 5, 6, 7, 12) = 0
◼ C8 = XOR of bits (8, 9, 10, 11, 12) = 0
◼ C8C4C2C1 = 0001
◼ error in bit 5
◼ C8C4C2C1 = 0101
◼ Two-bit error
◼ errors in bits 1 and 5
◼ C8C4C2C1 = 0100

Digital Circuits 27
◼ The Hamming code can be used for data of
nay length
◼ k check bits
◼ 2k –1  n + k

Digital Circuits 28
Single-Error Correction, Double-Error
Detection
◼ Hamming code
◼ Can detect and correct only a single error
◼ Multiple errors may not be detected.
◼ Hamming code + a parity bit
◼ Can detect double errors and correct a single error.
◼ The additional parity bit is the XOR of all the other
bits.
◼ E.g.: the previous 12-bit coded word
0 0 1 1 1 0 0 1 0 1 0 0 P13  0 0 1 1 1 0 0 1 0 1 0 0 1
(even parity).

Digital Circuits 29
◼ When the word is read from memory
◼ If P = 0, the parity is correct; P = 1, incorrect
◼ Four cases
1. If C = 0, P = 0, no error
2. If C  0, P = 1, a single error that can be corrected
3. If C  0, P = 0, a double error that is detected but cannot
be corrected
4. If C = 0, P = 1, an error occurred in the P13 bit

Digital Circuits 30
 7-5 Read-Only Memory
◼ Store permanent binary information
◼ 2k x n ROM
◼ k address input lines
◼ enable input(s)
◼ three-state outputs

Fig. 7.9
ROM block diagram
Digital Circuits 31
 ◼ 32 x 8 ROM
◼ 5-to-32 decoder
◼ 8 OR gates
◼ each has 32 inputs
◼ 32x8 internal programmable connections

Fig. 7.10
Internal logic of a
32  8 ROM Digital Circuits 32
 ◼ programmable interconnections
◼ close (two lines are connected)
◼ or open
◼ A fuse that can be blown by applying a high voltage pulse

Fig. 7.11
Programming the ROM
according to Table 7.3 Digital Circuits 33
◼ ROM truth table (partial)
◼ an example

Digital Circuits 34
Combinational Circuit Implementation
◼ ROM: a decoder + OR gates
◼ sum of minterms
◼ a Boolean function = sum of minterms
◼ For an n-input, m-output combinational ckt
 2n  m ROM
◼ Design procedure:
1. Determine the size of ROM
2. Obtain the programming truth table of the ROM
3. The truth table = the fuse pattern

Digital Circuits 35
◼ Example 7-1

◼ 3 inputs, 6 outputs
◼ B1=0
◼ B0=A0
◼ 8x4 ROM
Digital Circuits 36
 ◼ ROM implementation
◼ Truth table

Fig. 7.12
ROM implementation of Example 7.1

Digital Circuits 37
Types of ROM
◼ Types of ROM
◼ mask programming ROM
◼ IC manufacturers
◼ is economical only if large quantities
◼ PROM: Programmable ROM
◼ fuses
◼ universal programmer
◼ EPROM: erasable PROM
◼ floating gate
◼ ultraviolet light erasable
◼ EEPROM: electrically erasable PROM
◼ longer time is needed to write
◼ flash ROM
◼ limited times of write operations

Digital Circuits 38
 Combinational PLDs
◼ Programmable two-level logic
◼ an AND array and an OR array

Fig. 7.13
Basic configuration of three PLDs Digital Circuits 39
7.6 Programmable Logic Array
◼ PLA
◼ an array of programmable AND gates
◼ can generate any product terms of the inputs
◼ an array of programmable OR gates
◼ can generate the sums of the products
◼ more flexible than ROM
◼ use less circuits than ROM
◼ only the needed product terms are generated

Digital Circuits 40
 ◼ An example
F1 = AB + AC +
ABC
F2 = (AC + BC)
XOR gates
can invert the outputs

Fig. 7.14
PLA with three inputs, four
product terms, and two outputs
Digital Circuits 41
◼ PLA programming table
◼ specify the fuse map

Digital Circuits 42
◼ The size of a PLA
◼ The number of inputs
◼ The number of product terms (AND gates)
◼ The number of outputs (OR gates)
◼ When implementing with a PLA
◼ reduce the number of distinct product terms
◼ the number of terms in a product is not important

Digital Circuits 43
 ◼ Examples 7-2
◼ F1(A, B, C) =  (0, 1, 2, 4); F2(A, B, C) =  (0, 5, 6, 7)
◼ both the true value and the complement of the function
should be simplified to check

Fig. 7.15
Solution to Example 7.2

Digital Circuits 44
 • F1 = (AB + AC + BC)
• F2 = AB + AC + ABC

Fig. 7.14
PLA with three inputs, four
product terms, and two outputs
Digital Circuits 45
7-7 Programmable Array Logic
◼ a programmable AND array and a fixed OR
array
◼ The PAL is easier to program, but is not as flexible
as the PLA

第三版圖片，參考用!

Digital Circuits 46
◼ An example PAL
◼ product terms
cannot be shared

Fig. 7.16
PAL with four inputs,
four outputs, and a
three-wide AND-OR
structure
Digital Circuits 47
An example implementation
w(A,B,C,D) = (2,12,13)
x(A,B,C,D) = (7,8,9,10,11,12,13,14)
y(A,B,C,D) = (0,2,3,4,5,6,7,8,10,11,15)
z(A,B,C,D) = (1,2,8,12,13)
◼ Simplify the functions
w = ABC + ABCD
x = A + BCD
y = AB + CD + BD
z = ABC + ABCD + ACD + ABCD
= w + ACD + ABCD

Digital Circuits 48
◼ PAL programming table

Digital Circuits 49
 w = ABC + ABCD
x = A + BCD
y = AB + CD + BD
z = w + ACD + ABCD

Fig. 7.17
Fuse map for PAL
as specified in
Table 7.6
Digital Circuits 50
 7-8 Sequential Programmable Devices
◼ Sequential programmable logic device
◼ SPLD
◼ PLD + filp-flops

Fig. 7.18
Sequential programmable logic device

Digital Circuits 51
◼ Macrocell

Fig. 7.19
Basic macrocell logic
◼ A typical SPLD contains 8-10 macrocells
Digital Circuits 52
◼ Programming features:
◼ AND array
◼ use or bypass the flip-flop
◼ select clock edge polarity
◼ preset or clear for the register
◼ complement an output
◼ programmable input/output pins

Digital Circuits 53
 ◼ Altera macrocell
第三版內容，參考用!
CLK

Clk
MUX
8 Product Term
AND-OR Array
+ AND
Outp ut
MUX
pa d I/O Pin
Programmable ARRAY
Q

MUX's In ve rt
Control
F/B
MUX Seq. Logic
Block

Programmable polarity Programmable feedback

Digital Circuits 54
 ◼ Complex PLD
◼ Put a lot of PLDS on a chip
◼ Add wires between them whose connections can
be programmed
◼ Use fuse/EEPROM technology

Fig. 7.20
General CPLD configuration Digital Circuits 55
◼ Field-Programmable Gate Array
◼ Emulate gate array technology
◼ Hence Field Programmable Gate Array
◼ You need:
◼ A way to implement logic gates
◼ A way to connect them together
◼ PALs, PLAs = 10 - 100 Gate Equivalents
◼ Field Programmable Gate Arrays = FPGAs
◼ 100 - 1000(s) of Gate Equivalents

Digital Circuits 56
 Field-Programmable Gate Arrays

◼ Logic blocks
◼ To implement combinational
and sequential logic
◼ Interconnect
◼ Wires to connect inputs and
outputs to logic blocks
◼ I/O blocks
◼ Special logic blocks at
periphery of device for
external connections
◼ Key questions:
◼ How to make logic blocks programmable?
◼ How to connect the wires?
◼ After the chip has been fabbed 第三版內容，參考用!

Digital Circuits 57
 Basic Xilinx Architecture

Fig. 7.21
Basic
architecture of
Xilinx Spartan
and predecessor
devices

Digital Circuits 58
 Configurable Logic Block (CLB)

Fig. 7.22
CLB architecture
Digital Circuits 59
Interconnect Resources

Fig. 7.23
RAM cell controlling a PIP transition gate

Digital Circuits 60
Programmable Interconnect Point (PIP)

Fig. 7.24
Circuit for a programmable PIP
Digital Circuits 61
 I/O Block (IOB)

Fig. 7.25
XC4000 series IOB
Digital Circuits 62
 Enhancements

Fig. 7.26
Distributed RAM cell formed from a lookup table
Digital Circuits 63
 Xilinx Spartan XL FPGAs

Fig. 7.27
Spartan dual-port RAM
Digital Circuits 64
Xilinx Spartan XL FPGAs

Digital Circuits 65
Xilinx Spartan II FPGAs

Digital Circuits 66
Xilinx Spartan II FPGAs

Digital Circuits 67
 Xilinx Spartan II FPGAs

Fig. 7.28
Spartan II architecture Digital Circuits 68
 Xilinx Spartan
II FPGAs

Fig. 7.29
Spartan II CLB slice
Digital Circuits 69
 Xilinx Spartan II FPGAs

Fig. 7.30
Spartan II IOB Digital Circuits 70
 Xilinx Virtex FPGAs

Fig. 7.31
Virtex II overall
architecture

Digital Circuits 71
 Xilinx Virtex FPGAs

Fig. 7.32
Virtex IOB block
Digital Circuits 72