MCS-202

Computer Organisation
Indira Gandhi
National Open University
School of Computer and
Information Sciences

Block

2
Memory and Input/Output Organisation

UNIT 5
The Memory System
UNIT 6
Advance Memory Organisation
UNIT 7
Input/Output Organisation

UNIT 8
Device Technology
 FACULTY OF THE SCHOOL
Prof P. V. Suresh, Director Prof. V. V. Subrahmanyam
Dr Shashi Bhushan Mr Akshay Kumar
Mr M. P. Mishra Dr Sudhansh Sharma

PROGRAMME/COURSE DESIGN COMMITTEE

Shri Sanjeev Thakur Prof. Gayatri Dhingra, GVMITM, Sonipat
Amity School of Computer Sciences, Sh. Milind Mahajani
Noida Shri Amrit Nath Thulal Impressico Business Solutions, Noida, UP
Amity School of Engineering and Technology Prof. V. V. Subrahmanyam
New Delhi SOCIS, New Delhi
Dr. Om Vikas(Retd), Prof. P. V. Suresh
Ministry of ICT, Delhi
SOCIS, IGNOU, New Delhi
Shri Vishwakarma Dr. Shashi Bhushan
Amity School of Engineering and SOCIS, IGNOU, New Delhi
Technology New Delhi
Shri Akshay Kumar,
Prof (Retd) S. K. Gupta, IIT Delhi
SOCIS, IGNOU, New Delhi
Prof. T.V. Vijay Kumar, SC&SS, JNU,
New Delhi Shri M. P. Mishra,
Prof. Ela Kumar, CSE, IGDTUW, Delhi SOCIS, IGNOU, New Delhi
Dr. Sudhansh Sharma,
SOCIS, IGNOU, New Delhi
BLOCK PREPARATION TEAM
Dr Zahid Raja (Content Editor) Mr Vikas Mittal (Course Writer – Unit 5 & 6)
Jawaharlal Nehru University Maharaja Agrasen College,
New Delhi University of Delhi
Delhi

Dr Mohammad Sajid (Course

Writer – Units 7 & 8)
Department of Computer
Science
Aligarh Muslim University
Aligarh

(Language Editor) School of Humanities

IGNOU

Course Coordinator: Mr Akshay Kumar

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BLOCK 2 INTRODUCTION
In the first block this course, you are introduced to basic computer architectures, instruction execution, data
representation and logic circuits of a computer system. This Block covers two of the most important units that are part of
computer system architecture, viz. the memory system and Input/output system. This block consists of 4 units (unit 5 to
unit 8).
Unit 5 explains the basic memory hierarchy of a computer system. It also explains different kinds of memories used in a
computer system. The logic of RAM and ROM has also been explained in details. The unit also discusses secondary
memories like magnetic and optical disks in details.
Unit 6 provides details on advance memory organisation. It provides details on different aspects of cache memory and
main memory to cache mapping schemes. This unit also discusses the concept of interleaved memory, associative
memories and virtual memories used in a computer system.
Unit 7 explains the basic interfaces and mechanisms that are used to perform input and output. This unit also presents the
concept of DMA and input/output processor.
Unit 8 introduces you to basic technology of some of the popular input/output devices including keyboard, mouse,
monitor, printer etc.
A course on computers can never be complete because of the existing diversities of the computer systems. Therefore, you
are advised to read through further readings to enhance the basic understanding that you will acquire from the block.

Further Readings For The Block

1) Mano M Morris, Computer System Architecture, 3rd Edition/Latest Edition, Prentice Hall of India Publication,
Pearson Education Asia
2) Stallings W., Computer Organization & Architecture: Designing For Performance, 10th/11th Edition, Pearson
Education Asia
3) Hennessy/Patterson, Computer Organization and Design : The Hardware/ Software Interface; 5th/6th Edition,
Morgan Kaufmann.
 The Memory System
UNIT 5 THE MEMORY SYSTEM
Structure Page Nos.
5.0 Introduction
5.1 Objectives
5.2 The Memory Hierarchy
5.3 SRAM, DRAM, ROM, Flash Memory
5.4 Secondary Memory and Characteristics
5.4.1 Hard Disk Drives
5.4.2 Optical Memories
5.4.3 Charge-coupled Devices, Bubble Memories and Solid State Devices
5.5 RAID and its Levels
5.6 Summary
5.7 Answers

5.0 INTRODUCTION
In the previous block, fundamentals of a computer system were discussed. These
fundamentals included discussion on von-Neumann architecture based machines,
instruction execution, representation of digital data and logic circuits etc. This Block
explains the most important component of memory and Input/output systems of a
computer. This unit covers the details of the Memory. This unit discusses issues
associated with various components of the memory system, the design issues of main
memory and the secondary memory. Various characteristics of secondary memory and
its types that are used in a computer system, would also be discussed. The unit also
defines how multiple disks can be used to create a redundant array of disks that can be
used to provide a faster and reliable storage.

5.1 OBJECTIVES
After going through this Unit, you will be able to:

 explain the key characteristics of various types of memories and memory hierar-
chy;
 explain and differentiate among various types of random access memories;
 explain the characteristics of secondary storage devices and technologies;
 explain the latest secondary storage technologies;
 identify the various levels of RAID technologies

5.2 THE MEMORY HIERARCHY

In computers, memory is a device used to store data in binary form. Smallest unit of
binary data is called ‘bit’. Each bit of binary data is stored in a different cell or storage
unit and collection of these cells is defined as the memory. A memory system is
composed of a memory of fixed size and procedures which tells how to access the
data stored in the memory. Based on the persistence of the stored data, memory is
classified into two categories:

 Volatile memory: which loses its data in the absence of power.

 Non-volatile memory: Do not lose data when power is switched off.

Another classification of memory devices, which is also the objective of this unit is
based on the way they interact with the CPU which can be determined from figure 5.1
Main/ Primary memory interact directly with the CPU e.g. RAM and ROM.
5
Basic Computer Organisation Auxiliary/ secondary memory need I/O interface to interact with the CPU e.g.
magnetic disks and magnetic tapes. There are other memories like cache and registers,
which directly interacts with the CPU. Such memories are used to speed up the
program execution. For execution, a program must be loaded into the main memory
and should be stored on the secondary storage when it completes its execution.
Auxiliary memory is used as a backup storage, whereas main memory contains data
and program only when it is required by the CPU.

Figure 5.1: Memory Interaction with CPU

Various memory devices in a computer system forms a hierarchy of components

which can be visualised in a pyramidal structure as shown in Figure 5.2. As you can
observe in the Figure 5.2 that at the bottom of the pyramid, you have magnetic tapes
and magnetic disks; and registers are at the top of the pyramid. Main memory lies at
the middle as it can interact directly with the CPU, cache memory and the secondary
memory. As you go up in the pyramid, the size of the memory device decreases, the
access speed, however, increases and cost per bit also increases. Different memories
have different access speeds. CPU registers or simply registers are fastest among all
and are used for holding the data being processed by the CPU temporarily but because
of very high cost per bit they are limited in size. Instruction execution speed of the
CPU is very high as compared to the data access speed of main memory. So, to
compensate the speed difference between main memory and the CPU, a very high
speed special memory known as cache is used. The cache memory stores current data
and program plus frequently accessed data which is required in ongoing instruction
execution.

You may note the following points about memory hierarchy:

 The size of the memory increases as you go down the memory hierarchy.
 The cost of per unit of memory increases as you go up in the memory hierarchy
i.e. Memory tapes and auxiliary memory are the cheapest and CPU Registers are
the costliest amongst the memory types.
 The amount of data that can be transferred between two consecutive memory
layers at a time decreases as you move up in the pyramid. For example, from
main memory to Cache transfer one or few memory words of size in Kilobytes
are accessed at a time, whereas in a hard disk to main memory transfer, a block
data of size of 1 Megabyte is transferred in a single access.
 One interesting question about the memory hierarchy is why having faster
smaller memories does not slow down the computer? This is primarily due to the
6
 fact that there is very high probability that a program may access the instructions The Memory System
and data in the closed vicinity of presently executing instruction and data. This
concept is further explained in next unit.

Figure 5.2: Memory Hierarchy

In subsequent sections and next unit, we will discuss various types of memories in
more detail.

5.3 SRAM, DRAM, ROM, FLASH MEMORY

The main memory is divided into fixed size memory blocks called words. Size of the
memory word may be limited by the communication path and the processing unit size.
As word size/ length denotes the amount of bits that can be processed by the processor
at one time. Each memory word is addressed uniquely in the memory. A 32-bit
processor uses a word size of 32 bits whereas 64-bit processor uses a word of 64 bits.
RAM (random access memory) is a volatile memory i.e. content of the RAM vanishes
when power is switched off. RAM is a major constituent of the main memory. Both
read and write operations can be performed on RAM, therefore, it is also known as
read-write memory. Access time of each memory word is constant in random access
memory. RAM can be constructed from two types of technologies - Static Random
Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). The main
difference being that DRAM loses its content even if power is on, therefore requires
refreshing of stored bits in DRAM. Thus, DRAM is slower than SRAM, however, the
DRAM chips are cheaper. In general, DRAM is used as the main memory of the
computer, while SRAM is used as the Cache memory, which is discussed in details in
the next unit.
SRAM
SRAM can be constructed using flip-flops. It is a sequential circuit. A SRAM cell
using SR flip flop is shown in figure 5.3. As you can observe, this sequential circuit
has three inputs: select, read/write, and input and single output: output. When select
input is high “1” circuit is selected for read/write operation and when select input is
low “0” neither read nor write operation can be performed by the binary cell. Thus,
select input must be high in order to perform read/write operation by the binary cell.
Binary cell reads a bit when read/write input is low “0” and writes when read/write
input is high “1”. Third input input is used to write into the cell. The only caution over
here is that when read/write input is low “0” i.e. we want to perform a read operation,
then read operation must not be affected by the input input. This is ensured by
7
Basic Computer Orga
anisation inverted inpput to the firstt AND gate which
w guaranttees the inputt to both R annd S to be
low and thuus prevents anny modificatioon to the flip flop value. The
T characterristic table
of SR flip flop
f is given iin Unit 4 Blo
ock 1 for bettter understandding of the fuunctioning
of the binaryy cell.

Figure 5.3: Logic

L Diagram of
o RAM cell

Read operation: select iss high “1”, reaad/write is low

w “0” and inpput is either low “0” or
high “1” theen input to R and S will be
b 0 and flip flop
f will keepp its previouss state and
that will be the output.
Write operaation: select is
i high “1”, reead/write is high
h “1” and if
i input is loww “0” then
R will be hiigh “1” and S will be low w “0” and flipp flop will stoore “0” and if input is
high “1” theen R will go low”0” and S will go high “1” and flip flop
f will storee “1”.

A RAM chhip is composed of severral read/writee binary cellss. A block diiagram of

2mx n RAM M is shown in Figure 5.4. The T RAM shoown has a totaal capacity off 2m words
and each word is n bits long e.g. in 64 x 4 RAM M, the RAM has h 64 words and each
word is 4 biits long. To adddress 64 i.e. 26words, we need 6 address lines. So inn a 2m × n
RAM, we haveh 2m wordds where each word has n bits and RA AM has m-bbit address
which requiires___m addresss lines. The RAM
R is funcctional only when
w chip sellect (CS1)
signal =1 annd CS2 = 0. If chip sellect signal is not enabled or chip select signal is
enabled andd neither reaad nor write input is ennabled then data d bus willl in high
impedance state
s and no operation caan be perform med. During high impedaance state,
other input signals
s will be
b ignored whhich means ouutput has no lo ogical significance and
does not carrry a signal

4: Block Diaggram of 2mx n RAM

Figure 5.4
 The Memory System
DRAM
Dynamic Random Access Memory (DRAM) is a type of RAM which uses 1 transistor
and 1 capacitor (1T1C cell) for storing one bit. A block diagram of a single DRAM
cell is shown in Figure 5.5. In DRAM, transistor is used as a gate which opens and
closes the circuit and thus stops and allows the current to flow. Charging level of the
capacitor is used to represent the bit “1” and bit “0”. As capacitors tends to discharge
in a very short time period DRAM cells need to be refreshed periodically to store the
binary information despite continuous power supply. Hence they are called dynamic
random access memory. With low power consumption and very compact in size
because of 1T1C architecture DRAM offers larger storage capacity in a single chip.
Each DRAM cell in the memory is connected with Word Line (Rows) and Bit Line
(Columns) as shown in Figure 5.5. Word line (rows) controls the gates of the transfer
lines while Bit lines (columns) are connected to sense amplifiers i.e. to determine “0”
or “1”.

Figure 5.5: A DRAM cell

Figure 5.6 presents the general block diagram of 2M 2M × N DRAM, where binary
cells are arranged in a square of 2M × 2M words of N bit each. For example, 4 megabit
DRAM is represented in a square arrangement of (1024 × 1024) or (210 × 210 ) words
of 4 bit each. Thus, in the given example we have 1024 horizontal/ word lines and
1024 × 4 column/ bit lines. In other words, each element, which consists of 4 bits of
array, is connected by horizontal row lines and vertical column lines.

Figure 5.6: Block Diagram of DRAM

9
Basic Computer Organisation
Selection and role of various signals for read and write operation is as follows:

1. RAS (Row Address Strobe): On the falling edge of RAS signal, it opens or strobe
the address lines (rows) to be addressed.

2. /CAS (Column Address Strobe): Similar to /RAS, on the falling edge, this enables a
column to be selected as mentioned in the column address from the rows opened by
the /RAS to complete the read-write operation.

3. R/(/W), Write enable: This signal determines whether to perform a read operation
or a write operation. While the signal is low, write operation is enabled and data input
is also captured on falling edge of /CAS whereas high enables the read operation.

4. Sense amplifier compares the charge of the capacitor to a threshold value and
returns either logic “0” or logic “1”.

For a read operation once the address line is selected, transistor turns ON and opens
the gate for the charge of the capacitor to move to the bit line where it is sensed by the
sense amplifier. Write operation is performed by applying a voltage signal to the bit
line followed by the address line allowing a capacitor to be charged by the voltage
signal.

ROM (Read-Only Memory)

Another constituent of the main memory is ROM (read only memory). Unlike RAM,
which is read-write memory and volatile, ROM’s are read only and non-volatile
memory i.e. content of the ROM persist even if power is switched-off. Once data is
stored at the time of fabrication, it cannot be modified. This is why, ROM is used to
store the constants and the programs that are not going to change or get modified
during their lifetime and will reside permanently in the computer. For example,
bootstrap loader, which loads the part of the operating system from secondary storage
to the main memory and starts the computer system when power is switched on, is
stored in ROM.

A block diagram of 2m× n ROM looks similar to that of RAM. As ROM is a read-only
memory there is no need of explicit read and write signals. Once the chip is selected
using chip select signals a data word is read and placed on to the data bus. Hence, in
the case of ROM, you need an unidirectional data bus i.e. only in output mode as
shown in figure 5.7. Another interesting fact about ROM is that, ROM offers more
memory cells and thus, memory as compared to the RAM for same size chip.

Figure 5.7: Block Diagram of 2mx n ROM

10
 T Memory Syystem
The
m m
As shhown in Figu ure 5.7, 2 × n ROM has 2 words of n bits each foor which it haas m
addreess lines and n output datta lines. For example, in 128 × 8 ROM M, you have 128
memmory words off 8-bit each. For
F 128 × 8 ROM R i.e. 2m = 27, m = 7, yoou need 7 adddress
lines (minimum number
n of bitss required to represent
r 1288) and 8-bit ou
utput data buss.
Figurre 5.8 shows a 32×8 ROM M.

Figure 5..8: Internal diagram of 332x8 ROM

Unlikke RAMs, which

w are seequential circcuits, ROMss are combinnational circuuits.
Typiccally, to design a RAM of o specific sizze you need a decoder andd OR gates. For
exammple, to desiggn a ROM of size 32 x 8 bits
b you need a decoder off size 5×32 annd 8
OR gates.
g 5×32 decoder
d will have
h 5 input lines, which will act as 5 address linees of
the ROM,
R the deccoder will con
nvert 5-bit in
nput address tot 32 differennt outputs. Figgure
5.8 shows the connstruction of 32
3 × 8 ROM using
u 5×32 ddecoder and eiight OR gatess for
data output. ROM Ms of other sizes can be constructedd similarly. For examplee, to
consttruct a ROM of 64 × 4 RO OM, you need d a 6×64 decooder and fourr OR gates annd to
consttruct a ROM of size 256×88, you need 8×256 decoderr and 8 OR gaates.
As discussed,
d ROOMs are non-vvolatile mem mory and conteent of the ROOM once writtten,
cannnot be changedd. Therefore, ROMs are ussed to store thhe look-up tabbles for consttants
to sp
peed up the computation.
c In addition, ROM can stoore the boot loader progrrams
and gaming
g progrrams. All this requires, zeero error in writing
w of succh programs and
thereefore, ROM device
d fabricaation requires very high precision. Consstructing a ROOM,
as shhown in figurre 5.8, requires decision about
a which iinterconnectioons in the cirrcuit
shouuld be open annd which interconnections should be cloosed. There are
a four ways you
can program
p a RO
OM which aree as follows:
1. Mask
M ROM (MROM):
( Maasking of RO OM is done bby the device manufactureer in
the
t very last phase
p of the fabrication prrocess on cusstomers speciial request. Mask
M
ROMs
R are cuustomised ass per the useer requiremennts, thus, aree very costlyy as
different
d maskks are requireed for differennt specificatioons. Because of very high cost
of
o masking, thhis customizaation is generaally used in m manufacturing g of ROM at vvery
large
l scale.
2. Programmabl
P e ROM (PR ROM): MRO OMs are noot cost effeective for sm mall
productions,
p P
PROMs are preferred
p for small quantitties. PROMs are programm med
using
u a special hardware which
w blow fuses
f with a very high vooltage to prodduce
logic
l “0” andd intact fuse defines
d logic “1”. The conntent of PROM is irreverssible
once
o program
mmed.
3. Erasable
E PRO
OM (EPROM M): EPROM Ms are third type of RO OMs which are
restructured
r or med using shortwave radiaations. An ulttraviolet lightt for
o reprogramm
Basic Computer Organisation a specific duration is applied to the EPROM, which destroys/ erases the internal
information and after which EPROMs can be programmed again by the user.
4. Electrically EPROM (EEPROM) : EEPROMs are similar to EPROMs except of
using ultraviolet radiations for erasing PROM, EEPROM uses electrical signals to
erase the content. EEPROM can be erased or reprogrammed by the user without
removing them from the socket.

Flash Memory
Flash memory is a non-volatile semiconductor memory which uses the programming
method of EPROM and erases electrically like EEPROM. Flash memory was
designed in 1980s. Unlike, EEPROM where user can erase a byte using electrical
signals, a section of the memory or a set of memory words can be erasable in flash
memory and hence the name flash memory i.e. which erases a large block of memory
at once. Flash memory is easily portable and mechanically robust as there is no
mechanical movement in the memory to read-write data. Flash memory is widely used
in USB memory, SD and micro SD memory cards used in cameras and mobile phones
respectively.
There are two types of flash memory, viz. NAND flash memory, where read operation
is performed by paging the contents to the RAM i.e. only a block of data is accessed
not an individual byte or word; and NOR flash memory, which are able to read an
individual memory byte/word or cell.

The features of various semiconductor memories are summarised in the Table 1.

Erase
Write Volatile/
Memory Type Mechanism/
Mechanism Non- Volatile
Level
Random-access
Read–Write Electrical/ Byte Electrical Volatile
Memory (RAM)
Read –only
Read–Only Not Applicable Masks Non-volatile
Memory (ROM)
Programmable
Read–Only Not Applicable Electrical Non-volatile
ROM (PROM)
Erasable PROM Read-
UV light/ Chip Electrical Non-volatile
(EPROM) mostly
Electrically
Read- Electrical/
Erasable Electrical Non-volatile
mostly Byte
(EEPROM)
Read- Electrical/
Flash memory Electrical Non-volatile
mostly Block

Table 1: Features of Semiconductor Memories

Check Your Progress 1

1. Differentiate among RAM, ROM, PROM and EPROM.
……………………………………………………………………………………

……………………………………………………………………………………

2. What is a flash memory? Give a few of its typical uses.

……………………………………………………………………………………

……………………………………………………………………………………
12
3. A memory has a capacity of 16K  16 The Memory System
(a) How many data input and data output lines does it have?
(b) How many address lines does it have?
……………………………………………………………………………………

……………………………………………………………………………………
4. A DRAM that stores 4K bytes on a chip and uses a square register array. Each
array is of size 4 bits. How many address lines will be needed? If the same
configuration is used for a chip which does not use square array, then how many
address lines would be needed?
………………………………………………………………………………………
………………………………………………………………………………………
5. How many RAM chips of size 256K  4 bit are required to build 1M Byte
memory?
……………………………………………………………………………………...
……………………………………………………………………………………...

5.4 SECONDARY MEMORY AND

CHARACTERISTICS
In previous section, we have discussed various types of random access and read only
memories in detail. RAM and ROM together make the main memory of the computer
system. You know that a program is loaded into main memory to complete its
execution. Computational units or CPU can directly interact with the main memory.
Hence, faster main memory, which can match with the speed of CPU, is always
desirable. In the previous section configuration of two types of RAMs, viz SRAM and
DRAM were discussed. As you may observe the SRAM consists of flip-flop based
circuits, therefore, is quite fast in comparison to DRAM However, the cost per bit of
DRAM is much less than the SRAM. Thus, you may observe the size of main memory
is much more than cache. It is discussed in more details in the next unit. To achieve
high speed, cost per bit of main memory is generally high which also limits its size.
On the other hand, as we have discussed, RAM, which is a major constituent of the
main memory, is volatile i.e. content of the main memory is lost when power is
switched off. Because of above mentioned issues, you need a low cost and high
capacity, non-volatile memory to store program files and the data for later use.
Secondary memory devices which are at the bottom of the memory hierarchy pyramid
are ideal for the said purpose. We will discuss various secondary storage devices in
this section.

5.4.1 Hard Disk Drive

In the era of Big Data, in which variety of data is generated rapidly, large secondary
storage has become an important component of every computer system. Today, hard
disk drives (HDD) is the primary type of secondary storage. The size of hard disk
drives in modern computer system ranges from Gigabytes (GB) to Terabytes (TB).
Internal hard drives extends the internal storage of a computer system whereas
external hard drives are used for back up storage.
HDD are electro-mechanical storage devices, which store digital data in the form of
small magnetic fields induced on the surface of the magnetic disks. Data recorded on
the surface of magnetic disks is read by disks read/write head, which transforms
magnetic signal to electrical signal for reading and electrical signal to magnetic field

13
Basic Computer Orga
anisation for writing.. HDD is coomposed of manym concenntric magneticc disks mounnted on a
central shaft
ft as shown in Figure 5.8.

Figuure 5.8: Interrnal structurre of Hard diisk drives (H

HDD)

Figure 5.8 shows the innternal structture of an H HDD. An HD DD is made of o several

concentric magnetic
m diskks mounted on o a central sshaft called spindle.
s Each magnetic
disk is madee of either glaass or an alum
minium disk called platterr. Each platterr is coated
with ferrom magnetic maaterial for storing
s data. Platter itseelf is made of non-
ferromagnettic material soo that its ownn magnetic fieeld should nott interfere thee magnetic
field of the data. Generaally, both sidees of the plattter is coated with
w magneticc material
for good stoorage capacityy at low cost.
Data recordded on the disk is accessedd through a read/write headd. Each side oof the disk
has its own read write heead. Each readd/write head isi positioned at a distance of tens of
nanometer called
c flying height to thee platter so thhat it can eassily sense or detect the
polarization
n of the magneetic field.

Figuure 5.9: Read/ Write Heaad

Two motorss are used in HDD. First one o is called the spindle motor,
m which is used to
d motor is used to move
rotate the sppindle on whiich all the plattters are mouunted. Second
the read/write heads across the entire surface of the platter radially and is called The Memory System
actuator or access arm.
Magnetic Read and Write Mechanisms
During a read/ write operation, read/write head is kept stationary while platter is
rotated by the spindle motor. As you know, data on the disk is recorded in the form of
magnetic field. The current is passed through the read/write head which induces a
magnetic field on the surface of platter and thus, records a bit on the surface. Different
directions of current generates magnetic fields with different polarities and hence are
used for storing “1” and “0”. Similarly, to read a bit from the surface, the magnetic
field is sensed by the read/write head which produces an electric current of the same
polarity and hence the bit value is read.
Data Organization and Formatting
As discussed and shown in figure 5.8, hard disk drives consists of number of
concentric platters which are mounted on a spindle forming a cylindrical structure.
Data is written in the form of magnetic fields on both surfaces of these platters and is
read by read/write head which is connected to an actuator. In this section, we will
discuss structure of magnetic disk in detail.
Structure of the disk is shown in figure 5.10. As you know, each magnetic disk is a
circular disk mounted on a common spindle but entire disk space is not used for data.
Disk surface is divided in to thousands of concentric circular regions called tracks.
The width of every track is kept the same. Data is stored in these tracks. Magnetic
field of one track should not affect the magnetic region in the other track thus two
tracks are kept apart with each other by a constant distance. Further, each track is
divided into number of sectors and two sectors are kept apart using inter-sector gap.
Data is stored in these sectors. Each track forms a cylindrical structure with other
tracks on other platters below or above it. For example, an outer most cylinder will
have outer most track of all the platters. So, if we have n tracks in a platter then there
will be n concentric cylinders too.
Components of the drive are controlled by a disk controller. Now a days, disk
controllers are built in to the disk drive. A new or blank magnetic disk is divided into
sectors. Each sector has three components: header, 512 byte (or more) data area and a
trailer. This process of is called physical / low level formatting. Header and trailer
contains metadata about the sectors e.g. sector number, error correcting code etc. Disk
controller uses this information whenever it writes or reads a data item on to a sector.
Data is stored in series of logical blocks. The disk controller maps the logical blocks
on to the physical disk space and also manages sectors which have been used for
storing data and which are still free. This is done by the operating system after
partitioning the disk in to one or more groups of cylinders. Disk controller stores the
initial data structure file of every sector on to the disk. This data structure file contains
a list of used and free sectors, list of bad sectors etc. Windows uses File Allocation
Table (FAT) for the said purpose.

15
Basic Computer Orga
anisation

Figuree 5.10: Magn

netic Disk Sttructure of CAV
C

There are tw wo arrangemments with whhich platters aare divided innto tracks annd sectors.
The first arrrangement is called as connstant linear vvelocity (CLVV), in which thhe density
of bits per track
t is kept uuniform, i.e. outer tracks aare longer thaan the inner tracks
t and
hence contaains more num mber of sectoors and data. O Outermost traacks are generally 40%
longer than the innermosst track. In this arrangemennt, in order to o maintain unniform bit/
mong tracks, tthe rotation speed
data rate am s is increeased from ouutermost to innner most
track. This approach
a is used by CD-ROM and DVD D-ROM drivees.

In another approach
a callled as constaant angular velocity
v (CAV)
V), the densityy of bits /
data per track is decreassing as we move from innnermost trackk to outermost track by
keeping thee disk rotationn speed consttant. As disk is moving att a constant speed,s the
width of thee data bits inccreases in thee outer trackss, which resullts in the connstant data
rate. Figuree 5.10 shows that the widdth of sectors in outer traacks is increasing and
density of bits is decreasiing.

Disk Perforrmance

Data is readd and written on the disks by the operatting system for f usage at laater stage.
A disk storees the program ms and relateed data. How
wever, disk is a much slow wer device
and the proograms storedd on it cannoot be executeed by the prrocessing uniit directly.
Therefore, the
t programs and its related data, whicch are not in the main meemory, are
loaded in thhe main mem mory from thhe secondaryy storage. Sinnce, the speeed of disk
read/write iss very slow inn compared tot RAM, timee to read or write
w a byte from
fr or on
to the disk affects the coomputer overrall efficiencyy. Therefore, in a single read/write
r
operation on disk data ofo one or morre sectors is transferred
t too/from the meemory. An
operating syystem, in geneeral, request for
f read/writee to one or moore sectors onn the disk.
The time takken by the dissk to complette a read/ writte request of the
t operatingg system is
known as diisk access timme. There are number of faactors which affect the perrformance
of the disk. These factorss are:
1. Seek Tiime: It is deffined as a tim
me taken by tthe read/writee head, or simmply as a
head, to
o reach the desired
d track on which thee requested sector
s is locaated. Head
should reach
r the desired track in minimum tim
me. Shorter seeek time leadds to faster
I/O operration.
2. Rotationnal Latency: Since, every track consistts of a numbeer of sectors, therefore,
the readd/write operaation can beb completedd only when the desired sector is
availablle under the read/write head
h for the I/O operatio on. It dependds on the
 rotational speed of the spindle and is defined as a time taken by a particular sector The Memory System
to get underneath the read/write head.
3. Data Transfer Rate: Since, large amount of data is transferred in one read/write
operation, therefore, the data transfer rate is also a factor for I/O operation. It is
defined as the amount of data read or written by the read/write head per unit time.
4. Controller overhead: It is the time taken by the disk controller for mapping logical
blocks to physical storage and keep track of which sectors are free and which are
used.
5. Queuing Delay: time spent waiting for the disk to be free.
The disk access time is defined as the summation of seek time, rotational latency, data
transfer rate, controller overhead and queuing delay and is given by the equation.

𝑎𝑐𝑐𝑒𝑠𝑠 𝑠𝑒𝑒𝑘 𝑟𝑜𝑡𝑎𝑡𝑖𝑜𝑛𝑎𝑙 𝑑𝑎𝑡𝑎 𝑐𝑜𝑛𝑡𝑟𝑜𝑙𝑙𝑒𝑟

𝑞𝑢𝑒𝑢𝑖𝑛𝑔

Out of the five parameters mentioned in the above equation, most of the time of the
disk controller goes in moving the read/write to the desired location and thus seeking
the information. If the disk access requests are processed efficiently then performance
of the system can be improved. The aim of disk scheduling algorithm is to serve all
the disk access requests with least possible head movement. There are number of disk
scheduling algorithms which are presented here in brief.

First Come First Serve (FCFS) scheduling: This approach serves the disk access
request in the order they arrived in the queue.

Shortest Seek Time First (SSTF) scheduling: Shortest Seek Time First disk scheduling
algorithm selects the request from the queue which requires least movement of the
head.

SCAN scheduling: The current head position and the head direction is the necessary
input to this algorithm. Disk access requests are serviced by the disk arm as disk arm
starts from one end of the disk and moves towards the other end. On reaching the
other end the direction of the head is reversed and requests are continued to be
serviced.

C-SCAN scheduling: Unlike SCAN algorithm, C-SCAN does not serve any request in
the return trip. Instead, on reaching to the end, it reverses back to the beginning of the
disk and then serves the requests.

LOOK scheduling: LOOK is similar to SCAN algorithm with only a single difference,
after serving the last request, LOOK algorithm does not go till the end instead it
immediately reverses its direction and moves to the beginning of the other end.

5.4.2 Optical Memories

So far, the storage devices you have studied are based on either electric charge or
magnetic field. Magnetic memories are primarily used as a secondary storage device,
but they can easily be damaged. However they have lower cost per bit than solid state
devices.
First laser based memory was developed in 1982 by Phillips and Sony. Laser based
storage devices uses a laser beam to read or write data and are called as optical
memories or optical storage devices. As laser beams can be controlled more precisely
and accurately than magnetic read/write heads. Data stored on optical drives remains
unaffected by the magnetic disturbances in its surrounding.

17
Basic Computer Orga
anisation Initially, theese optical stoorage devices commonly known
k as com
mpact disk (CDD) or CD-
DA (Digitall Audio) weree used to storre only audioo data of 60 minute
m duratiion. Later,
huge comm mercial succeess of CD leead to devellopment of low cost opptical disk
technology. These CDs can be used as auxiliary storage and can store anny type of
digital data. A variety off optical-disk devices have been introduuced. We brieffly review
some of these types.

Compact Disk
D ROM (C
CD-ROM)
Compact Disk
D or CD-R ROM are mad de of a 1.2 m mm thick sheeet of a polyycarbonate
material. Eaach disk surfaace is coated with a reflecctive materiall generally alluminium.
The standarrd size of a coompact disk is 120 mm in diameter. Ann acrylic coat is applied
on top of thee reflective suurface to prottect the disk fr
from scratchess and dust.

F
Figure 5.11:: Outer Layoout of a CD

Unlike maggnetic disks, data on an optical

o disk iss recorded inn a spiral shaape tracks.
Each track is separated by a distancee of 1.6 mm.. Data in a trrack is recordded in the
form of landd and pit as shown
s in Figuure 5.13. Whhen a focused laser beam inn incident
on to the opptical disk, thhe disk is burrned as per thhe digitally reecorded data forming a
pit and landd structure. Thhe data is reaad from the suurface by meaasuring the inntensity of
the reflected
d beam. The pit area scattters the incideent beam, whhereas the lannd reflects
the incident beam, whichh are read as “0”“ and “1” reespectively.

Figure 5.112: Spiral traack of CD Figure 5.133: Land & Piit formation in CD trackk

As shown in i CD are in spiral shape. The tracks inn CDs are

n Figure 5.122, the tracks in
further divid
ded into secttors. All sectoors in CDs arre equal in leength. This means
m that
density of data
d recorded on the disk is uniform acrross all the traacks. Inner trracks have
less numberr of sectors whereas
w outer tracks
t have m
more sectors. CD-ROM devvices uses
constant lineear velocity ((CLV) methodd for reading the disk content. In this method,
m the
disk is rotated at lower velocity as we move away from the center of the disk. This The Memory System
ensures a constant linear velocity at each track of the CD. The format of a sector of
CD is show in Figure 5.14.

SYNC HEADER DATA L-ECC

12 Bytes 4 Bytes 2048 Bytes 288 Bytes

Figure 5.14: Sector format of CD

Data on the CD-ROM are stored in a track as a sequence of sectors. As shown in the
Figure 5.14 each sector has four fields viz. sync, header, user data followed by error
correcting codes. Each part of the sector is described below:

• Sync: It is the first field in every sector. The sync field is 12 byte long. The
first byte of sync field contains a sequence of 0s followed by 10 bytes of all 1s
and 1 byte of all 0s.

• Header: Header is four byte field in the sector. Three bytes are used to
represent the sector address and one byte is used to represent the mode i.e.
how subsequent fields in the sector are going to use. There are 3 modes:

• Mode Zero: Specifies a no user data i.e. blank data field.

• Mode One: Specifies an user data of 2048 bytes followed by 288 bytes of
error correcting code.
• Mode Two: No error correcting code will be used thus subsequent field
will contain 2336 bytes of user data.

• Data: Data field contains the user 2048 byte of user data when mode is 1 or
mode 2.

• L-ECC: Layered error correcting code field is 288 byte long field which is
used for error detection and correction in mode 1. In mode 2, this field is used
to carry an additional 288 bytes of user data.

Compact Disk Recordable (CD-R)

CD-Recordable are the compact disks which are capable of storing any type of digital
data. The physical structure of CD-R is same as that of CD-ROM as discussed in
previous section except that polycarbonate disk has a very thin layer of an organic dye
before the Aluminum coating. CD- R can record user data only once but user can read
the data many times thus these are also known as CD-WO (write once), or WORM
(write once read many). Many CD writers allow the users to write CD-R in multiple
session until CD is full. In each writing session, a partition is created in the CD- R.
But once written, data on CD-R cannot be changed or deleted. There are three types of
organic dyes used in CD-R.
Cyanine dyes are the most sensitive dye amongst the three types. CD-Rs have cyanine
dyes are green in color. Very sensitive to UV rays and even can lose the data if
exposed to direct sunlight for few days.
Phthalocyanine dye does not need a stabilizer as compared to cyanine dyes. They are
silver, gold or light green in color. They are very less sensitive as compared to cyanine
dyes but if exposed to direct sunlight for few weeks, it may lose the data.
Azo dye is the most stable among all types. It is most resistant to UV rays but if
exposed to direct sunlight for 3-4 weeks, the CD -R may lose the data.
19
Basic Computer Organisation Compact Disk Rewritable (CD-RW)
The CD-RW are re-writable optical disks. The data on CD-RW can be read or written
multiple times. But for writing again on the already written CD-RW, the disk data
must be erased first. There are two approaches of erasing the data written on CD-RW.
In the first approach, the entire disk data is erased completely i.e. all traces of any
previous data is erased. This is called full blanking. Whereas in another approach
called as fast blanking, only the meta data is erased. The later approach is faster and
allows rewriting the disk. The first approach is used for confidentiality purposes.
The phase change technology is used in CD-RW. The phase change disk uses a
material that has significantly different reflectivity in two different phase states. There
is an amorphous state, in which the molecules exhibit a random orientation and which
reflects light poorly; and a crystalline state, which has a smooth surface that reflects
light well. A beam of laser light can change the material from one phase to the other.
The phase change technology of CD-RW uses a 15-25 % degree of reflection whereas
CD-R works on 40-70 % degree of reflection.

Digital Versatile Disk (DVD)

Digital versatile disk commonly known as DVD is also an optical storage device like
CD, CD-R, CD-WR. Among the three DVDs have highest storage capacity ranges
from 1.4 GB to 17 GB on a single side. The higher storage capacity is enabled by the
use of laser beams of shorter wavelength as compared to compact disks. DVD uses a
laser beam of 650 nm whereas compact disk uses a laser beam of 780 nm. Shorter
wavelength laser beam creates shorter pits on the polycarbonate disk, thus offers
higher storage capacity for similar dimensions. DVD-Audio and DVD-video are a
standard format for recording audio and video data on DVDs. Like compact disks,
DVD also comes in various variants like DVD-ROM, DVD-R, DVD-WR etc.

Blue Ray Disk

A blue ray disk is a digital disk that can store several hours high definition videos.
Blue ray disks is of the same size of DVD, but can store 25 GB to 128 GB of data. A
blue ray disk is designed to replace DVD technology. It has its applications in gaming
applications, which uses very high quality animations.

5.4.3 Charge-coupled Devices, Bubble Memories and Solid State

Devices
Charge-coupled Devices CCDs (CCDs)
Charge couple devices are photo sensitive devices which are used to store digital data.
CCD is an integrated circuit of MOS-capacitors called cells, which are arranged in an
array like structure in which each cell is connected with its neighbouring cell. Each
capacitor can hold the charge which is used to represent the logic “1”. While reading
the array of capacitors, the capacitor moves its charge to the neighbouring capacitor
with next clock pulse. CCD arrays are mainly used in representing images and video
data, where presence and absence of charge in the capacitor represents the
corresponding pixel intensity.
As mentioned, CCD are highly photo-sensitive in nature and thus, produces a good
quality picture even if light is dim or in low illumination intensity. Now a days, CCDs
are widely used in digital cameras, satellite imagery, radar images and other high
resolution imagery applications.

Magnetic Bubble Memories

Working principle of magnetic bubble memory is similar to that of charge coupled
devices (CCD) discussed in the previous section. Magnetic bubble memory is an
20
arrangement of small magnetic area called bubble on a series of parallel track made of The Memory System
magnetic material. Each bubble represents a binary “1” and absence of a bubble on
magnetic material is interpreted as “0”. Binary data is read from the memory by
moving these bubbles towards the edge of a track under the influence of external
magnetic field. Magnetic field produces as bubbles remain persistent and do not
demagnetise by its own. So, magnetic bubble memories are non-volatile type
memories.

Solid State Devices (SSD)

Solid state drives also known as solid state storage devices are based on flash memory.
As discussed, flash memory, a non-volatile type memory uses semiconductor devices
to store the data. The major advantage of SSD is that it is purely an electronic device
i.e. unlike HDD, SSD does not have mechanical read/ write head other mechanical
components. Hence, reading and writing through SSD is faster than HDD. Now a
days, SSD have replaced HDD in computer systems, however, SSD disks are more
expensive than HDDs.

Check Your Progress 2

1. What will be the storage capacity of a disk, which has 8 recording surfaces, 32
tracks with each track having 64 sectors. Also, what would be the size of one
cylinder of the disk? You may assume that each sector can store 1 MB data.
……………………………………………………………………………………

……………………………………………………………………………………
2. What would be the rotation latency time for the disk specified above, if it has a
rotational speed of 6000 rpm?
……………………………………………………………………………………

……………………………………………………………………………………

3. What are the advantages and disadvantages of using SSD over HDD?
………………………………………………………………………………………………

………………………………………………………………………………

4. What are the differences between CLV and CAV disks?

……………………………………………………………………………………...
……………………………………………………………………………………...

5.5 RAID AND ITS LEVELS

Continuous efforts have been made by researchers to enhance the performance of the
secondary storage devices. As pointed out in previous sections performance of the
secondary storage is inversely affected by disk access time. Lower the disk access
time higher would be the performance. What about an idea of providing parallel
access to a group of disks? With the use of parallel access the amount of data that can
be accessed per unit time can be enhanced by a significant factor. A mechanism which
splits the data on multiple disk is known as data striping. Data access through parallel
access allows users to access data stored at multiple disks simultaneously, thus
reduces effective reading time. Does data striping ensure protection of data against
disk failure?

21
Basic Computer Organisation Another important factor for secondary storage is the reliability of data storage
system. Storing same data on more than one disks enhances reliability. If one disk
fails, then data can be accessed through another disk. Replicating data on multiple
disks is called mirroring. Mirroring brings redundancy in data. So many schemes have
been employed to enhance the performance and reliability of data and collectively
they are called as redundant arrays of inexpensive disks (RAID). Based on the trade-
off between reliability and performance RAID schemes have been categorises into
various RAID levels.
Data striping increases the data transfer speed as different data bytes are accessed in
parallel from different disks in a single disk access time. Whereas mirroring protects
data from disk failures. If one disk fails then same data is accessed from the copy of
the data stored in other disk.

RAID Levels

RAID Level-0: RAID level-0 implements block splitting of data with no protection
against disk failures. In block splitting, each block is stored in a different disk in the
array. For example, ith block of a file will be store in ( i mod n ) + 1 disk, where n is
the total number of disks in the array. In this case, a significant enhancement on the
performance can be observed as n blocks can be accessed (one each from each disk) in
a single disk access time.

(a) RAID Level 0

RAID Level-1: This level protects data by implementing mirroring. If a system has 2
disks then each block of information will be stored in both of the disks. This ensures,
if one disk fails then same copy of the block is accessed from the second disk.
Mirroring introduces redundancy unlike level-0 which increases the data transfer rate.

Strip 0 Strip 1 Strip 2 Strip 3 Strip 0 Strip 1 Strip 2 Strip 3

Strip 4 Strip 5 Strip 6 Strip 7 Strip 4 Strip 5 Strip 6 Strip 7
Strip 8 Strip 9 Strip 10 Strip 11 Strip 8 Strip 9 Strip 10 Strip 11

Strip 12 Strip 3 Strip 14 Strip 15 Strip 12 Strip 13 Strip 14 Strip 15

(b) RAID Level 1

RAID Level-2: This level uses error detection and correction bits, which are extra bits
used for detection and correction of a single bit error in a byte. This is why this level
is also known as memory-style error correction code organization. If one of the disk
fails then parity bits and remaining bits of the byte are used to recover the bit value.

22
 The Memory System

b0 b1 b2 b3 f0(b) f1(b) f2(b)

(c) RAID 2 (Redundancy through Hamming Code)

RAID Level-3: Single parity disk is used in this scheme. Parity bit for a sector is
computed and stored in a parity disk. During the access, parity bit of the sector is
computed and if computed parity bit is equal to the stored parity, the missing bit is 0
otherwise it is 1. This RAID level is also known as bit-interleaved parity organization.
Thus has an advantage over level-2 that only single parity disk is used as compare to
number of parity disks in level-2. The biggest drawback of this approach is that all the
disks are used for single I/O operation in computation of the parity bit which slows
down the disk access and also restricts parallel access.

b0 b1 b2 b3 Parity(b)

(d) RAID Level 3

RAID Level-4: This level uses block striping and one disk is used to keep parity
block. This is also called block-interleaved parity organization. The advantage of
block interleaving is that parity block along with corresponding blocks on other disks
is used to retrieve the damaged block or the blocks of the failed disk. Unlike in level-
3, block access reads one disk which allows parallel access to other blocks stored in
other disks in the array.

Block 0 Block 1 Block 2 Block 3 Parity (1-3)

Block 4 Block 5 Block 6 Block 7 Parity (4-7)

Block 8 Block 9 Block 10 Block 11 Parity (8-11)

Block 12 Block 13 Block 14 Block 15 Parity (12-15

(e) RAID 4 (Block level Parity)

23
Basic Computer Organisation RAID Level-5: This level stores block of data and parity in all the disks in the array.
One disk store the parity while data is spread out on different disks in the array. This
structure is also known as block-interleaved distributed parity.

Block 0 Block 1 Block 2 Block 3 Parity (0-3)

Block 4 Block 5 Block 6 Parity (4-7) Block 7

Block 8 Block 9 Parity (8-11) Block 10 Block 11

Block 12 Parity (12-15) Block 13 Block 14 Block 15

Parity (16-19) Block 16 Block 17 Block 18 Block 19

(f) RAID 5 (Block-level Distributed Parity)

RAID Level-6: Level-6 uses error correcting codes for recovery of damaged data
while other levels uses parity. It also provides protection against multiple disks
failures. For the recovery purposes, this arrangement is used to store redundant data
on some of the disks, hence it is also called as p + q redundancy scheme. Here, p is the
number of disks that store the error correcting codes while q is the number of disks
that store redundant data.

Block 0 Block 1 Block 2 Block 3 Parity (0-3) Parity (0-3)

Block 4 Block 5 Block 6 Parity (4-7) Q (4-7) Block 7

Block 8 Block 9 P (8-11) Q (8-11) Block 10 Block 11

Parity 12 Parity (12- Q (12-15) Block 13 Block 14 Block 15

15)

(g) RAID Level 6

Table below summarises characteristics of various RAID levels.

I/O Data
Request Transfer
RAID Typical
Category Features Rate Rate
Level Application
(Read (Read
/write) /write)
Applications
a) The disk is divided Large Small which requires
0 Striping into blocks or sectors. Blocks: Blocks: high performance
b) Non-redundant. Excellent Excellent for non-critical
data
a) Mirror disk which
contains the same data
is associated with every
disk. Good / May be used for
1 Mirroring Fair /fair
b) Data Recovery is fair critical files
simple. On failure, data
is recovered from the
mirror disk.

24
 a) All member disks The Memory System
participate in every I/O
request.
b) Synchronizes the
spindles of all the disks
to the same position. Not useful for
Parallel
2 c) The blocks are very Poor Excellent commercial
Access
small in size (Byte or purposes.
word).
d) Hamming code is
used to detect double-
bit errors and correct
single-bit error.
a) Parallel access as in
level 2, with small data
Large I/O request
blocks.
Parallel size application,
3 b) A simple parity bit is Poor Excellent
Access such as imaging
computed for the set of
CAD
data for error
correction.
a) Each member disk
operates independently,
which enables multiple
input/output requests in
parallel. Not useful for
Independent Excellent/ Fair /
4 b) Block is large and commercial
access fair poor
parity strip is created purposes.
for bits of blocks of
each disk.
c) Parity strip is stored
on a separate disk.
a) Allows independent
access as in level 4.
b) Parity strips are
distributed across all High request rate
Independent Excellent Fair /
5 disks. read intensive,
access / fair poor
b) Distribution avoids data lookup
potential input/output
bottleneck found in
level 4.
Also called the p+q
redundancy scheme, is
Application
much like level 5, but
Independent Excellent/ Fair / requiring
6 stores extra redundant
access poor poor extremely high
information to guard
availability
against multiple disk
failures.

Check Your Progress 3

1. What is the need of RAID?
……………………………………………………………………………………

……………………………………………………………………………………

2. Which RAID levels provide good data transfer rate?

……………………………………………………………………………………
25
Basic Computer Organisation ……………………………………………………………………………………
3. Which RAID level is able to fulfil large number of I/O requests?
……………………………………………………………………………………

……………………………………………………………………………………

5.6 SUMMARY

This unit introduces the concept of memory hierarchy, which is primarily required due
to the high cost per bit of high speed memory. The processing unit have register,
cache, main memory and secondary or auxiliary memory. The main memory consists
of RAM or ROM. This unit explains the logic circuit and organisation of RAM and
ROM. The unit also explains several different types of secondary storage memories.
The unit provide details on hard disk and its characteristics. It also gives details of
different kind of optical disk. The concept of access time and constant linear and
angular velocity has also been explained in details. For larger computer systems
simple hard disk is not sufficient, rather an array of disks called RAID are used for
such systems to provide good performance and reliability. The concept of RAID and
various levels of RAID has been defined in this unit. The next unit will introduce you
to the concept of high speed memories.

5.7 ANSWERS

Check Your Progress 1

1. RAM is a sequential circuit, volatile, requires refreshing (DRAM) and is a read/
write memory; ROM, PROM and EPROM are mostly non-volatile memories.
ROM is a combinational circuits. All these ROMs are written mostly once and
read many times.
2 Flash memory is a non-volatile semiconductor memory, where a section of the
memory or a set of memory words can be erased. They are portable and
mechanically robust as there is no mechanical movement in the memory to read-
write data. Flash memory is used in USB memory, SD and micro SD memory
cards used in cameras and mobile phones respectively.
3. (a) Since a word of data is 16 bits, it will have 16 data input and 16 data output
lines, if not multiplexed.
(b) The number of words are 16K, which is 214. Thus, 14 address lines would be
required.
4. The memory must select one of the 4K bytes, which is 212. In case a square array
is used (as shown in Figure 5.6), then 6 row address and 6 column address lines
would be needed, which can be multiplexed. So just 6 address lines be sufficient.
However, for a non square memory you may require all 12 address lines.
5. Two chips will be required to make 256  8 memory. 4 such combinations would
be required to make 1 MB memory. Thus, you will require 8 such chips.
Check Your Progress 2
1. Storage capacity of a disk = recording surfaces × tracks per surface × sectors per
track × size of each sector
Storage capacity of a disk = 8× 32 × 64 × 1 MB = 23×25×26×220 = 234 = 16 GB
One cylinder will have = = 8× 64 × 1 MB = 23×26×220 = 512 MB

26
2. The time of one rotation = 1/6000 min = 60/6000 sec = 1/100 sec= 10 millisec The Memory System
Rotational latency = on an average time of half rotation = 5 ms

3. SSD drives does not require any mechanical rotation, therefore are less prone to
failure. In addition, they are much faster than HDD. But they are more expensive
than HDD

4. The size of sectors on CLV disks is same on the entire disk, therefore, these disks
are rotated a different speed. Density of data is same in all the sectors. In CAV
disks the rotation speed is same, thus, sector size is more in the outer tracks.
However, reading/writing process, in general, is faster.
Check Your Progress 3
1. RAID are a set of storage devices put together for better performance and
reliability. Different kind of RAID levels have different objectives.

2. Good data transfer rate are provided by RAID level 0, 2 and 3.

3. Large number of I/O requests are fulfilled by RAID level 0, 1, 4,5 ,6.

27
 The Memory System
UNIT 6 ADVANCE MEMORY
ORGANISATION
Structure Page Nos.
6.0 Introduction
6.1 Objectives
6.2 Locality of Reference
6.3 Cache Memory
6.4 Cache Organisation
6.4.1 Issues of Cache Design
6.4.2 Cache Mapping
6.4.3 Write Policy
6.5 Associative Memory
6.6 Interleaved Memory
6.7 Virtual Memory
6.8 Summary
6.9 Answers

6.0 INTRODUCTION
In the last unit, the concept of Memory hierarchy was discussed. The Unit also
discussed different types of memories including RAM, ROM, flash memory,
secondary storage technologies etc. The memory system of a computer uses variety of
memories for program execution. These memories vary in size, access speed, cost and
type, such as volatility (volatile/ non-volatile), read only or read-write memories etc.
As you know, a program is loaded in to the main memory for execution. Thus, the size
and speed of the main memory affects the performance of a computer system. This
unit will introduce you to concepts of cache memory, which is small memory between
the processing unit and main memory. Cache memory enhances the performance of a
computer system. Interleaved memory and associative memories are also used as
faster memories. Finally, the unit discusses the concept of virtual memory, which
allows programs larger than the physical memory.

6.1 OBJECTIVES
After going through this Unit, you will be able to:
 explain the concept of locality of reference;
 explain the different cache organisation schemes;
 explain the characteristics of interleaved and associative memories;
 explain the concept of virtual memory.

6.2 LOCALITY OF REFERENCE

Memory system is one of the important component of a computer. A program is
loaded in to the main memory for execution. Therefore, a computer should have a
main memory, which should be as fast as its processor and should have large size. In
general, the main memory is constructed using DRAM technology which is about 50
to 100 times slower than the processor speed. This may slow down the process of
instruction execution of a computer. Using SRAM may change this situation as it is
almost as fast as a processor, however, it is a costly memory. So, what can you do? Is
it possible to use large main memory as DRAM, but use a faster small memory
between processor and main memory? Will such a configuration enhance performance
of a computer? This section will try to answer these questions.

5
Basic Computer Orga
anisation The importaant task of a computer
c is to
t execute insstructions. It has
h been observed that
on an average 80-85 percent of thee execution ttime is spennt by the proocessor in
accessing thhe instructionn or data fromm the main mmemory. The situation
s becoomes even
worst whenn instruction tto be executeed or data to be processedd is not present in the
main memoory.
Another facctor which has been observved by analyssing various programs
p is thhat during
the programm execution, the processsor tends to access a seection of thee program
instructions or data for a specific timee period. For example, wh hen a program m enters in
a loop struccture, it conttinues to acceess and execute loop stattements as loong as the
looping conndition is satiisfied. Similaarly, wheneveer a program calls a subrooutine, the
subroutine statements
s aree going to exxecute. In another case, when
w a data ittem stored
in an array or
o array like sstructure is acccessed then it is very likeely that eitherr next data
item or prevvious data iteem will be accessed by thee processor. AllA these phennomenons
are known as
a Locality off Reference orr Principle off Locality.
So, accordinng to the priinciple of loccality, for a specific timee period, the processor
tends to maake memory references
r cloosed to each oother or accesses the samee memory
addresses again
a and again. The earrlier type is known as sppatial locality ty. Spatial
locality speccifies if a datta item is acccessed then daata item storeed in a nearbyy location
to the data item just acccessed may be b accessed inn near futuree. There can bbe special
case of spaatial locality, which is terrmed as sequuence localityy. Consider a program
accesses thee elements oof a single dim mensional arrray, which is a linear data structure,
in the sequeence of its inddex. Such acccesses will reead/write on a sequence of memory
locations onne after the otther. This typee of locality, which
w is a case of spatial locality,
l is
referred to as
a sequence loocality.
Another typpe of localitty is the tem mporal localiity, if a dataa item is accessed or
referenced at
a a particularr time, then thhe same data item is expected to be acccessed for
i near future. Typically it is observedd in loop stru
some time in uctures and subroutine
s
call.
As shown in n Figure 6.1, when the proogram enters iin the loop strructure at linee 7, it will
execute the loop statemeents again andd again multipple times till the loop termminates. In
this case, processor
p needs to access instructions 9 and 10 freequently. On the other
hand, when a program acccesses a dataa item store inn an array, thhen in the nexxt iteration
it accesses a data item stoored in an adjjacent memorry location to the previous one.

Figure 6.1: Loop struucture

The localityy of referencce, be it spaatial or tempporal, suggessts that in most
m cases
accesses to a program innstruction annd data confinnes to a locallity, hence, a very fast
memory thaat captures thhe instructionss and data neearer to the current instrucctions and
data accessees can potenttially enhance the overall performancee of a compuuter. Thus,
attempts are continuously made to utilize the precious time of the processor efficiently The Memory System
A high speed memory, called cache memory, was developed. Cache memory utilises
the principle of locality to reduce the memory references to the main memory by
keeping not only the currently referenced data item but also the nearby data items. The
cache memory and its organisation is discussed in the next sections.

6.3 CACHE MEMORY

A processor makes many memory references to execute an instruction. A memory
reference to the main memory is time consuming as main memory is slower compared
to the processing speed of the processor. These memory references, in general, tends
to form a cluster in the memory, whether it is a loop structure, execution of a
subroutine or an access to a data item stores in an array.

If you keep the content of the cluster of expected memory references in a small,
extremely fast memory then processing time of an instruction can be reduced by a
significant amount. Cache memory is a very high speed and expensive memory as
compared to the main memory and its access time is closer to the processing speed of
the processor. Cache memory act as a buffer memory between the processor and the
main memory.

Because cache is an expensive memory so its size in a computer system is also very
small as compared to the main memory. Thus, cache stores only those memory
clusters containing data/ instructions, which have been just accessed or going to be
accessed in near future. Data in the cache is updated based on the principle of locality
explained in the previous section.

How data access time is reduced significantly by using cache memory?

Data in main memory is stored in the form of fixed size blocks/pages. Cache memory
contains some blocks of the main memory. When processor wants to read a data item
from the main memory, a check is made in the cache whether data item to be accessed
is present in the cache or not. If data item to be accessed is present in the cache then it
is read by the processor from the cache. If data item is not found in the cache, a
memory reference is made to read the data item from the main memory, and a copy of
the block containing data item is also copied into the cache for near future references
as explained by the principle of locality. So, whenever processor attempts to read the
data item next time, it is likely that the data item is found in the cache and saves the
time of memory reference to the main memory.

Figure 6.2: Cache Memory

As shown in the Figure 6.2, if requested data item is found in the cache it is called as
cache hit and data item will be read by the processor from the cache. And if requested
data item is not found in cache, called cache miss, then a reference to the main
memory is made and requested data item is read and block containing data item will
also be copied into the cache.
7
Basic Computer Organisation Average access time for any data item is reduced significantly by using cache then
without using cache. For example, if a memory reference takes 200 ns and cache takes
20 ns to read a data item. Then for five continuous references will take:
Time taken with cache : 20 (for cache miss) + 200 (memory reference)
+ 4 x 20 (cache hit for subsequent access)
= 300 ns

Time without cache : 5 x 200 = 1000 ns

In the given example, the system first looks into the cache for the requested data item.
As it is the first reference to the data item it will not be present in the cache, called as
cache miss, and thus, requested data item will be read from the main memory. For
subsequent requests of the same data item, the data item will be read from the cache
only and no references will be made to the main memory as long as the requested data
remains in the cache.

Effective access time is defined as the average access time of memory access, when a
cache is used. The access time of memory access is reduced in case of a cache hit,
whereas it increases in case of cache miss. In the above mentioned example processor
takes 20 + 200 ns for a cache miss, whereas it takes only 20 ns for each cache hit.
Now suppose, we have a hit ratio of 80%, i.e. 80 percent of times a data item would
be found in the cache and 20 % of the times it would be accessed from the main
memory. So effective access time (EAT) will be computed as :

effective access time = (cache hit x data access time from cache only )
+(cache miss x data access time from cache and main memory)

effective access time = 0.8 (hit ratio) x 20 (cache hit time)

+ 0.2( miss ratio) x 220 (cache miss and memory reference)

effective access time = 0.8 x 20 + 0.2 x 220

= 16 + 44
= 60 ns

From the example it is clear that cache reduces the average access time and effective
access time for a data item significantly and enhance the computer performance.

Check Your Progress 1

1. What is the importance of locality of reference?

……………………………………………………………………………………
……………………………………………………………………………………
……………………………………………………………………………………
2. What is block size of main memory for cache transfer?
……………………………………………………………………………………
……………………………………………………………………………………
……………………………………………………………………………………

3. Hit ration of computer system is 90%. The cache has an access time of 10ns,
whereas the main memory has an access time of 50ns. Computer the effective
access time for the system.
……………………………………………………………………………………
……………………………………………………………………………………
……………………………………………………………………………………
8
 The Memory System

6.4 CACHE ORGANISATION

The main objective of using cache is to decrease the number of memory references to
a significant level by keeping the frequently accessible data/ instruction in the cache.
Higher the hit ratio (number of times requested data item found in cache / total
number of times data item is requested), lower would be the references to the main
memory. So there are number of questions that need to be answered while designing
the cache memory. These Cache design issues are discussed in the next subsection.

6.4.1 Issues of Cache Design

In this section, we present some of the basic questions that should be asked for
designing cache memory.

What should be the size of cache memory?

Cache is an extremely fast but very expensive memory as compared to the main
memory. So large cache memory may shoot up the cost of the computer system and
too small cache might not be very useful in real time. So, based on various statistical
analyses, if a computer system has 4 GB of main memory then the size of the cache
may go up to 1MB.

What would be the block size for data transfer between cache and main memory?

Block size directly affects the cache performance. Higher block size would ensure
only fewer number of blocks in cache, whereas small block size contains fewer data
items. As you increase the block size, the hit ratio first increases but it decreases as
you further increase the block size. Further increase in block size will not necessarily
result in access of newer data items, as probability of accessing data items in the block
with larger number of data items tends to decrease. So, optimal size of the block
should be chosen to maximise the hit ratio.

How blocks are going to be replaced in cache?

As execution of the process continues, the processor requests for new data items. For
new data items and thus, new blocks to be present in the cache, the blocks containing
old data items must be replaced. So there must be a mechanism which may select the
block to be replaced which is least likely to be needed in near future.

When changes in the blocks will be written back on to the main memory?

During the program execution, the value of a data item in a cache block may get
changed. So the changed block must be written back to the main memory in order to
reflect those changes to ensure data consistency. So there must be a policy, which may
decide when the changed cache block is written back to the main memory.
In certain computer organisations, the cache memory for data and instruction are
placed separately. This results in separate address spaces for the instructions and data.
These separate caches for instructions and data are known as instruction cache and
data cache respectively. If processor requests an instruction, then it is provided by the
instruction cache, whereas requested data item is provided by the data cache. Using
separate cache memories for instruction and data enhances computer performance.
While some computer systems implements different cache memories for data and
instructions other implements multiple level of cache memories. Two level cache
popularly known as L1 cache and L2 cache is most commonly used. Size of level 1
cache or L1 cache is smaller than the level 2 or L2 cache. Comparatively more
frequently used data/ instructions are stored in L1 cache.
9
Basic Computer Organisation

As discussed earlier, the main memory is divided into blocks/ frames/ pages of k
words each. Each word of the memory unit has a unique address. A processor requests
for read/write of a memory word. When a processor's request of a data item cannot be
serviced by cache memory, i.e. a cache miss occurs, the block containing requested
data item is read from the main memory and a copy of the same is stored in cache
memory. A cache memory is organised as a sequence of line. Each cache line is
identified by a cache line number. A cache line stores a tag and a block of data. Cache
and main memory structure is shown in Figure 6.3. General structure of cache
memory having M lines and N=2n main memory size is shown in figure 6.3(a) and
figure 6.3(b) respectively.

(a) Cache structure

(b) Main Memory structure

Figure 6.3: Structure of Cache and Main Memory
An example of cache memory of size 512 words is shown in Figure 6.4. The example
shown in Figure 6.4 has a main memory of 64 K words of 16 bits each and cache
10
memory can have 512 words of 16 bits each. To read a data item processor sends a 16 The Memory System
bit address to the cache and if cache misses then the data item/ word is fetched from
the main memory and accessed data item/ word is also copied into the cache. Please
note that the size of block is just 1 memory word in this case.

Figure 6.4: Example of Cache and Main Memory

6.4.2 Cache Mapping
As discussed earlier, a request of processor to access a main memory is to checked in
cache memory. Where can a block of main memory be places in cache and how
processor can determine, if the data requested is present in cache? Answer to these
questions are provided by cache mapping scheme. A mapping mechanism maps the
block from the main memory to a cache line. The mapping is required as cache is
much smaller in size than the size of the main memory. So only few blocks from the
main memory can be stored in cache. There are three types of mapping in cache:
Direct Mapping:
Direct mapping is the simplest amongst all three mapping schemes. It maps each
block of main memory into only one possible cache line. Direct mapping can be
expresses as a modulo M function, where M is the total number of cache lines as
shown:
𝑖 𝑗 𝑚𝑜𝑑𝑢𝑙𝑜 𝑀
where, i = number of cache line to which main memory block would
be mapped.
j = the block address of main memory, which is being requested
M = total number of cache lines
So, line 0 of the cache will store block 0, M, 2M….. and so on. Similarly, line 1 of
cache will store block 1, M + 1, 2M + 1, and so on.
An address of main memory word, as shown in Figure 6.3(b), consists of n bits. This
address of each word of main memory has two parts: block number (n-k bits) and
word number within the block (k bits). Here, each block of the main memory contains
2k number of words. The cache memory interprets n-k bit block number in to two parts
11
Basic Computer Organisation as: tag and line number. As indicated in Figure 6.3(a), the cache memory contains M
lines. Assuming m address bits (2m = M) are used to identify each line, then most
significant (n-k) - m bits of (n-k) bit block number are interpreted as tag and m bits are
used as line number of the cache. Please note the tag bits are used to identify, which of
the main memory block is presently in that cache line. The following diagram
summarizes the bits of main memory address and related cache address:
Main Memory Address (n bits)

Main Memory Block Address ((n-k) bits) Block address size (k bits)

Address bits for identifying

Address for Tag Address mapping to Cache Line
a word in a Block

((n-k)-m) bits for tag m bits to identify the Cache line Block address size (k bits)

Figure 6.5: Main Memory address to Cache address mapping in Direct

mapping Scheme
Please note the following points in the diagram given above.
The size of Main Memory address: n bits
Total number of words in main memory: 2n
The size of a Main memory block address: most significant (n-k) bits
Number of words in each block: 2k
In case, a referenced memory address is in cache, bits in the tag field of the main
memory address should match the tag filed of the cache.
Example: Let us consider a main memory of 16 MB having a word size of a byte and
a block size is of 128 bits or 16 words (one word is one byte in this case). The cache
memory can store 64 KB of data. Determine the following:
a) Size of various addresses and fields
c) how will you determine that a hexadecimal address is in cache memory,
assuming a direct mapping cache is used?
Solution:
a) Size of main memory= 16MB = 224 Bytes
Each block consists of 16 words, thus total number of blocks in main
memory would be = 224/ 16 = 220 blocks, thus n = 24 and
k = 4 (as 24=16). Therefore, main memory block address (n-r) = 20
Data size of cache is 64 KB = 216 Bytes
Total number of cache lines (M) = cache size/ block size = 216 / 24 = 212 ,
therefore, number of cache lines = 212 and m = 12
Length of address field to identify a word in a Block (k) = 4 bits
Length of address to identify a Cache line (m) = 12 bits
Length of Tag field = (24- 4) - 12 = 8 bits.
Thus, a main memory address to cache address mapping for the given example would
look like this:
Main Memory Address n = 24 bits
Address of a Block of data = 20 bits k=4 bits
Address mapping for direct cache mapping scheme
Tag = 8 bits Cache line number address m = 12 bits k=4 bits
Figure 6.6: Direct Cache mapping
12
 The Memory System

b) Consider a 24 bit main memory address in hexadecimal as FEDCBA. The

following diagram will help in identifying, if this address is in the cache memory or
not in case direct mapping scheme is used.

Main Memory Address n = 24 bits = 6 hex digits

F E D C B A
Address of a Block of data = 20 bits k=4 bits
FEDCB A
Address mapping for direct cache mapping scheme
Tag = 8 bits Cache line number address m = 12 bits k=4 bits
FE DCB A
1111 1110 1101 1100 1011 1010
Figure 6.7: Direct Cache mapping example

Now, the following steps will be taken by the processing logic of processing unit and
hardware of Cache memory:
1. The tag number (FE in this case) is compared against the Tag number of data
stored in the cache line (DCB in this case).
2. In case both are identical
then (this is the case of cache hit): Ath word from the cache line DCB is
accessed by the processing logic.
else (this is a case of cache miss): The cache line 16 words data is read to
cache memory line (DCB) and its tag number is now FE. The
required Ath word is now accessed by the processing logic
Direct mapping is very easy to implement but has a disadvantage as location in which
a specific block is to be stored in cache is fixed. This arrangement leads to low hit
ratio as when processor wants to read two data items belongs to two different blocks,
which map to single cache location, then each time other data item is requested, the
block in the cache must be replaced by the requested one. This phenomenon is also
known as thrashing.
Associative Mapping:
Associative mapping is the most flexible mapping in cache organisation as it allows to
store any block of the main memory in any of the cache line/or location. It uses
complete (n-k) bits of block address field as a tag field. Cache memory stores (n-k)
bits of Tag and (2k × Word Size in bit) data. When a data item/ word is requested, (n-
k) bit tag field is used by the cache control logic to search the all the tag fields stored
in the cache simultaneously. If there is a match (cache hit) then corresponding data
item is read from the cache, otherwise (cache miss) the block of data that contains the
word to be accessed is read from the main memory. It replaces any of the cache line.
In addition, the block address of the accessed block from the main memory replaces
the tag of the cache line. It is also the fastest mapping amongst all types. Different
block replacement policies are used for replacing the existing cache content by newly
read data, however, those are beyond the scope of this unit. This mapping requires
most complex circuitry, as it requires all the cache tags to be checked simultaneously
with the block address of the access request.
Main Memory Address :
Address bits for identifying
Address of a block of data is same as Tag
a word in a Block
(n-k) bits k bits

Every line of Associative Cache has the following format:

13
Basic Computer Organisation
Tag Data Block of k words

(n-k) bits Data bits

Figure 6.8: Associative mapping

The following example explains the set associative mapping.
Example: Let us consider a main memory of 16 MB having a word size of a byte and
a block size is of 128 bits or 16 words (one word is one byte in this case). The cache
memory can store 64 KB of data. Determine the following size of various addresses
and fields, if associative mapping is used
Solution:
Size of main memory= 16MB = 224 Bytes
Each block consists of 16 words, thus total number of blocks in main
memory would be = 224/ 16 = 220 blocks, thus n = 24 and
k = 4 (as 24=16). Therefore, main memory block address (n-r) = 20
Data size of cache is 64 KB = 216 Bytes
Total number of cache lines (M) = cache size/ block size = 216 / 24 = 212 ,
therefore, number of cache lines = 212 and m = 12
Length of Tag field = (24- 4) = 20 bits.
Size of data = 2k × Word Size in bit = 24 × 8 = 128 bits.
Thus, size of one line of cache = 128+20=148 bits.
Set Associative Mapping:
The major disadvantage of direct mapping is that location of the cache line onto which
a memory block is going to be mapped is fixed which results in poor hit ratio and
unused cache locations. The associative mapping removes these hurdles and any block
of memory can be stored anywhere in cache location. But associative cache uses
complex matching circuit and big tag size. Set Associative mapping reduces the
disadvantages of both the above mentioned cache mapping techniques and is built on
their strengths. In set associative mapping scheme, cache memory is divided into v
sets where each set contains w cache lines. So, total number of cache lines M is given
as:
𝑀 𝑣𝑥𝑤
where v is the number of sets and w is the number of cache lines in v
The cache mapping is done using the formula:
𝑖 𝑗 𝑚𝑜𝑑𝑢𝑙𝑜 𝑣
where i is the set number and j is the block address of word to be accessed.
Cache control logic interprets the address field as a combination of tag and set fields
as shown:

Tag Set Word

((n-k)-d) bits d bits k bits

Figure 6.8: Set Associative mapping

14
Cache mapping logic uses d-bits to identify the set as 𝑣 2 and ((n-k)-d)) bits are The Memory System
used to represent the tag field. In set-associative mapping, a block j can be stored at
any of the cache line of set i. To read a data item, the cache control logic first
simultaneously looks into all the cache lines using ((n-k)-d)) bits of tag field of the set
identified by d-bits of the set field, otherwise a data item is read from the main
memory and corresponding data is copied into the cache accordingly. Set associative
mapping is also known as w-way set-associative mapping. It uses lesser number of
bits (((n-k)-d) bits) as compare to (n-k) bits in associative mapping in tag field.
A comprehensive example showing possible locations of main memory blocks
in Cache for different cache mapping schemes is discussed next.

Example: Assume a main memory of a computer consists of 256 bytes, with

each memory word of one byte. The memory has a block size of 4 words. This
system has a cache which can store 32 Byte data. Show how main memory
content be mapped to cache if (i) Direct mapping (ii) Associative mapping and
(iii) 2 way set associative memory is used.
Solution:
Main memory size = 256 words (a word = one byte) = 28 ⇒ n=8 bits
Block Size = 4 words = 22 ⇒ k=2 bits
The visual representation of this main memory:
Block Number of Memory Location Address Assume data
memory Block Word stored
in equivalent decimal Address Address in the location
000000 00 1001010
000000 01 1101010
0
000000 10 0001010
000000 11 0001010
000001 00 1111010
000001 01 0101010
1
000001 10 1001010
000001 11 1101010
000010 00 1101010
000010 01 0001010
2
000010 10 0101010
000010 11 0011010
… … … …
000111 00 0000010
000111 01 0000011
7
000111 10 0000011
000111 11 0001110
… … … …
111111 00 1111010
111111 01 1111011
63
111111 10 0101011
111111 11 0101110
Figure 6.9: An example of Main Memory Blocks

(i) Direct Mapping Cache:

The size of cache = 32 bytes
The block size of main memory = words in one line of cache =4 ⇒ k=2 bits
The cache has = 32 /4 = 8 lines with each line storing 32 bits of data (4 words)
Therefore, m=3 as 23 = 8
15
Basic Computer Organisation Thus, Tag size = (n-k) - m = (8 - 2) - 3 = 3

The address mapping for an address: 11111101

Block Address of Main Address of a word in a
Memory Block
111 111 01
111 111 01
Tag Line
Number
Line Number = 111 = 7 in decimal
Tag = 111

The address mapping for an address: 00001011

Block Address of Main Address of a word in a
Memory Block
000 010 11
000 010 11
Tag Line
Number
Line Number = 010 = 2 in decimal
Tag = 000
The following cache memory that uses direct mapping shows these two words
(along with complete block in the cache)
Line Number Contents of Cache Memory
of Cache Tag of Data in Cache = 4 words = 32 bits
in Decimal Data Word 11 Word 10 Word 01 Word 00
0
1
2 000 0011010 0101010 0001010 1101010
3
4
5
6
7 111 0101110 0101011 1111011 1111010
Figure 6.10: An example Cache memory with Direct mapping

The access for an address: 00011110

Block Address of Main Address of a word in a
Memory Block
000 111 10
000 111 10
Tag Line
Number

In case, a word like 00011110 is to be accessed, which is not in the cache

memory and as per mapping should be mapped to line number 111 =7, the
cache access logic will compare the tags, which are 000 for this address, and
111 in the cache line 7. This is the situation of cache miss, so accordingly this
block will replace the content stored in line 7, which after replacement is
shown below:
7 000 0001110 0000011 0000011 0000010
16
Please note the change in data value in the cache line 7. The Memory System

(ii) Associative Mapping Cache:

The size of cache = 32 bytes
The block size of main memory = words in one line of cache =4 ⇒ k=2 bits
Therefore, cache has = 32 /4 = 8 lines with each line storing 32 bits of data (4
words)
Tag size = n-k = (8 - 2) = 6
The address mapping for an address: 11111101
Block Address of Main Address of a word in a
Memory Block
111111 01
111111 01
Tag

The address mapping for an address: 00001011

Block Address of Main Address of a word in a
Memory Block
000010 11
000010 11
Tag

The following associative cache shows these two words.

Line Number Contents of Cache Memory
of Cache Tag of Data in Cache = 4 words = 32 bits
in Decimal Data Word 11 Word 10 Word 01 Word 00
0 111111 0101110 0101011 1111011 1111010
1 000010 0011010 0101010 0001010 1101010
2 000111 0001110 0000011 0000011 0000010
3
4
5
6
7
Figure 6.11: An example Cache memory with Associative mapping

The access for an address: 00011110

Block Address of Main Address of a word in a
Memory Block
000111 10
000111 10
Tag Number

A word like 00011110 can in any cache line, for example, in the cache memory
shown above it is in line 2 and can be accessed.
(iii) 2way set associative Mapping:
The size of cache = 32 bytes
The block size of main memory = words in one line of cache =4 ⇒ k=2 bits
The number of lines in a set (w) = 2 (this is a 2 way set associative memory)
The number of sets (v) = Size of cache in words/(words per line × w )
= 32/(4×2) =4
Thus, set number can be identified using 2 bits as 22 = 4
17
Basic Computer Organisation Tag size = (n-k)-v = (8 - 2) - 2 = 4
The address mapping for an address: 11111101
Block Address of Main Memory Address of a word in a
Block
1111 11 01
1111 11 01
Tag Set Number
Set number = 11 = 3 in decimal
Tag = 1111
The address mapping for an address: 00001011
Block Address of Main Memory Address of a word in a
Block
0000 10 11
0000 10 11
Tag Set Number
Set number = 10 = 2 in decimal
Tag = 0000

Contents of Cache Memory Way 0 Set Contents of Cache Memory Way 1

Tag # Tag Data in Cache = 4 words = 32
bits
Word Word Word Word Word Word Word Word
11 10 01 00 11 10 01 00
0
1
2 0000 0011010 0101010 0001010 1101010
1111 0101110 0101011 1111011 1111010 3 0001 0001110 0000011 0000011 0000010
Figure 6.12: An example Cache memory with Set Associative mapping

The access for an address: 00011110

Block Address of Main Address of a word in a
Memory Block
0001 11 10
0001 11 10
Tag Set
Number
Set number = 11= 3 in decimal
Tag = 0001
Word 00011110 can be stored and accessed from the cache set 11 at the second
line (way 1).

6.4.3 Write Policy

Many processes read and write data in cache and main memory either by the
processor or by the input/ output devices. Multiple read possess no challenge to the
state of the data item, as you know, cache maintains a copy of frequently required data
items to improve the system performance. Whenever a process writes/ updates the
values of the data item in cache or in main memory, it must be updated in the copy as
well. Otherwise it will lead to an inconsistent data and cache content may become
invalid. Problems associated with writing in cache memories can be summarised as:

• Caches and main memory can be altered by multiple processes which may
result in inconsistency in the values of the data item in cache and main
memory.
18
 The Memory System
• If there are multiple CPUs with individual cache memories, data item written
by one processor in one cache may invalidate the value of the data item in
other cache memories.
These issues can be addressed in two different ways:
1. Write through: This writing policy ensures that if a CPU updates a cache,
then it has to write/ or make the changes in the main memory as well. In
multiple processor systems, other CPUs-Cache need to keep an eye over the
updates made by other processor's cache into the main memory and make
suitable changes accordingly. It creates a bottleneck as many CPUs try to
access the main memory.
2. Write Back: Cache control logic uses an update bit. Changes are allowed to
write only in cache and whenever a data item is updated in the cache, the
update bit of the block is set. As long as data item is in the cache no update is
made in the main memory. All those blocks whose update bit is set is replaced
in the main memory at the time when the block is being replaced in the cache.
This policy ensures that all the accesses to the main memory are only through
cache, and this may create a bottleneck.
You may refer to further readings for more details on cache memories.
Check Your Progress 2
1. Assume that a Computer system have following memories:
RAM 64 words with each word of 16 bits
Cache memory of 8 Blocks (block size of cache is 32 bits)
Find in which location of cache memory a decimal address 21 can be found if
Associative Mapping is used.
……………………………………………………………………………………
……………………………………………………………………………………

2. For the system as given above, find in which location of cache memory a decimal
address 27 will be located if Direct Mapping is used.
…………………………………………………………………………………………
………………………………………………………………………………
3. For the system as given above, find in which location of cache memory a decimal
address 12 will be located if two way set associative Mapping is used.
……………………………………………………………………………………
……………………………………………………………………………………

6.5 MEMORY INTERLEAVING

As you know that cache memory is used as a buffer memory between processor and
the main memory to bridge the difference between the processor speed and access
time of the main memory. So, when processor requests a data item, it is first looked
into the cache and if data item is not present in the cache (called cache miss), only
then main memory is accessed to read the data item. To further enhance the
performance of the computer system and to reduce the memory access time of the
main memory, in case of cache miss, the concept of memory interleaving is used.
Memory interleaving is of three type, viz. lower order memory interleaving, higher
order memory interleaving and hybrid memory interleaving. In this section we will
discuss the lower order memory interleaving only. Discussion on other memory
interleaving techniques is beyond the scope of this unit.
In memory interleaving technique, main memory is partitioned into n number of equal
sized modules called as memory banks and technique is known as n-way memory
19
Basic Computer Organisation interleaving. Where each memory module has its own memory address register, base
register and instruction register, thus each memory bank can be accessed individually
and simultaneously. Instructions of a process are stored in successive memory banks.
So, in a single memory access time n successive instructions of the process can be
accessed from n memory banks. For example, suppose main memory is divided into
four modules or memory banks denoted as M1, M2, M3 and M4 then first n
instructions of a process will be stored as: first instruction in M1, second instruction in
M2, third instruction in M3, fourth instruction in M4 and again fifth instruction in M1
and so on.
When processor issues a memory fetch command during the execution of the
program, memory access system creates n consecutive memory addresses and places
them in respective memory address register of all memory banks in the right order.
Instructions are read from all memory modules simultaneously and loads them into n
instruction registers. Thus, each fetch for a new instruction results in the loading of n
consecutive instructions in n instruction registers of the CPU, in the time of a single
memory access. Figure 6.13 shows the structure of 4-way memory interleaving. The
address is resolved by interpreting the least significant bits to select the memory
module, and rest of the most significant bits are the address in the memory module.
For example, in an 8-bit address and 4-way memory interleaving, two least significant
bits will be used for module selection and six most significant bits will be used as an
address in the module.
8-bit address in 4-way memory interleaving
Address in the module Module Selection
6 bits 2 bits

Figure 6.13: Address mapping for Memory interleaving

The following example demonstrates how the main memory words be distrib-
uted to different interleaved memory modules. For this example, only a four bit
address of main memory is used.
Main Memory Module 00 Module 01
Address Data ---- Address Data ---- Address Data
0000 10 00 10 00 20
0001 20 01 50 01 60
0010 30 10 46 10 25
0011 40 11 23 11 78
0100 50
0101 60
0110 80
0111 76
1000 46
1001 25
1010 58 Module 10 Module 11
1011 100 Address Data Address Data
1100 23 00 30 00 40
1101 78 01 80 01 76
1110 35 10 58 10 100
1111 11 11 35 11 11

Figure 6.14: Example of Memory interleaving

20
Please note in the figure above how various data values are distributed in the modules. The Memory System

6.6 ASSOCIATIVE MEMORY

Though cache is a high speed memory but still it needs to search the data item stored
in it. Many search algorithms have been developed to reduce the search time in a
sequential or random access memory. Searching time of a data item can be reduced
further to a significant amount of data item is identified by its content rather by the
address. Associative memory is a content addressable memory (CAM), that is
memory unit of associative memory is addressed by the content of the data rather by
the physical address. The major advantage of this type of memory is that memory can
be searched in parallel on the basis of data. When a data item is to be read from an
associative memory, the content of the data item, or part of it, is specified. The
memory locates all data items, which matches the specified content, and marks them
for reading. Because of the architecture of the associative memory, complete data item
or a part of it can be searched in parallel.

Hardware Organization
Associative memory consists of a memory array and logic for m words with n bits per
word as shown in block diagram in Figure 6.15. Both argument register (A) and key
register (K) have n bits each. Each bit of argument and key register is for one bit of a
word. The match register M has m bits, one each for each memory word.
The key register provides a mask for choosing a particular field or key in the argument
word. The entire argument is compared with each memory word only if the key
register contains all 1s. Otherwise, only those bits in the argument that have 1s in their
corresponding positions of the key register are compared. Thus, the key provides a
mask or identifying information, which specifies how reference to memory is made.
The content of argument register is simultaneously matched with every word in the
memory. Corresponding bits in the mach register is set by the words that have match
with the content of the argument register. Set bits of the matching register indicates
that corresponding words have a match. Thereafter, memory is accessed sequentially,
to read only those words whose corresponding bits in the match register have been set.

21
Basic Computer Organisation

Figure 6.15: Block diagram of associative memory

Example: Consider an associative memory of just 2 bytes. The content register and
argument registers are also shown in the diagram.

Description The content of associative Memory Match Word

Argument Register 0 1 1 0 0 0 0 1
Key Register 1 1 1 1 0 0 0 0
Bits to be matched 0 1 1 0
Word 1 0 1 1 0 0 1 1 0 Match
Word 2 1 0 0 1 1 0 0 0 Not machted
Figure 6.16: An Example of Associative matching

Please note as four most significant bits of key register are 1, therefore only they are
matched.

6.7 VIRTUAL MEMORY

As we know that a program is loaded into the main memory for execution. The size of
the program is limited by the size of the main memory i.e. cannot load a program in
to the main memory whose size is larger than the size of the main memory. Virtual
memory system allows users to write programs even larger than the main memory.
Virtual memory system works on the principle that portions of a program or data are
loaded into the main memory as per the requirement. This gives an illusion to the
programmer that they have very large main memory at their disposal. When an
address is generated to reference a data item, virtual address generated by the
processor is mapped to a physical address in the main memory. The translation or
mapping is handled automatically by the hardware by means of a mapping table.

22
Let us say, you have a main memory of size 256K (218)words. This requires 18-bits to The Memory System
specify a physical address in main memory. A system also has an auxiliary memory as
large as the capacity of 16 main memories. So, the size of the auxiliary memory is
256K ×16 = 4096 K which requires 24 bits to address the auxiliary memory. A 24-bit
virtual address will be generated by the processor which will be mapped into an 18-bit
physical address by the address mapping mechanism as shown in Figure 6.17.

Figure 6.17: Virtual Address Mapping to Physical Address

In a multiprogramming environment, programs and data are transferred to and from
auxiliary memory and main memory based on demands imposed by the processor. For
example program 1 is currently being executed by the CPU. Only program 1 and a
portion of its associated data as demanded by the processor are loaded from secondary
memory into the main memory. As programs and data are continuously moving in and
out of the main memory, space will be created and thus both program or its portions
and data will be scattered throughout the main memory.

Check Your Progress 3

1. How can interleaved memory can be used to improve the speed of main memory
access?
……………………………………………………………………………………
…………………………………………………………………………………
2. Explain the advantages of using associative memory?
……………………………………………………………………………………
……………………………………………………………………………………

3. What is the need of virtual memory.

……………………………………………………………………………………
……………………………………………………………………………………

6.8 SUMMARY
This unit introduces you to the concept relating to cache memory. The unit defines
some of basic issues of cache design. The concept of cache mapping schemes were
explains in details. The direct mapping cache uses simple modulo function, but has
limited use. Associative mapping though allows flexibility but uses complex circuitry
and more bits for tag field. Set-associative mapping uses the concept of associative
and direct mapping cache. The unit also explain the use of memory interleaving,
which allows multiple words to be accessed in a single access cycle. The concept of
23
Basic Computer Organisation content addressable memories are also discussed. The cache memory, memory
interleaving and associative memories are primarily used to increase the speed of
memory access. Finally, the unit discusses the concept of virtual memory, which
allows execution of programs requiring more than physical memory space on a
computer. You may refer to further readings of the block for more details on memory
system.

6.9 ANSWERS
Check Your Progress 1

1. While executing a program during a period of time or during a specific set of

instructions, it was found that memory reference to instructions and data tend to
cluster to a set of memory locations, which are accessed frequently. This is
referred to as locality of reference. This allows you to use a small memory like
cache, which stores the most used instructions and data, to enhance the speed of
main memory access.
2. Typical block size of main memory for cache transfer may be 1, 2, 4, 8, 16, 32
words.

3. effective access time = 0.9 (hit ratio) x 10 (cache hit time)

+ 0.1( miss ratio) x (50+10) (cache miss and memory reference)
effective access time = 0.9 x 10 + 0.1x 60
= 9+6
= 15 ns
Check Your Progress 2

1. Main memory size = 64 words (a word = 16 bits) = 26 ⇒ n=6 bits

Block Size = 32 bits = 2 words = 21 ⇒ k=1 bit
The size of cache = 8 blocks of 32 bits each = 8 lines
Tag size for associative mapping = n-k = (6 - 1) = 5
The address mapping for an address: 21 in decimal that is 010101
Block Address Address of a word in a
Block
01010 1
01010 1
Tag

In set associative memory the given tag can be stored in any of the 8
lines.
2. Main memory size = 64 words (a word = 16 bits) = 26 ⇒ n=6 bits
Block Size = 32 bits = 2 words = 21 ⇒ k=1 bit
The size of cache = 8 blocks of 32 bits each = 8 lines ⇒ m=3 bits
Tag size for direct mapping = (n-k) - m = (6 - 1) - 3 = 2
The address mapping for an address: 27 in decimal that is 011011

Block Address of Main Address of a word in a

Memory Block
01 101 1
01 101 1
Tag Line Number
The required word will be found in line number 101 or 5 (decimal)

3. Main memory size = 64 words (a word = 16 bits) = 26 ⇒ n=6 bits

Block Size = 32 bits = 2 words = 21 ⇒ k=1 bit
24
 The number of sets (v) = 4 sets of 2 lines each, thus, d = 2 The Memory System

Tag size for direct mapping = (n-k) - d = (6 - 1) - 2 = 3

The address mapping for an address: 12 in decimal that is 001100
Block Address of Main Address of a word in a
Memory Block
001 10 0
001 10 0
Tag Set Number
Set number = 10 = 2 in decimal
Thus, required word can be in any of the line in set number 2.

Check Your Progress 3

1. Memory interleaving divides the main memory into modules. Each of these
module stores the words of main memory as follows (example uses 4 modules
and 16 word main memory.
Module 0: Words 0, 4, 8, 12 Module 1: Words 1, 5, 9, 13
Module 2: Words 2, 6, 10, 14 Module 3: Words 3, 7, 11, 15
Thus, several consecutive memory words can be fetched from the interleaved
memory in one access. For example, in a typical access words 4, 5, 6, and 7 can
be accessed simultaneously from the Modules 0, 1, 2 and 3 respectively.

2. Associative memory do not use addresses. They are accessed by contents. They
are very fast.

3. Virtual memory is useful, when large programs are to be executed by a computer

having smaller physical memory.

25
 The Input / Output
UNIT 7 – INPUT/OUTPUT ORGANISATION System

Structure
7.0 Introduction
7.1 Objectives
7.2 Input/Output (I/O) Devices
7.3 The Input/Output (I/O) Interface
7.3.1 System Bus and I/O Interface Modules
7.3.2 I/O and Memory Bus
7.3.3Isolated and Memory-Mapped I/O
7.4 Device Controllers
7.4.1 Device Controller and I/O Interface
7.5 Device Drivers
7.6 Asynchronous Data Transfer
7.6.1 Strobe Control
7.6.2 Handshaking
7.7 Input/Output (I/O) Techniques
7.7.1 Programmed I/O
7.7.2 Interrupt-Driven I/O
7.7.3 Interrupt Handling
7.7.4 Direct Memory Access (DMA)
7.8 Input Output Processor (IOP)
7.8.1 Characteristics of I/O Channels
7.9 External Communication Interfaces
7.10 Summary
7.11 Solutions /Answers

7.0 INTRODUCTION
In the preceding units, you have learned the concepts of the memory system for a computer
system. The memory system of a computer includes primary, secondary and auxiliary, and
high-speed memories. As discussed, the main memory of thecomputer system is used for
storing the instructions and data of the programs, which are getting executed. To execute the
program, the computer may need some data which is known as input.The program execution
results in the creation of processed data, which is known as output. In addition to the memory
system, another important component is the input and output system which is used to
receive/send data from/to the external environment. This unit introduces you to various
Input/Output (I/O) techniques and controllers, device drivers, structure ofI/O interface, and
asynchronous data transfer.This unit also explains the I/O processor which is exclusively used
for I/O operations.

7.1 OBJECTIVES
After going though this unit, you should be able to:
 define the structure of input/output (I/O) interface and I/O devices;
 explain the structure of controllers;
 explain different data transfermodes;
 explain various techniques used for Input/Output in a computer system;
 discuss the need of an input/output (I/O) processor;
 explain the role of external serial and parallel communication interfaces;
 explain the concepts of interrupt processing

7.2 INPUT/ OUTPUT (I/O) DEVICES

The input/output devices are used by a computer system to provide an interface with the
external environment i.e., humans and other devices, which are connected to a computer.
Themajor components of a typical microcomputer system are microprocessor/CPU, memory
43
 Basic Computer system and an I/O interface.These components are connected through buses. The primary
Organisation function of the system bus is to transfer control information, addresses, instructions, and data
between these components. Figure 7.1 depicts the block diagram of a typical microcomputer
system.

Figure 7.1: A Typical Microcomputer System’s Block Diagram

The microcomputer, as shown in Figure 7.1, has a single micro processing unit (MPU). It also
has RAM and ROM, which may be constructed by a number of RAM and ROM chips. The
diagram also shows two basic interfaces, viz. keyboard interface and display interface, which
are connected through the system bus. You may please note that other I/O interface may be
connected in a similar way. Please also note that the system bus has been shown in the diagram
as three distinct buses, viz. control bus, address bus, and data bus.
An Input/Output (I/O) subsystem includes all the input/output interfaces and connected
Input/output devices.The basic objective of an I/O subsystem is to provide an efficient
communication medium between the computer system and the external environment (humans
and other devices).An I/O interface is used to connect an external I/O device with the computer
system. The I/O interface interchanges control, status and data with the external device. The
I/O interfaces can also be used to transfer instruction/data/control within the computer units,
including processor registers and memory units.An I/O device attached to the computer is also
known as peripheralor external device. The external devices may be categorized on the basis
of their communication endpoints as:
 Human readable: These devices provide information in human readable form. Example-
display terminals,printers, etc.
 Machine-readable:These devices provide information in machine readable form.
Example-magnetic disks, CD-RW, etc.
 Communication:These devices provide information to communication devices such as
MODEM.

7.3 THE INPUT/OUTPUT (I/O) INTERFACE

AnI/O interface (also known as I/O Module) is used totransfer information between internal
memory and peripheral devices. Each peripheral device has its own set of characteristics. An
I/O interface helps in resolving the differences between the processing unit components and
peripherals. The following table lists major differences:

44
 The Input / Output
Table 7.1: Peripheral devices and processing unit components System

Sr.
Processing unit components Peripheral Devices Remarks
No.
Hence, they perform
Processor and memory are Peripheral devices are
1 operations in a different
electronic devices. electromagnetic devices.
manner
Data transfer rate of processor is Data transfer rate of peripheral
2 Thus, a synchronization
very fast. devices is slow.
Peripherals, in general, use mechanism is required.
3 Processor uses word format.
bytes/blocks format.
Each peripheral device may have a
4
Processor may communicate either different operating mode. Thus, an interface to handle
directly with different manners or Each peripheral device must be different operating modes is
indirectly using an interface in controlled in such a way that the required.
5
similar fashion. operation of one does not disturb the
operation peripheral device.

To address the issues mentioned in Table 7.1, ahardware component between the peripheral
devices and CPU is required to control and synchronize all input/output operations in the
computer systems. These hardware components, which are used to provide an interface
between the peripheral devices and the processor, are known asinterface units.An I/O
interface acts as a bridge between the processor and peripheral devices.
The I/O interface offers an interface which connects the internal components i.e.,processor and
main memory as well as external components i.e., peripheral or external devices. In addition to
data transfer between processor to I/O devices, it also establishes the coordination between
them. Moreover, the I/O interface also hascomponents like buffer system and error detection
mechanism to deal with the speed differences between processor and peripheral devices.

Figure 7.2: A Block Diagram of an I/OInterface connectingwith Processor and External Devices

Roles of I/O Interface

The major roles of I/O interfacesare:
1. Communication with the processor
To provide data transfer between processor and I/O interface, the control signals
(Read/Write/Status), address of memory locations and actual data are required to exchange.
The system bus works as a communication medium in order to facilitate the exchange of
information/data between the processor and I/O interface. In system bus, the addressbus is
used to send addresses; the control bus for control signals whereasthe data bus is employed for
actual data transfer between processor and I/O interface.
2. Synchronization of control and timing signals
The I/O interface shares system bus with memory in order to provide data transfer. The timing
and control signals are required in order to synchronize the flow of data from peripheral
devices to processor/memory and vice versa. For instance-An I/O interface may request for
control of data bus for data transfer from a peripheral device to the processor.
3. Communication with the I/O device
To complete an I/O operation, the exchange of data between I/O device and I/O interface is
necessary. AnI/O operation may require sendingstatus signals, commands, or data.
4. Provision for data buffering
Due to the speed mismatch between the I/O devices and processor, the facility for data storage
for a temporary period is required. The I/O interface stores information in registers temporarily
which is referred to as data buffering. An I/O operation occurs in short bursts and the data are
temporarily stored in a buffer area of I/O interfaceuntil the peripheral device/processoris ready
45
 Basic Computer to receive the data. Therefore, it is not required to hold the system bus for I/O operation due to
Organisation slower I/O devices.
5. Error detection mechanism
The I/O interface also provides an in-built mechanism for error detection to check the
communication errors along withmechanical errors. The errors are reported to the processor
using parity bits and other mechanisms for further actions. Some mechanical errors may occur
in devices such as mechanical and electrical failures, printer’s paper jam etc.
In Figure 7.3, the internal block diagram of I/O interface unit consisting of different signals for
processor as well as for I/O device is shown.

Figure 7.3: I/O Interface Unit’s Block Diagram

7.3.1 System Bus and I/O Interface Modules

The control bus, data bus and address bus form a single bus which is known as system bus and
it is used to establish the connection between the processor and I/O devices. Figure 7.4 depicts
the communication links between the processor and several peripheral devices.

Figure7.4: Communication links between Processor and Peripheral devices

The I/O bus is connected to all peripheral devices through I/O interfaces. In order to
communicate with an intended device, the processor sendsthe address of the device using
address bus. Every I/O interface consistsof an address decoder to continuously monitor the
content of address bus. When anI/O interface observes the address of its own peripheral
device, it activates the associated device and the bus; otherwise, the peripheral device
is disabled. A control signal (I/O command) is also provided simultaneously through the
control bus. The four types of I/O commands that are arising out of the processor are as
follows:
1. Control Command: This is the control signal code which is sent to the
corresponding peripheral device and informs it about the action it has to perform.
2. Status Command: The is the statussignal which is used to test status conditions of
the peripheral devices and interface. Some status commands are BUSY, DATA
AVAILABLE, ERROR or NOT IN BUFFER etc.

46
 3. Data Output Command: The signal/commandis utilized to activate the I/O interface The Input / Output
for data transfer from the processor to buffer of I/O interface. The data from the System
buffer is ultimately sent to the peripheral device. The data is sent from the CPU to
the buffer of interface after this command is provided.
4. Data Input Command: The processor sends this signalwhenever there is a need to
read data from data any peripheral device. After the issuance of this command, the
data from the intended peripheral device are extracted into the interface’s buffer and
this is followed by the data read operation by the processor.
7.3.2 I/O and Memory Bus
Aprocessor requires communicating with the I/O devices and memory system. The system
bus (I/O Bus & Memory Bus) is used to control the exchangeof data among the processor,
memory system and I/O devices. The I/O bus and memory bus; both busesconsist of data,
address and control lines. To establish communication with the memory and I/O devices, the
system bus can be used as follows:
i. One bus for each memory system and I/O.
ii. Shared data and addressbuses for both I/O devices and memory system but
exclusive control bus for both.
iii. Shared system bus for both memory system and I/O devices.
7.3.3 Isolated and Memory-Mapped I/O
In case ofisolated I/O, the data and address buses are shared between I/O and memory but
separate read/write control lines are used for I/O devices. Wheneverthe processor decodes
instruction for an I/O device, it places the address on the address line and activates I/O read
or write control line which causes data transfer between CPU and I/O device.
In other alternative, the computer employs the same set of read/write signals for I/O and
memory and does not differentiate between I/O and memory addresses. This configuration is
known as memory-mapped I/O.

7.4 DEVICE CONTROLLERS

The system bus is used to establish communication between the processor and all components
including I/O devices. Some components are directly connected to the processor through
system while some components are not directly connected to system bus.The intermediate
electronic device, known as device controller, is used to connectthe I/O device and the system
bus. The I/O device is connected at one end while it is connected with the system bus on
another end. Thus, a device controller works as an interface to provide the communication
medium between the system bus and I/O device.
Device Controller
It is not necessary that a device controller controls a single peripheral device. It can generally
control more than peripheral devices. The device controller is available as an electronic circuit
board, which can be directly plugged into the system bus. The device controller is also
connected through a cable with a peripheral device. The connectors at the rear panel of a
computer are in fact the end points of these cables. These connctors are called the ports and are
used to plugin the external peripheral device to a computer. Figure 7.5 depicts the connection
of computer system and I/O devices through device controllers.
In Figure 7.5, the following points are important to consider:
i. Each peripheral device is attachedtoa hardware interface known as I/O Port.
ii. A single-port device controller can controlonlyone peripheral device whereas the
multi-port device controller controls multiple peripheral devices.
iii. In case of direct memory access (DMA), the communication between I/O controller
and memory is established through system bus only, while the communication path
passes through the CPU for non-DMA communication.
The followings are themajor benefits for connecting computer system with I/O devices using
device controllers:
i. A single device controller may be used to connect multiple I/O devices with the
computer system simultaneously.
ii. The device controllers allow I/O devices to upgrade/change without any
update/change required in the current configuration of a computer system.
iii. The device controllers allow connecting the I/O devices ofdifferent
configurations/manufacturers with the computer system. It allows computer usersto
purchase I/O devices of different their configurations/manufacturers.

47
 Basic Computer
Organisation

Figure 7.5: Device Controller connecting I/O Devices and Computer System

7.4.1 Device Controller and I/O Interface

Due to the different input/output needs and design complexities, there exist various peripheral
deviceswith different structures. Thus,the common/standard structure of I/O interface does not
exist. Figure 7.6 shows a generalblock diagram of an I/O interface. The common
characteristics of the general structure of an I/O interface are as follows:
i. I/O logicis required in order to decode and execute thedata between the processor
and I/O interface. Hence, control lines between the I/O interface and processors are
required.
ii. Data lines between the system bus and I/O interface are necessary to facilitate the
actual data transfer.
iii. The data registers may behave like a buffer between processor and I/O interface.
iv. To deal with each I/O device with different configuration,the I/O interface must have
a separate logic specific.

Figure 7.6: Block Diagram of an I/O Interface

7.5 DEVICE DRIVERS

The device driver is a software interface to handle communication with a specific peripheral
device. The purpose of the device driver is to decodea logical request from the computer user
into a series of specific actions performed by theperipheral device. For instance, a computer
user may request to read a record from a disk. The device driver converts this logical request
into a series of discrete commandsi.e.,check the status of the intended disk in the drive,
locating the desired file, setting the position of R/E head, etc.

Device Drivers in Windows Systems

The device drivers are realized in the form of dynamic linked libraries (DLLs). The DLL
consists of shareable code and thus, a single copy of the DLL code is loaded into the
mainmemory. The hardware/software vendors can implement adevice driver for new
48
deviceswithout modifying or affecting the code of Windows operating system. Moreover, it The Input / Output
allows multiple optional drivers tobe configured for differentperipheral devices. System
For Windows based system, the device installation in the form ofPlug and Play is necessaryin
order to add new peripheral devices. The objective of Plug and Play is to convertthe device
connecting process from manual to automatic. In automatic device connecting process, the
device will be attached which is followed by installation of driver software. After this, the
installation process will be automatic and the settings will be changedaccording to the
configuration of the host computer system.

Device Drivers for UNIX Systems

The device drivers are generally linked to the object code of the core of operating system
which is known as kernel. To use a new device not included in operating system, the device
driver object code has been re-linked with UNIX kernel. The advantages of this technique are
simplicity and run-time efficiency while the main disadvantage is it requires regeneration of
the kernel in order to attach a new device. Each entry of the /dev directory of the UNIX
system is associated with a device driver which in turn is attached with the related device.
Table 7.2 consists of information of some device as follows:
Table 7.2: Device Name in UNIX System
Device name Description
/dev/console console of a system
/dev/lp line printer
/dev/tty01 user terminal 1
/dev/tty02 user terminal 2

Check Your Progress 1

1. What do you understand by I/O Interface?List major functions of I/O interface?
………………………………………………………………………………………………

………………………………………………………………………………………………

………………………………………………………………………………………………
2. What is the need of device controller? What are the major benefits?
………………………………………………………………………………………………

………………………………………………………………………………………………

………………………………………………………………………………………………

3. What is the need of a device driver? Give examples of device drivers.

…………………………………………………………………………………………….

.….………………………………………………………………………………………….

.……………………………………………………………………………………………..

7.6 ASYNCHRONOUS DATA TRANSFER

This section discusses the different data transfer modes.Thereexists two ways to transfer
data from sender to receiver in a digital computer system. It is necessary tosynchronize the
data transfer operationsusing clock pulses. When the internal registers of the two units i.e.
I/O interface and CPU share a common clock, the mode of data transfer between them is
known as synchronous data transfer. On the contrary, both of the units i.e., I/O interface and
CPU are designed to work independent manner and each unit uses its own private clock in
order to establish coordination. This mode of data transfer is knownas asynchronous data
transfer.
The asynchronous data transfer faces some problems. Since there exists no fixed time slot to
send or receive data. Therefore, there is no guarantee that whether the data is old or new.
This problem can be solved using the following two methods:
i. Strobe Control Method
ii. Handshaking Method

49
 Basic Computer 7.6.1 Strobe Control method
Organisation
In strobe control method a single control line is used each time for data transfer and this
control signal is referred to as Strobe. The strobe may be activated in the following two
different ways:
A. Source-initiated Strobe – Figure 7.7 depicts the block diagram and timing diagram for
source-initiated strobe method. In this method, the data transfer is performed as:
i. Initially, source unit putsthe data on data bus and the strobe signal is switched
ON.
ii. The destination unit reads data from the data bus.
iii. After reading data,the strobe gets OFF.

a. Block Diagram b. Timing Diagram

Figure 7.7: Source Initiated Strobe

B. Destination-initiated Strobe –Figure 7.8 depicts the block diagram and timing diagram
for destination-initiated strobe method. The steps for data transfer are as follows:
i. First, the destination unit switches ON the strobe signal.
ii. After observingstrobe ON, the source unitputs data on the data bus.
iii. The destination unit reads the data from the data bus and the strobe signal gets
OFF.

a. Block Diagram b. Timing Diagram

Figure 7.8: Destination Initiated Strobe

Disadvantages of Strobe Method:

The disadvantages of strobe methods are as follows:
 In source-initiatedstrobe method, it is not possible toconfirm the status of data at
destination unit i.e., whether the data received is valid or not.
 In destination-initiatedstrobe method,itis not possible toconfirm the status of data at
the data bus i.e., whether the data extracted from the data bus is valid or not.

7.6.2 Handshaking method

In handshaking method of asynchronous data transfer, the problemsof strobe control method
can be handled. The handshaking method can be realized in the following two different
ways:
A. Source-Initiated Handshaking – It consists of the following signals:
Data Valid: When activates, itspecifies that data on the data bus is validotherwise invalid.
Data Accepted: When activates, it specifies that data is acceptedotherwise not accepted.
The steps of data transfer in Source Initiated Handshaking method are as follows:
i. First, source unitcopiesdata on the data bus and enablesData Valid signal.
ii. The destination unitreceives data from the data bus and enablesData Accepted
signal.
iii. After this, Data Validsignalisdisabled whichimplies that data on data bus is
invalid now.
iv. Finally, Data Accepted signal is disabled which indicates that the process of data
transferhas been completed.
Now,it can be ensured that destination unit has read the valid data from the data bus
usingData Accepted signal.Figure 7.9 depicts the blockdiagram and timing diagram of
thesource-initiated handshaking method.

50
 The Input / Output
System

a. Block Diagram

b. Timing Diagram
Figure 7.9: Source Initiated Handshaking

B. Destination-Initiated Handshaking – It employs the following signals:

Request for Data:When activated, it requests for putting data on the data bus.
Data Valid: When activated, itspecifies data is valid on the data bus otherwise invalid
data.
The steps of data transfer in Source Initiated Handshaking method are as follows:
i. When destination unit is ready to receive data, the appropriate signal
i.e.,Request for Data gets activated.
ii. In response, the sourceunit places data on the data bus as well asit also
enablesData valid signal.
iii. Next, the destination unit accepts data from the data bus. After receiving data, it
disablesRequest for Data signal.
iv. Lastly, the Data valid signal is disabled implies that the data bus consists of
invalid data now.
Using data valid signal in Destination Initiated Handshaking, it is possible to ensure that
source has put the data on the data bus.Figure 7.10 shows the block diagram and timing
signal in destination-initiated handshaking. It consists of Request for Dataas well as Data
valid signals.

a. Block Diagram

b. Timing Diagram
Figure 7.10: Destination Initiated Handshaking

7.7 INPUT/OUTPUT (I/O) TECHNIQUES

This section explains the methods to use I/O interface to support data transfer (input/output)
from peripheral devices.The data transfer (I/O operation) between the computer system and
peripheral devices may be performed using three techniques given as follows:
 Programmed I/O
 Interrupt-driven I/O
 Direct memory access (DMA)
Table 7.3presents important characteristics of the above three techniques.

51
 Basic Computer
Organisation Table 7.3: Three I/O Techniques

I/O Technique Data Transfer Processor Interrupt

Path through Intervention

Programmed I/O Processor Continuous Not-Required

Interrupt-driven I/O Processor Discontinuous Required
Direct memory access Direct to At the beginning Required
(DMA) Memory and end

7.7.1 Programmed I/O

In this technique, the processor is completely responsible for managing all I/O operations. The
program which requests for I/O operation directly and continuously controls the I/O operation
through the processor.The processor runsprogram that starts, continuously monitors and
endsan I/O operation.The I/O operation may involve the following data transfer operations:
a. Data transfer from processor registers to I/O device.
b. Data transfer from I/O device to main memory through processor registers.
The major steps in programmed I/O are as follows:
i. The processor issues READ/WRITE command.
ii. The processor requests for I/O operation to I/O interface.
iii. I/O interface sets status bits.
iv. The processor continuously checks the status bits.
v. The processor waits for I/O device.
vi. When I/O device is ready, I/O operation (Read/Write data) is performed.
Figure 7.11 depicts the diagram of programmed I/O technique. When the CPU issues a
command for an Input or an output to the I/O interface, it must wait until the I/O operation is
completed. This process is known as polling.
Disadvantage: With the programmed I/O method, the processor continuously checks the
status of the I/O device whether it is ready or not. The processor has to wait for slower I/O
operations to complete. Therefore, this technique is wasteful of processor’s time.

Figure 7.11: Programmed I/O

I/O Commands
Wheneverthe processor addresses an I/O interface, it sends an address and I/O command.
There are four I/O commands which a processor may send to I/O interface for I/O
operation.The I/O commands are given as follows:

52
  Control:Control commands are used to activate the device and also specify what The Input / Output
System
operation is to perform. For example- aUSE command to make a specific device as
current device for read/write operation.
 Test: The Test I/O command is used to check the status of a device. For instance-
Whether the device is in error condition, ready state, or notreadystate.
 Read: This command is used to receiveone item of input data from the I/O device
which is in communication.
 Write:This command is used to sendone item of output data to the respective output
device.
7.7.2 Interrupt-driven I/O
For an I/O operation inprogrammed I/O, the processor continuously waits for the operation to
be completed and the data transfer occurs when the device is ready. This process is known as
polling which leads to slow performance of the processor. Interrupt-driven I/O can reduce the
polling time efficiently.In interrupt-driven I/O, the processor issues a read/write command and
it starts the execution of some other program/instructions. Whenever the desired device is
ready or has completed the assigned I/O task, an interrupt signal is sent to processor for further
actions. Figure 7.12 depicts the procedure of interrupt-driven I/O technique. The complete list
of steps in interrupt-driven I/O is as follows:
i. The processor issues read /write command
ii. The processor executes some other program/instructions
iii. The I/O interface reads data from the desiredI/O device
iv. I/O interface interrupts the processor
v. The processor checksthe interrupt after completingeach instruction cycle
vi. The processor saves the context of the program in execution
vii. The processor requests for the desired data
viii. The I/O interface transfers data
ix. The processor resumes the previous program it had been executing before the
interrupt.
Advantage: This technique reduces the overall waiting time of the processor.

Figure 7.12: Interrupt Driven I/O

7.7.3 Interrupt Handling

An interrupt is an event which may occur to receive some service by a device or due to some
error. After an interrupt occurs, it causes multiple tasks in the software as well as in the
hardware.
53
 Basic Computer Figure 7.13 represents the series of hardware tasks which occurred in order to I/O operation
Organisation using an I/O device. The complete lists of tasks required for interrupt processing are as
follows:
1. An I/O device sends an interrupt signal to processor.
2. The processor completes the execution of currently running instruction and next, it checks
and takes action accordingly.
3. An acknowledgement signal is also sent by the processor to the corresponding I/O device.
4. The processor saves the context of the program that is being executed currently. It saves
the following registers:
(a) The status of the processor: program status word (PSW) register
(b) The next instruction to be executed: program counter (PC) register.
5. In addition to thecontents of PC & PSW for the interrupted program, it is required to store
the contents of the registers of processor on the stack. Figure 7.14 depicts an example of
interrupt occurrence. According to theFigure 7.14, a user running program is interrupted
after the execution of the instruction at location N. To handle the interrupt, the processor
saves the contents of all general-purpose registers, PSW, PC along with the address of the
next instruction at location N+1.
6. The processor loads the PC with the address of first location of the interrupt and then, the
processor starts executing instruction from the interrupt-handler program. It means that the
interrupt handler handles the interrupt.
7. When the processing of the interruptis completed. The context of the previous program is
restored i.e.contents stored at stack are restored in the processor registers, which is shown
in Figure 7.15.
8. Finally, the values of PC and PSW are retrieved from the stack and restored on the
corresponding registers. It leadsto execution of the instruction whichwas interrupted from
the previously interrupted program.

Figure 7.13: The sequence of steps in Interrupt-Processing

In simplewords, the interrupt handling consists of the followings:

i. Interruptthe current program
ii. Saves the context of the interrupted program
iii. Transfer control to interrupt servicing program
iv. Execute the interrupt servicing program
v. Restore the context of interrupted program
vi. Resume interrupted program from the point where it was interrupting.
Design Issues
To realize the interrupt-driven I/O, there exist two design issues given as follows:
1) How does the processor identify the I/O device issuing the interrupt?
2) How does the processor handlemultiple interrupts occurred simultaneously?

54
 The Input / Output
System

Figure 7.14: Interrupt occur for instruction at memory location N

Figure 7.15: Return after handling an Interrupt

The following four general techniques can be used to solve the above design issues:
i. Multiple Interrupt Lines: Multiple interrupt lines can be used to handle multiple
interrupts. In this technique, the priorities are assigned to various interrupts.
Whenever an interrupt occurs, the highest priority interruptwill be handled first
among all interrupts. However, the practical realization of this technique is difficult
because computer system provides only a few lines for the interrupt.
ii. Software Poll: The processor jumps to an interrupt service routine after an interrupt
has occurred. The processor polls at I/O interface by observing the status register in
order to identify the I/O interface which caused the interrupt. The software poll
technique is time consuming due to polling process.
iii. Daisy Chain or Hardware Poll: In this technique, the interrupt request line is shared
by all I/O interfaces. Whenever an interrupt occurs, the processor sends an
55
 Basic Computer acknowledgement of interrupt. This acknowledgement goes to all the I/O devices
Organisation through I/O interface. When it reaches to the I/O device which sends interrupt, the I/O
device sends a response by specifying an address or unique identifier through the data
bus. This unique identifier helps in deciding the appropriate interrupt servicing
program. The hardware poll consists of an in-built priority mechanism and this
priority is based on the sequence of devices on interrupt acknowledge line.
iv. Bus Arbitration: The bus arbitration technique allows only one I/O interface to
control the bus and this I/O interface is known as bus master. It means only one
interrupt request can be fulfilled at the same time. After acknowledgement of
interrupt by processor, the I/O interface sends the interrupt vector to processor
through data lines. The interrupt is handled according to the number in interrupt
vector.
7.7.4 Direct Memory Access (DMA)
The programmed I/O as well as interrupt-driven I/O techniques require the processor’s
interventions for data transfer to/from the main memory. Since processor may involve in the
execution of multiple programs due to multiprogramming, which restricts the processor time
for testing the I/O device and servicing the I/O request by transferring I/O data over the system
bus. Is it possible to store/retrieve data to/from main memory without involving the processor
in the data transfer? Yes! There exists an alternative approach which is referredto as direct
memory access (DMA). In DMA, the main memory andI/O interface exchange data directly
without the active involvement of processor. Figure 7.16 depicts the block diagram of direct
memory access (DMA) technique. Now, an obvious question arises: What is the use of DMA
interface? The DMA interface is mainly used to transfer a large quantity of data which
isexchanged between I/O device andmainmemory.
Figure 7.16 depicts the block diagram of DMA technique. The steps of the DMA technique
aregiven as follows:
i. Processor issues read/write command to DMA module for transferring the block of
data
ii. The processor sends the following information to DMA interface-
a. To perform read/write operation, the Read /Write signal is sent using control
lines
b. I/O Device address is communicated through a data bus
c. Beginning address of memory block using data bus
d. “The number of words to be transferred” is communicated through data bus. This
information is stored in a count register.
iii. The processor executes some other program.
iv. Now, DMA controller performs the data transfer
v. When DMA controller finishes the data transfer, it sends an interrupt signal to
processor

Figure 7.16: DMA Technique

Figure 7.17 shows the block diagram of DMA module along with its different signal lines.
The DMA module handles data transfers to send the entire block of data and one word at a
time is transferred directly to or from memory without going through the registers of
processor.After transferring the entire block, an interrupt signal is sent to processor by DMA
module.Therefore, the processor involvement is limited only at the start and end of the I/O
operation.
In DMA, the processor intervention is minimized but it must use the path through system bus.
Thus, DMA interface requests for system bus to transfer one data word at a time and the
control of the system bus is returned to the processor after transferring on word of data. This
process is known as cycle stealing. The CPU cycle stealing causes the delay to the operation
56
of processor for one memory cycle. In DMA technique, the active involvement of processor The Input / Output
can be restricted at the beginning and at the completion of the I/O operation. System
Figure 7.18 depicts the five cycles of typical instruction execution. In Figure 7.18, three points
are marked where a processor can respond to DMA request, and; a point is also marked where
the processor can respond tointerrupt request. The point at which the interrupt request can be
acknowledged is called the interrupt cycle.

Figure 7.17: DMA’s Block Diagram

Figure 7.18: Breakpoints for DMA and Interrupt in an Instruction Cycle

There exist different configurations to realize the DMA mechanism. Figure 7.19(a) shows one
of the several configurations. In this configuration, the system bus is shared by all interfaces.
The DMA works as a supportive component and may employ programmed I/O fordata transfer
between memory and I/O interface using DMA interface. The advantage of this configuration
and programmed I/O is that DMA does not require extra system bus cycles to transfer
information from DMA to/from I/O interface as well as from main memory to/from DMA.

(a) Single Shared System Bus with detached DMA

57
 Basic Computer
Organisation

(b) Single Shared SystemBus with integrated DMA-I/O

(c) I/O bus

Figure 7.19: Three Different DMA Configurations

Figure 7.19(b) depicts one more DMA configuration which has some advantages over the first
configuration shown in Figure 7.19(a). In this configuration, adirect path is provided between
the DMA interface and I/O interface and this path is different than the system bus.
Furthermore, DMA logic may actas aconstituent of I/O interface and single or multiple I/O
interfaces may be controlled by it. One more flexible configuration is shown in Figure 7.19(c)
in which the DMA interface is connected to I/O bus. This configuration isextendable in an easy
manner. The additional benefit in both configurations is that the data transfer can be performed
from DMA interface to I/O interface without the involvement of the system bus.
Check Your Progress 2
1. What do you understand by Programmed I/O technique?
………………………………………………………………………………………………
………………………………………………………………………………………………
…………………………………………………………………………………………….
2. Explain interrupt?What processing is performed on the occurrence of an interrupt?
………………………………………………………………………………………………
………………………………………………………………………………………………
……………………………………………………………………………………………..
3. Why is DMA needed? What are its advantage and disadvantages?
………………………………………………………………………………………………
………………………………………………………………………………………………
…………………………………………………………………………………………….

7.8 INPUT-OUTPUT PROCESSOR (IOP)

The evolution of I/O techniques passes through many development stages and this evolution
can be helpful to understand the idea of I/O processors. Various stages of
evolutionaresummarizedas follows:
1. Direct Control: The processor directly controls I/O device.
2. Control using I/O controllers without interrupts: In this configuration, processor and I/O
interfaces are different with each other and programmed I/O without interrupts was
employed by I/O interface for I/O data transfer.

58
3. Control using I/O controllers with interrupts: In this configuration, the processor need not The Input / Output
to wait for an I/O operation to be completed which leads to improved efficiency of the System
processor.
4. Control transferred to DMA: In this configuration, the involvement of the processor is
restricted at the beginning and on completion of DMA operation. The I/O interface and
DMA module control the data transfer directly without the involvement of the processor.
5. Control transferred to I/O processor: On the request of main processor, the I/O processor
takes control of I/O operation and performs I/O operation with the intervention of the
main processor. This approach allows controllingvarious I/O devices with minimum
involvement of processor.
Through various evolution stages, it is evident that the responsibility of I/O tasks has been
shifted from CPU to I/O-processor and it leads to improvedperformance of the processor.
It is also evident from the recent developments that a major shift occurs due to the introduction
of I/O interface which is capable to executethe I/O instructions. Hence, the ‘I/O interface’ is
often called anI/O processor or I/O channel.

Input Output Processor (IOP)

An IOP is a processor that handles only the I/O processing.The block diagram of a computer
system with input output processor is shown in Figure 7.20. The computer system with I/O
processor consists of three major components: (a) a memory unit (ii) the processor and (iii) the
IOP. The IOP controls and manages the input-output tasks. On the command of CPU, the IOP
can fetch, decode and execute I/O instructions which are loaded to perform the I/O operations.

Figure 7.20: Block Diagram of a Computer System with I/O Processor

7.8.1 I/O Processor’s Characteristics

In simple words, anI/O processor (or I/O channel)is theextension of the concept of DMA
technique. An I/O channel holds complete control of the I/O operation and is also capable to
execute I/O instructions. The CPU initiates the I/O operations andhandovers the execution of
I/O commands to I/O processor. In response, the I/O processor executes the I/O instructions
stored into the main memory.
The I/O channels can be divided into two categories:
i. Selector I/O channels
ii. Multiplexer I/O channels.

(a) Selector I/O Channel

59
 Basic Computer
Organisation

(b) Multiplexer I/O Channel

Figure 7.21: Structures of I/O Channels
A. Selector I/O channel: The selector I/O channel isa dedicated channel to perform data
transfer exclusively with a high speed I/O device connected to it. Each I/O controller
may controla single or multiple I/O devices. Thus, I/O channelsreduce the burden
ofthe CPU by controlling the I/O controllers. The selector I/O channel is shown in
Figure 7.21(a).
B. Multiplexer I/O channel: Figure 7.21(b) depicts themultiplexer I/O channel. This
I/O channel is capable to handle I/O operations with more than oneI/O device
altogether. For example-if, there are three slow devices interested to send the
following bytes given as:
Ist I/O device: A1 A2 A3 A4 A5 ……
IIndI/O device: B1 B2 B3 B4 B5……
IIIrd I/O device: C1 C2 C3 C4 C5……

Then, the byte multiplexer I/O channel may send the bytes as follows:
C1 B1 A1 C2 B2 A2 C3 B3 A3……

For high-speed devices, block multiplexer I/O channels can be used which transfers data in
form of blocks.

7.9 EXTERNAL COMMUNICATION INTERFACES

The external communication interface is used to provide an interface between the peripheral
devices and I/O interface. There exist two main categories of external communication
interfaces:
(a) Serial Communication Interface
(b) Parallel Communication Interface
The serial communication interfaceemploys only one line for transferring one bit of data at a
time. Serial interfaces are used for terminalsandprinters.
Theparallel communication interfacecan transfer several bits at the same time. The parallel
interfacesareusuallyutilized for I/O deviceshigh-speed.For instance, disks and tapes use
parallel interfaces. The communication that takes place across the communicationinterface
includes the exchange of data and control information.
In both serial and parallel communication, the I/O interface must engage in communication
with the peripheral. The communication steps for the read/write operation are given as follows:
 The I/O interface sends a control signal to I/O device to requestpermission to receive or
send data.
 TheI/O device accepts the Read/Write request and sends an acknowledgement.
 The data transfer operation either from I/O device to I/O interface (Read operation) or
from I/O interface to I/O device (Write operation) is performed.
 The I/O device sends an acknowledgement signal after the data transfer operation.
Point-to-Point andMultipoint Configuration
There are two types of connection between the external I/O devices and I/O interface in a
computer system: (i) point-to-point (ii) multipoint. In a point-to-point interface, a dedicated
line is provided between the external device and I/O interface in the computer system. The

60
examples of use of point-to-point interfaces point are: keyboard, printer and external modems. The Input / Output
Some common examples of point-to-point interfaces are EAI-232 and RS-232C. System
On the other hand, the multipoint external interfacesare used to support external multimedia
devices (such as audio, video, CD-ROM) and mass storage devices (such as tape drives and
disk). Some common examples of multipoint external interfaces are Infini Band and
FireWire.

Check Your Progress 3

1. List majorcharacteristics of I/O processor.
………………………………………………………………………………………………

………………………………………………………………………………………………

………………………………………………………………………………………………

2. Differentiate selector and multiplexer I/O channels.

………………………………………………………………………………………………

………………………………………………………………………………………………

………………………………………………………………………………………………

3. Compare serial and parallel external interfaces.

………………………………………………………………………………………………

………………………………………………………………………………………………

………………………………………………………………………………………………

7.10 SUMMARY
This unit explains exclusively the I/Oorganisation of a computer system. This unit presents the
description of I/O devices, the concept of I/O interface, the description and structure of device
controllers, and asynchronous data transfer modes. It also discusses three I/O techniques
i.e.,programmed I/O, interrupt-driven I/O, and direct memory access (DMA). The threeI/O
techniques involve processor at different levels and help processor to behave differently. The
interrupt processing is also discussed in detail.The evolution of I/O processor is also discussed
along with the brief explanation of the input/output processor as well as the external
communication interfaces. The I/O processors are the most recent I/O interfaces that are
capable to execute the I/O instructions without the involvement of the processor.

7.11 SOLUTIONS /ANSWERS

Check Your Progress 1

1. An I/O interface acts as a bridge between the I/O devices and processor. It provides a
communication interface to connect the computer with the external environment. The I/O
interfaces are used to send/receive data from the external environment using external
device or peripheral. The I/O interface offers the following major functions:
 Synchronization of control and Timing signals
 Establish communication between peripheral devices and processor
 Data buffering to due to the speed mismatch between memory and processor
 A mechanism for error detection
2. Device controllers work as a connecting mediumto connect the peripheral devices to a
computer system rather than connecting them directly to the system bus. On device
controller, the I/O device is connected at one end while it is connected with the system bus
on another end. Thus, a device controller works as an interface between the system bus
and the I/O device. The major benefits for connecting I/O devices to a computer system
using device controllers are as follows:
61
 Basic Computer  A single device controller can be used to connect multiple I/O devices with the
Organisation computer system simultaneously.
 The device controllers allow I/O devices to upgrade/change without any
update/change required in the current configuration of computer system.
 The device controllers allow connecting the I/O devices with different
configurations/manufacturers with the computer system. This feature offers more
flexibility to the computer users in order to buy I/O devices of different
configurations/manufacturers
3. A device driver is a software module which manages the communication with a specific
I/O device. It provides a software interface to hardware devices.Some examples of
different device drivers are printer driver, sound card driver, graphics driver, network card
driver, USB driver etc.

Check Your Progress 2

1. Programmed I/O technique is used to perform the I/O operation and it does not need an
interrupt for I/O operation.The main purpose of the programmed I/O is to perform data
transfer between processor and external environment. This technique is very inefficient,
especially when multiprogramming environment is used, as Programmed I/O requires
continuous involvement of the processor for the I/O to complete. This wasted time could
have been used for exection of other programs.
2. An interrupt is an event which may occur to receive some service by a device or due to
some error. After an interrupt occurs, it causes multiple tasks in the software as well in
the hardware. The abstract steps for the interrupt handling are as follows:
 Interrupt the current program
 Saves the context of the interrupted program
 Transfer control to interrupt servicing program
 Execute the interrupt servicing program
 Restore the context of the interrupted program
 Resume interrupted program from the point of interruption.
3. DMA is needed to enable a device to transfer data without exposing the CPU which
results in much less CPU overhead.The advantages of DMA are:
 DMA allows a peripheral device to read and write to/from memory without
passing through the CPU.
 DMA allows for faster processing as the processor can be working on something
else while the peripheral can perform memory related work.
The disadvantages of DMA are:
 requires a DMA controller to carry out the operation, which increases the cost of
the system
 problem of cache coherence

Check Your Progress 3

1. Some of the characteristics of I/O channels are:
 An I/O processor (I/O channel)is the extension of the DMA concept.
 An I/O channel holds complete control of the I/O operation and is also capable to
execute I/O instructions.
 The CPU initiates the I/O operations and handovers the execution I/O commands
to I/O channel. In response, the I/O channel executes the I/O instructions stored
into the main memory.
2. The difference between Selector Channel and Multiplexer Channel is that the Selector
channel communicates the data with only one dedicated high-speed device at one time
while the multiplexer channel is capable to handle I/O with multiple devices at the same
time.
3. The difference between serial and parallel interfaces is given below:
 The serial communication interface employs only one line to transfer one bit of
data at a time. The parallel communication interface can transfer several bits at
the same timeis usually utilized for I/O devices high-speed.
 Serial interfaces are used for terminals and printers while high-speed peripherals
such as disks and tapes use parallel interfaces.

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 I/O Technology
UNIT 8 I/O TECHNOLOGY
Structure

8.0 Introduction
8.1 Objectives
8.2 Mouse
8.2.1 Classifications of Mice
8.3 Keyboard
8.3.1 Features of Keyboard
8.4 Monitors
8.4.1 Cathode Ray Tube
8.4.2 Liquid Crystal Display
8.4.3 Light-Emitting diode
8.5 Video Cards
8.5.1 Resolution
8.5.2 Color Depth
8.5.3 Video Memory
8.5.4 Refresh Rates
8.5.5 Graphic Accelerators
8.5.6 Video Card Interfaces
8.6 Sound Cards
8.7 Digital Camera
8.7.1 Webcam
8.8 Voice Based Input Devices
8.8.1 Siri
8.8.2 Alexa
8.9 Printers
8.9.1 Impact Printers
8.9.2 Non-impact Printers
8.10 Scanners
8.10.1 Resolution
8.11 Modems
8.12 Summary
8.13 Solutions /Answers
References

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 I/O Technology
8.0 INTRODUCTION
In the previous unit, you have studied the concept of input/output interfaces and I/O
techniques. The previous unit discussed three I/O techniques i.e., programmed I/O, Interrupt-
driven I/O and DMA were discussed along with the evolution of I/O processor. A computer
supports a number of I/O devices in order to perform data transfer with external environment.
This unit provides a brief introduction to the various I/O devices such as mouse, keyboard,
monitor, printer, scanner, video & sound cards etc. It also discusses the modern voice-based
input devices. The unit does not attempt to provide all the details of these devices, but attempts
to introduce you the characteristics, basic functions and use of the devices in the context of the
processor.

8.1 OBJECTIVES
After study of this unit, the students ought to be able to:
 Explain the features of mouse and its classifications;
 List the basic characteristics, functioning and interfacing requirements of keyboard;
 Explain different types of monitors
 Explain video Cards, sound cards, and digital camera
 Explain different types of printers;
 Explain the basic characteristics of Modems and scanners;
 Explain the concept of voice-based input

8.2 MOUSE
Douglas C. Engelbart at Stanford Research Institute (now SRI International) proposed the
basic concept of mouse in order to use it with computer system. Xerox Corporation is first
organization which developed the first Mouse. It is hand-held hardware input pointing device,
which gives user a cursor (pointing mark) on monitor screen and this cursor is used to send the
input to computer system. The purpose of mouse is to detect two-dimensional movement
relative to surface. Typically, mouse is available with two or three buttons but a single button
is sufficient to control the movement of cursor. There exist different types of mice namely
Wired, Wireless, Bluetooth, Trackball, Optical, Laser, Magic, USB etc.
The unit of mouse resolution is Counts Per Inch (CPI) which represents the number of signals
per inch of physical travel of mouse. The value of CPI may range from 400 to 1600. The
mouse also sends CPI data to computer with some frequency which is known as polling rate.
The polling rate may range from 60 Hz to 1000 Hz. The large value of CPI will result in faster
movement of cursor which requires sending much data to computer demanding high polling
rate. Therefore, it will be difficult to control the accuracy for large value of CPI.
8.2.1 Classifications of Mice
The classifications of mice are based on connectors, number of buttons and position sensing
technologies. Two classifications are discussed-
1. Connectors: This category deals with categorization of computer mice based on
ports/physical channels which are used to connect the mouse and computers.
a) Bus Mouse-Bus was used to connect the first mouse with PC. Thus, it has been called
as the bus mouse. It was used with IBM-compatible personal computers in its early
days. A specialized bus interface was used to connect them with PC which was
implemented via an ISA add-in card.
b) Serial Mouse-In Serial mouse, serial port was used for connection. It is basically an
interface present physically on computer for communication. Bit by bit information
goes in and taken out of the computer through this port. It is a male port of D-type
having 9 pin (DB9M) which is found at the back of the motherboard. However, this
category of mice is no longer in use.
c) PS/2 Mouse-The green colored PS/2 port is used to connect the mouse. Introduced in
1987, PS/2 uses 6-pin mini-din connector. It is the successor of serial connectors.
PS/2 ports were first used in the PS/2 systems and they are still being used in modern
designs. Green color of PS/2 port is for mouse and purple colored is for keyboard.
d) USB Mouse-USB mouse are same in terms of shape and appearance but the
difference lies in terms of connector. They are connected to a USB port. USB stands
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 for universal serial bus has superseded the PS/2 ports, though some of the computers I/O Technology
still have the PS/2 ports. This standard defines the cables, connectors and
communication protocols for connection and communication between computers and
attached peripheral devices. The objective of this standard was to standardize
computer devices connection.
e) Wireless Mouse-These are the modern mouse that does not require any cable for
connection. Eliminating the clutter of cables, it provides a neat type of mouse to use.
Some of its key features are- comfortable ergonomic design, improved battery life,
Plug-and-Play, multi-function and wide compatibility

2. Sensing Technology: There are two types of mice based on sensing technologies i.e.,
mechanical mouse and optical mouse.
a) Mechanical mouse has a rubber or metal ball in middle, which is used to control the
movement of cursor. The sensors inside the ball detect the rotation of ball. When the
ball rolls with the movement of mouse, it causes sensors to detect the rotation of ball
along the two axes which consequently send signals to monitor screen. Figure 8.1(a)
depicts the mechanical mouse.
b) Optical mice use light emitting diodes (LEDs), optical sensors and digital image
processing. The optical mouse detects by sensing the changes in the reflected light.
The change in reflected light is measured by analyzing the images and the cursor
moves on screen accordingly. Figure 8.1(b) shows the optical mouse.

(a) (b)

Figure-8.1: Difference between (a) Mechanical Mouse and (b) Optical Mouse

8.3 KEYBOARD
A keyboard is an input device, which is used since the inception of the computer systems. The
keyboard allows manual input of alphabets, numbers, special characters, which are available as
keys on a board. Figure 8.2 depicts a keyboard. In general, users use a keyboard to transfer a
meaningful sequence of characters or numbers to a computer. Thus, a keyboard can be used to
send input data into a computer from the external world.

Figure-8.2: Overview of how Keyboard transfers data to the computer

8.3.1 Features of Keyboard

Some of the basic characteristics of keyboard are given as follows.
 Keyboard Layout
The layout defines the arrangement of the keys on the keyboard. This arrangement is mostly
influenced by the typewriter. The keyboard layout is now available for many different
languages of the world. A good layout is the one, which allows faster data input. Thus, in most
cases, computer keyboard layout is identical to typewriter key layout, which was designed for
enhancing the speed of data input. The standard keyboard layout for English is called
QWERTY layout. QWERTY layout stands for the six top alphabets in the keyboard. The
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QWERY arrangement was created by Sholes, who invented typewriter. However, a computer I/O Technology
in addition to alphabets is required to input numbers, special characters, and several shortcut
commands. Therefore, keyboard has a very detailed arrangement of keys.
One popular keyboard designed by IBM for the personal computer had 101 keys. This
keyboard's key layout is shown in Figure 8.3. This keyboard consists of key sets for alphabets
in the middle, numeric key pad in the right for easy entry of numbers, function keys at the top
name F1, F2, which are used as shortcut to various functions in different software, and a set of
cursor keys to move the cursor on the screen. Later, a set of windows function keys were
added to this design.
Another keyboard layout was designed by A Dvorak and William Dealey in 1936. Their layout
was primality designed for people who find typing with all fingers difficult and would like to
type using only two fingers. It was expected that typing would be faster by using Dvorak-
Dealey keyboard, as you can use both the hands while typing. You can find more details on
this keyboard in the further readings. With the availability of newer mobile smart devices,
there are many possibilities of designing new keyboards for specific areas, including better
designed layout for regional scripts.
For the languages of our nation, Indic keyboard layout is a standard layout. This layout
supports 12 Indian scripts.

Figure-8.3: IBM 101-key Keyboard layout

 Keyboard Touch
In addition to layout, the other important characteristic of a keyboard is the keyboard touch.
The keys should be sensitive enough to capture the data being entered by the user. A good
keyboard must be able to send data with speed. These days, in addition, to physical keyboards,
touch screen keyboards are also available. Most of these keyboards provide features of
predictive text and autocorrect, which facilitate data entry by the user.
 Scan Codes
When a key is pressed on a keyboard, it transfers the scan code relating to those keys to the
processor. Scan code of every key is unique. The scan codes are used to communicate the
desired data or action to the processor. A keyboard of processor is connected through interrupt
driven I/O mechanism. Therefore, when a key or several keys are pressed together on the
keyboard, it interrupts the processor, provided processor has enabled interrupts. The processor
receives the scan code/codes and identifies the key or keys that were pressed using the scan
code table stored in the ROM BIOS. In addition, the status byte that is associated with the
keyboard informs the processor about the status of keys that are used a toggles, like, Caps lock,
Num Lock, etc. But how does a keyboard identified that more than one keys are pressed
together, such as CTRL & ALT & DEL. Interestingly, a keyboard sends two scan codes to the
processor - one when key is pressed and second key is released, which were called Make and
Break scan codes respectively. Thus, by knowing the timing of these make and break scan
codes, processor determines, which keys are pressed together. A detailed discussion on scan
codes is beyond the scope of this Unit.

8.4 MONITORS
A monitor is an output display device connected to processor and it displays the vision into the
brain of the processor. It allows a user to graphically interact with the processor which is
helpful to send output as well as to receive input to/from the user. Technically speaking, it is
display device which provides a graphical vision by converting the digital/analog signals into
the visual form.

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The monitor looks like a television set but both the devices are different with each other. The I/O Technology
monitors have greater sharpness, lower input lag, higher refresh rates, color purity, and operate
at higher frequencies in comparison to TV sets. The TV set consists of tuner or demodulator
circuit to convert the signals
Whenever users are interested to buy a monitor, they search for the better configurations in
minimum possible budget. The configuration of monitors consists of display size, resolution,
supported frequencies, the size of the picture tube and the type of connector used to connect to
the computer. Monitors are manufactured by many manufacturers like LG, Samsung, Acer,
Dell, HP, Lenovo, Sony, Asus, BenQ, etc. The monitors are available with different sizes i.e.,
14’’, 15’’, 17”, 19’’, 21.9’’, 24’’ or even higher. The monitors are also available with different
screen form factor i.e., flat and curved screens. The monitors can be categorized into three
categories based on the design technology. These categories are discussed in next sub-sections.

8.4.1 Cathode Ray Tubes

The cathode ray tubes monitors and television sets are based on the technology of Cathode ray
tube (CRT). A CRT is a partly empty glass tube which consists of inert gas at low pressure. A
negatively charged electrode which is known as Cathode/Electron gun is used to shoot beams
of electrons at high speed towards a positively charged electrode (anode). The high-speed
electrons impinge on the small phosphor coated screen. The screen consists of dots with three
primary colors i.e., Red, Green and Blue. Indeed, there exists either one electron gun for the
three colors (Red, Green and Blue) or one different electron gun for each color. Figure-8.4
depicts the cathode ray tube (CRT). The quality of image on CRT screen is influenced by
following four factors:
1. Phosphor coating: The monitor screen is coated with phosphor (fluorescent material)
which emits light when bombarded by electron gun. The phosphor coating is provided in
inner surface of cathode ray tube. The coating affects the color and the persistence. The
term persistence in the context of monitor is defined as the time for which the effect of a
single hit on a dot on the monitor surface lasts.
2. Shadow Mask/Aperture Grill: It is the manufacturing technology for CRT monitors to
produce clear and focused color images. It determines the resolution of the screen in color
monitors. In shadow mask CRT, each pixel position consists of 3 phosphor color dots one
for each red, green and blue. The Triad and inline arrangements are used for the alignment
of color dots to produce good quality images.
Another technology for same purpose is the aperture grille
3. Electron Gun: The electron gun must be efficient in its working. The high-quality
electron gun affects the quality/sharpness of the image.
4. The screen glare and lighting of the monitor are also major factors to influence the quality
of the image.

Focusing System Electron Beam

Y deflects
Base

Phosphor coated screen

X deflects
Connector Pins

Electron Gun Control grid voltage

Figure-8.4: Cathode Ray Tube

8.4.2 LIQUID CRYSTAL DISPLAYS (LCDs)

LCDs were developed by the company RCA in the year 1960. An LCD is an electronically
modulated optical device which employs light-modulating properties of liquid crystals
combined with polarizers. The light is not emitted directly from the liquid crystals rather a

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reflector is used to produce images in color or monochrome. An LCD blocks the light to I/O Technology
display patterns. LCDs are lightweight screens and are mainly used for portable computers.
They are known for low power consumption, good resolution and bright colors. The LCDs can
be divided into following three categories based on display generation techniques.
1. Reflective LCDs: The display is generated by selectively blocking reflected light.
2. Backlit LCDs: The display is generated due to a light source behind LCD panel.
3. Edgelite LCDs: The display is generated due to a light source that is adjacent to LCD
panel.

LCD Technology
To manufacture the LCD screens, Nematic technology is used. The molecules of liquid
crystals (rod-shaped crystals) which are known as Nematic cells are used. Figure 8.5 depicts
Nematic cells. The Nematic cells are packed (sandwich) between two thin plastic membranes.
The Nematic cells have special properties i.e., these cells can change the polarity and bend of
the light. The electric current is used to control these properties by applying the electric on
grooves in the plastic membranes.

Figure-8.5: Nematic Cells

There exist two types of LCDs i.e., Passive matrix and Active matrix.
1. Passive Matrix- The passive matrix arrangement is most widely used technology due to
low weight, high image quality, low cost and high response time. LCD panel consists of a
grid of horizontal and vertical conductors. The conductors consist of Indium Tin Oxide to
create a picture. Each pixel is located at the intersection of two conductors in the grid.
Whenever current is passed through a pixel, it becomes dark
2. Active Matrix-It employs Thin Film Transistors (TFT) and that’s why known as TFT
technology. In active-matrix arrangement, TFTs are arranged in a matrix on a glass
surface and these TFTs are considered as pixels. These TFTs receives a small amount of
white light, which is then enhanced by TFT to activate a pixel. The advantage of using
TFTs is that they have faster response times, as they use smaller amount of light.
However, the disadvantage of using TFTs are that they are difficult to fabricate, therefore,
are costly. TFT LCD Display Technology is shown in the below Figure-8.6.

Figure-8.6: TFT LCD Display Technology

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8.4.3 Light Emitting Diodes (LED)

The light-emitting diode (LED) monitors display is a flat screen, flat-panel computer monitors
or television. It uses array of LEDs as pixels for displaying the videos. It is light weight and
has a very short depth. LCD monitors and LED monitors differ only in terms of backlighting;
typical LCD monitors uses fluorescent backlights whereas an LED monitor uses light-emitting
diodes. The earlier LCD monitors used CCFL instead of LEDs to illuminate the screen. LED
monitors offer many features/benefits namely slim design, flicker-free & brighter images,
longer lifespan, broader dimming range, low power consumption, better color and picture
quality etc. Figure 8.7 lists the benefits of LED monitors.

Figure-8.7 Benefits offered by LED monitors

Check Your Progress 1

1. Explain mechanical and optical mice.

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2. Discuss scan codes.

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3. What are the differences between LCDs and LEDs?

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8.5 VIDEO CARDS

First, this section discusses a brief overview of graphic display technology with the primary
focus on CRT monitors, before jumping to video hardware. The graphic display system is
responsible for displaying bit-mapped graphics on monitor. Every image is formed using small
dots which are known as picture elements or pixels. Figure 8.8 shows the pixels of an image.
The description of each pixel is stored in the memory which is taken care by video system.

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Pixels

Figure-8.8 Bit-mapped Graphics Image

The display memory which is used to store the data for images is known as frame buffer. At
any moment, the frame buffer consists of data for bit-map representation of current image on
screen and the next image. The frames are read dozens of times per second and sent to the
monitor using a cable in serial manner. Upon receiving the stream of data, the monitor forms
and displays it on the screen by scanning raster movement from first up to down one row at a
time. Based on this raster movement CRT, the monitor will illuminate its small phosphor dots.
It is shown in Figure 8.9 and Figure 8.10.

Frame Buffer Image

Figure-8.9: Frame Buffer and the corresponding image displayed on the system

The greater number of dots leads to better resolution of the image as well as the sharper the
picture. The number of dots directly correspond to the richness of the image (or gray levels for
a monochrome display) displayed by the system. The higher the number of colors, the more is
the information required for each dot. Therefore, higher resolution and color depth of the
system required bigger memory storage by the system to store the frame buffers.

Figure 8.10: Raster Display

8.5.1 Resolution
The resolution is defined as the possible sharpness or clarity of an image. The resolution does
not depend upon the physical characteristics of the monitor. It is measured in terms of number
of pixels on a monitor. For instance, a standard VGA graphic display with resolution 640×480
consists of 640 and 480 pixels on horizontal and vertical axes respectively. In order to
construct an image, different numbers of pixels are spread across both the axes of monitor
screen. Higher is the resolution, sharper is the image due to large number of pixels.
The sharpness of an image on actual live-screen does not depend only on resolution but it is
measured in the unit of dots-per-inch. These dots-per-inch are dependent on (i) size of the

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image and (ii) resolution of the image. An image will be sharper on a smaller screen in I/O Technology
comparison to bigger screen. For instance, an image may appear sharp on a 15" monitor and
may be a little jagged on a 12” monitor display. Figure 8.11 shows a circle with different
sharpness on different size monitor screens.

Figure-8.11: Circle with low and high resolutions

8.5.2 Color Depth

The image is constructed using stream of pixels. If the value of pixel is ‘ON’ and ‘OFF’, the
pixel will be displayed in image on the screen as a pure black and white respectively. If single
bit is assigned to a pixel, the image will be black and white. This system is known as two-
color system. The pure black and white images can be converted to gray levels, which are
different levels between white and black. This requires a greater number of bits to code each
pixel. For instance-if you assign two bits to each pixel, four color levels are possible: White,
Light Gray, Dark Gray and Black. In general, you need more than one bit to describe a pixel.
Hence, one bit per pixel implies 2 colors or 2 gray-levels, 2 bits per pixel implies 4 colors or 4
gray-levels, and 3 bits per pixel implies 8 colors and so on. It means n bits per pixel imply 2n
gray-levels. For colored images color codes for the intensity of the three primary colors, viz.
Red, Green and Blue, for each pixel are stored.
Color Depth can be understood as the number of bits allocated to every pixel in order to store
color code information. Since every bit of a pixel corresponds to a specific color i.e., all bits at
the same position for all pixels corresponds to the same color. Thus, the bits corresponding to
same color can be regarded to form a plane and these planes are known as color planes. It is
considered the color planes are stacked on top of each other which are helpful in deciding final
color at each pixel. Thus, depending upon number of bits required for each pixel, there are 3
Color Planes (one each for Red, Green and Blue). Figure-8.12 depicts the 3-bits color display
and 3 color planes.

Figure-8.12: 3-bits Color Display with 3 color planes

The computer system with a 3-bit RGB color planes utilized 1 bit for each of the red, green
and blue color components. Therefore, every color component can exist only in “ON" or
"OFF" state. The three-bit RGB ‘ON’ or ‘OFF” color components result in 8-colors consisting
of three primary RGB colors i.e., red, green and blue; two pure colors i.e., white and black;
and three complementary colors i.e., magenta, cyan, and yellow colors. The RGB values (ON"
or "OFF") of 3-bits color are given in Table 1 and the colors are displayed in Figure 8.13.

Figure-8.13: 8 possible colors for 3-bits Color Display

Table-1: 3-bit Color Display RGB values

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 Bit-values (‘ON’ or ‘OFF’) Color I/O Technology

0 0 0 Black
0 0 1 Blue
0 1 0 Green
0 1 1 Cyan
1 0 0 Red
1 0 1 Magenta
1 1 0 Yellow
1 1 1 White

What Color depths are practically used?

If n is the color depth representing the total number of bits used to store one pixel, the number
of colors will be 2n (2 to the power n). Table 2 puts the most popular color modes.

Table 2: Popular Color Depths

Sr. No. Color Depth(bits/pixel) Color Mode
1 1 Monochrome
2 4 16-Colours
3 8 256-Colours
4 16 High Color
5 24 True Color

Human & Color Depth of Monitor Screen

The modern monitors can display up to a maximum of 262,144 (218) colors for 18 bits/pixel
Color Depth. If different tones (color pitch) are allowed and eight bits are used for each RGB
color, a total of 16.77 million colors (256 tones (R) x 256 tones (G) x 256 tones (B) =
16,777,216 colors) can be generated. On the other hand, human eyes are capable to distinguish
maximum few million different colors. Thus, even if the monitor screens display colors more
than few million, they would not be distinguished by humans. It also implies that the practical
upper limit the 24-bit per pixel color depth. Since the number of possible colors produced by
this color depth is more than the colors that could be distinguished by human eye, these colors
are called the true colors. However, 24-bits color or true color systems have more color than
possibly useful; the extra 8-bits are used by designers to store special effects information of the
image. These extra bits formed a channel which is known as Alpha channel.

8.5.3 Video Memory

The video memory/frame buffer is used to store the video to be displayed. The quality of video
display depends on the efficiency of the video system i.e., how quickly the frames are accessed
and updated. Initially, a fixed area of RAM is allocated to the video memory. Later, video
RAM along with video cards was introduced and it can be increased by placing additional
video RAM under the unified memory architecture (UMA). UMA is helpful in reducing the
cost of computer system. In UMA supported systems, an area of main memory is used as
frame buffer/video memory which results is elimination of bus for video processing.
Therefore, the computer system with UMA may be less costly.
Basically, UMA comes with on-board video card in the modern low-cost motherboards. The
required resolution and color-depths are the deciding factor for the size of video
memory/frame buffer. The minimum size of video memory can be calculated simply by
multiplying the Color Depths and resolution of the monitor screen.
Let us solve a simple exercise. Assume a standard VGA monitor screen with resolution 800 
600 and color depth value 8.

Number of Pixels = 800  600=480000

Color Depth (8 or 23) = 3-bits
Minimum Memory required = 1,440,000 bits (180,000 bytes)
= 180 KB

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It implies that minimum RAM required for resolution 800  600 and 8 color depth is 180 KB. I/O Technology
But the memory is available in exponential power of 2 and the next minimum size of memory
is 256 KB. It implies that minimum size RAM required for resolution 800  600 and 8 color
depth is 256 KB.
Now-a-days, a very odd-looking resolution i.e., 1152×864 has become popular. Could you
guess why this is so? The following are the reasons behind its popularity. There are nearly one
million (9,95,328) pixels for VGA with 1152×864 resolution. For color depth value 8, nearly 8
million bits or 1 MB memory is required. Further, human eyes perceive only a few million
colors and this resolution is more suitable. In addition, a square pixel that has a ratio of 4: 3
allows easier programming.
Please note that the calculations shown above are not applicable for 3-D displays, which
requires more memory due to the issues like “Double Buffering” and/or “Z-Buffering”.

8.5.4 Refresh Rates

The Video Controller (a special circuit) scans the frame buffer and reads rows one by one
followed by sending this data in serial manner. On monitor screen, the electron beam starts
scanning one-line at a time from left to right direction in order to create images. The horizontal
refresh rate or horizontal frequency is the rate at which horizontal sweeps take place, while
vertical refresh rate or vertical frequency is the rate at which vertical sweeps take place. The
vertical frequency is also known as refresh rate or frame rate, as during a vertical sweep one
complete frame is displayed. There exist several hundred rows in each frame and thus,
horizontal frequency is hundreds of times higher than vertical frequency. The unit of
horizontal frequency is KHz while the unit of vertical frequency is Hz.
Note: It is necessary to maintain the same frequencies between the monitor and video system
for better quality of images. The compatible refresh rates are provided with the manual of the
monitor.

8.5.5 Graphic Accelerators

An important chip associated with video card is known as Graphic Accelerator which is the
replacement older technology known as Graphic Co-Processor. The graphic accelerator chip
is a dedicated unit that executes in-built video functions of image construction and rendering,
thus, releasing the microprocessor (main processor) from this work. The accelerator chips are
optional but they are required due to noticeable impact on the performance of the computer,
especially in graphics-intensive tasks such as- Rendering of 3D models and images, Video
editing and Gaming. The graphic accelerator are needed if you need the following:
 Good support to 3-D graphics.
 Better resolution of graphics.
 Larger size of memory in the frame buffer.
 Better speed of display of drop-down menu.
 Good quality video playback.
The Graphics accelerators are widely used in industries such as- Motion pictures for special
effects, Computer-aided design (CAD), Video games, 3D-effect etc.

What is a 3-D Accelerator?

The accelerator chip that has built-in ability to perform the mathematical calculations and
execute the algorithms required for 3-D image generation and rendering, are called 3-D
Accelerator. A 3-D image is just an illusion for human eyes which basically represents a
projection of 3-D images/videos on 2-D monitor screens. This conversion takes place by
projection and transparency effects, perspective effects, color depth and lighting effects. In
addition, the following techniques can be used for creating 3-D images on 2-D screens: (i)
Ray-Tracing, which traces the path of light rays emitted by a light source; (ii) Z-buffering,
which uses a buffer to store the third axis, i.e., Z-axis positions and (iii) Double-Buffering,
which uses two buffers in place of a single buffer.

8.5.6 Video Card Interfaces

A video card interface connects the video display to the computer system in order to improve
the performance of the visual data you see on your screen. The video card can either be a
separate component which is plugged into a slot on the motherboard of the computer or it may
be integrated into the motherboard known as “onboard”. For isolated video cards, the
connection is realized using either Peripheral Connect Interface (PCI) or Accelerated
Graphics Port (AGP) bus.

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 PCI- It is introduced by Intel and also known as Peripheral Component Interconnect. It is I/O Technology
a high-speed common bus which is used to attach the computer peripherals to the
motherboard. It is used to attach sound cards, network cards and video cards. The
computers may use now some modern technologies like PCI-Express (PCIe), USB and
AGP.
 AGP-It is also known as Advanced Graphics Port. It is a standard connector port used to
connect the video card with the microprocessor and the main memory. It is a dedicated
high-speed connection interface which is used by only graphics subsystem. AGP employs
pipelining, isolated data and address buses and high-speed mode to improve the
performance of graphics card.
In specific computers, the video card is directly connected with the microprocessor and
may use direct memory access (DMA) I/O technique to send data from main memory to
frame buffer.

8.6 SOUND CARDS

Multimedia has become an indispensable component of personnel computers to play different
music files like MP3, MP4, WAV (Waveform audio file), WMA (Windows media audio),
AAC (Advanced audio coding), FALC (Free lossless audio codec), OGG (The latest Free
Sound format standard) etc.
The Sound card can either integrated into motherboard (built-in sound card) or connected
through expansion slot. As you may study in computer networks, the analog sound waves
could be converted into electrical form using electrical signals, which is used to compute the
strength of sound. Usually, the analog audio signal is converted into digital audio (or digital
signals) in the form of bits using sampling process. The microprocessor manipulates the digital
audio bits and this data is sent to the sound card. The sound card converts this data into analog
audio in order to play back through the speakers or headphones. The major functions of a
modern sound card are as follows:
1. Conversion from digital sound signals to analog form to play back the sound.
2. Amplifiers to augment the strength of sound signals
3. Sound recording.
4. Sound synthesis.
5. Mixing of sound from various resources.

The three basic issues relating to sound cards are - Compatibility, Connections and Quality.
 Compatibility: Sound cards must be compatible for hardware as well as for software
to meet the current industry standards/protocols. Some specific software like games
need sound cards to be compatible with industry standards. You may refer to further
readings to know about these standards.
 Connections: The sound card must provide different connections in order to perform
various functions. It should provide MIDI port (Musical Instrument Device Interface)
which allows user to produce music directly by using synthesizer circuit in the sound
card. It also allows connecting a Piano keyboard to the computer system.
 Quality: There exist different sound cards which provide sounds with different
qualities. The quality of sound differs due to the noise control, digital quality and the
ranges of frequency supported by the sound card.

Check Your Progress 2

1. Explain the concept of a frame buffer in the context of Video Card interfaces.
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2. What do you understand by horizontal and vertical frequencies?
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3. Compute the minimum required video memory for 16 color depth and a monitor screen
with the highest possible resolution 7680x4320.
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4. Explain sound card. What are the functions of sound card?
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8.7 DIGITAL CAMERA

The first digital camera was invented in the year 1975 by Steven Sasson at Eastman Kodak.
Digital camera is a hardware device that takes images or record videos and stores them on
memory as digital data on memory card instead of on photographic film in analog camera. In
digital Camera, the images are stored in digital form and thus they can be reused later for
different purposes like printing, editing etc. Since the digital camera takes images (input) and
sends them to computer (output), it is considered as input as well as output device.
Figure 8.14 depicts the digital camera which is taking an image of subject (scene) under
consideration. A digital camera consists of a sequence of lenses which focuses light on to a
semiconductor device to create an image of a scene under consideration. The semiconductor
device, in turn, records this light as digital images by using an in-built processor.
The semiconductor device is known as an Image sensor which converts light into electrical
charges. Two types of Image sensors exist: Charge Coupled Devices (CCD) and
Complementary Metal Oxide Semiconductor (CMOS). CCD is more popular and powerful
kind of sensor in comparison to CMOS image sensors.

Figure-8.14: Working of a Digital Camera

The resolution (pixels) of digital camera is major deciding factor for the quality images. The
higher the resolution, the better the digital camera is. The major benefits of a digital camera are
as follows
 Allows user to see the videos and images immediately
 Allows user to store thousands of images/videos due to in-built memory
 Digital cameras are portable
 Allows user to edit images directly
 Allows flexibility in printing of desired images

8.7.1 Webcam
A digital camera without storage connected to computer system or network is referred as
Webcam. In modern computers, the webcam can either be a separate component which is
plugged into the computer or be an in-built integrated camera. In order to use webcams, it is
necessary to install the required software. A webcam is an input device which is used to
capture the images/videos and then send it to the computer. Webcams are used for
videoconference or video calling or online meeting using Google Meet, Zoom, MS Team and
others services.
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8.8 Voice Based Input Device
Modern devices are capable to take human voice as input using speech recognition processes
and execute applications accordingly. These devices are known as Voice Based Input devices.
As compared to microphone, the speech recognition process of these devices recognizes
human voice; converts it into machine-language and execute programs/applications
accordingly. Figure 8.15 two devices which use speech recognition process to recognize
human voice.

Figure-8.15: (a) Siri (b) Echo Dot 3 Smart Speaker with Alexa
The Voice Based Input Devices can recognize spoken words in two ways. The spoken words
can either be recognized from a pre-defined vocabulary or be recognized from a known
speaker after training of the input device. Whenever speaker utters a word from the pre-defined
vocabulary, the Voice Based Input device may display the characters of monitor screen for
verification by the speaker. However, some of these devices may process the speech without
verification from the speaker. The process of speech recognition compares each uttered word
with the words stored in pre-defined vocabulary table.

8.8.1 Siri
Apple Inc. offers a built-in, voice-controlled virtual assistant with most of products i.e.,
iPhone, iPad, Apple Watch or Mac (macOS Sierra and later) etc. This voice-controlled
personal assistant is known as Siri. The users may talk to Siri as they talk to their friends. Siri
allows a seamless interaction with Apple devices such that user speaks to Siri and Siri speaks
to user. Siri helps users to get their job done after receiving user commands. Siri can help to
open a file, send messages, open a web browser, open a website, booking a ticket, watch
movies, and many other activities.
Siri works based on the Artificial Intelligence and Natural Language Processing fields. It
consists of three components -Conversational interface, personal context awareness and
service delegation systems. The conversational interface understands the user word-for-word
manner and the semantic of text is produced using personal context awareness which is based
on habit and language of the user. The service delegation helps to deliver services using built-
in apps and their inner workings.

8.8.2 Alexa
Amazon offers virtual interactive voice-based AI powered digital assistant known as Alexa.
This device has been designed in association with Alexa Voice Service (AVS) in order to
simulate real conversations. “Alexa” is basically the “wake word” which is used to alert the
device to start listening the voice to perform some tasks. Alexa employs intuitive voice
commands to provide services to perform some specific tasks. Figure 8.15(b) depicts the
Amazon Alexa. It is available as Echo speakers, smart thermostats, lamps and lights, and right
on your phone through the Alexa app. Alexa can do quick math, play music, check news and
weather updates, read emails and control many of the smart products.
Alexa also works based on the Artificial Intelligence and Natural Language Processing fields.
It Alexa consists of speakers, microphone and a processor which is used to activate the device.
It receives input and sends it to cloud where Alexa Voice services (AVS) interprets and
understands the user input. Accordingly, AVS sends the appropriate output back to user
device. The internet connection is the basic requirement to use Alexa.

8.9 PRINTERS

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Printers are devices that accept textual and graphical contents as output from a computer I/O Technology
system and print contents on paper in a controlled manner. The text and photographic images
are produced by printers. Printers differ in technology used, memory, speed, resolution, color
supported, size, hardware compatibility, cost and others factors. The present-day printer
technologies include the dot matrix printer, Inkjet or tank printers, Laser Printers etc. to serve
different needs. The available printers can be divided into two classifications-Impact and Non-
impact printers. Figure 8.16 shows the classifications of printers.

Figure-8.16: Classification of Printers

8.9.1 Impact Printers

Impact printer uses mechanical components for printing i.e., physical contact between printing
head and paper. In order to print, the characters and graphics are produced on a paper by
striking. They produce banging noise during printing. Impact printers can be divided further
two categories-Character and line printers. The character printers print only one at a time by
striking on ribbon whereas line printers print one line at time. The line printers are fast and
costly printer in comparison to character printers. Different types of impact printers are line
printers, dot-matrix printers and, daisy-wheel printers.

(b)
(a)
Figure-8.17: (a) Dot-matrix printer (b) Local Railway ticket

Dot Matrix Printer

A Dot Matrix Printer (DMP) employs fixed number of pins to print on paper. The print head
with many pins runs back and forth on the page and prints by striking against a socked cloth
ribbon in order to make a mark on paper. In DMP, the characters are using matrix of dots and
the printed character is basically an accumulation of several dots on the paper. Therefore, the
arbitrary font or graphics will be generated in each printing. Figure 8.17 shows a DMP and the
local railway ticket printed by DMP.

8.9.2 Non-Impact Printers

In non-impact printer, no mechanical moving component is employed for printing. These
printers don’t strike or impact the ribbon for print. The technologies used by non-impact
printers are chemical, inkjet, electrostatic, xerographic and laser. These printers work silently.
Non-impact printers can be further divided into two categories-Character and Page printers.
The non-impact character printers spray tiny drops of ink on to the without striking/physical
contact with paper. The page printers print one full page at once. Different types of non-impact
printers are inkjet, photo, and laser printers.
Laser Printer

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Laser printers are very common page printers and print one page at once. Laser printers I/O Technology
employ a focused light beam to transfer image or text onto paper. The modern laser printer use
Resolution Enhancement Technology (RET) which is introduced by Hewlett-Packard. This
technology smoothens the edges of character, diagonal lines etc. to produce better quality
printouts. To produce high quality print, the basic requirement is the memory which increases
as a square of resolution i.e., dots per inch (DPI). For 600 dpi, approximately 3.5 MB
(600x600 bits) memory is required whereas 14 MB (1200x1200 bits) is required for 1200 dpi.
Figure 8.18 depicts a single function monochrome laser printer.

Figure-8.18: Single function Monochrome Laser Printer

8.10 SCANNERS
A scanner is an electronic device which is used to capture images from tangible sources like
photographic images, paper, posters, slides and others. The scanner converts the captured
images into electronic form and stores them in computer memory in order to view/modify
later. The scanner employs light sensors arranged in the form of an array in scan-able area. The
light sensors detect differences in brightness of reflections from an image and then scan the
source.
The existing scanners differ in many factors such as compatibility, resolution, support for
different media and interfaces, etc. Two popular types of scanners are - Flatbed Scanners and
Handheld Scanners.
Flatbed Scanners are used to scan high-resolution tangible images into detailed and sharp
electronic images. The images are placed on a flat glass tray and movable sensors are used to
scan the images. Figure 8.19(a) shows a flatbed scanner. Handheld scanners are used to scan
the physical documents, and require good hand control for high quality scanning. These are the
most portable and cheapest scanners and shown in Figure-8.19(b).

Scanning is used for many different applications. The scanners are used as Magnetic Ink
Character Recognition (MICR) scanner in order to scan cheques and Bar-Code readers to
identify different objects. One more application is Optical Recognition of Characters (OCR).
The OCR software use character/pattern matching algorithms to recognize characters and
converts the scanned text to a text file. The OCR technology is very much useful in digitizing
the ancient text written in old scripts.

Figure-8.19: (a) Flatbed Scanner (b) Handheld Scanner

8.10.1 Resolution
The resolution of scanner is the quality of image achieved by scanner. It is measured in dots
per inch (dpi) and it indicates the number of dots per inch scanned horizontally and vertically.
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It implies that the more is the dpi of a scanner, the more details a scanned electronic image will I/O Technology
have. The scanned file size increases with increased resolution. There are various ways to
measure the resolution.

Optical Resolution - The upper resolution limit of a scanner which is used to scan the images
is known as optical resolution (hardware resolution). For example- if the optical resolution of
a scanner is 300 dpi, it means 90000 (300x300) pixels per square inch can be captured by the
scanner. The scanners may be available with optical resolutions of 300, 600, 1200, 2400 dpi or
even more.

Interpolated Resolution- The resolution of image can be augmented using interpolation

algorithms and this resolution is known as Interpolation resolution. The interpolation
technique employing complex algorithms is used to add intermediate pixels based on the
properties of surrounding pixels. The interpolation technique results in increased size of
scanned images but it provides smoother and high-quality images without adding any
additional information. For instance- if the optical and interpolated resolutions are 300x300
dpi and 4800x4800 dpi respectively. This implies 90000 pixels per square inch can be captured
by the scanner while the interpolation algorithm can add 15 pixels between every pair of pixels
to increase the dpi of image.

8.11 MODEMS
Modem (i.e., modulator-demodulator) is a device that connects two computers using telephone
lines in order to exchange data with each other. The modem receives digital signals from
computer, puts them into analog circuit by modifying a constant wave (known as carries) and
then analog signals are transmitted over the telephone lines. This process is known as
modulation. It occurs whenever user connects to the Internet. Demodulation is the inverse
process of modulation in which the digital signals are derived from the modulated wave. It
occurs whenever user receives data from a website, which is then displayed by your browser.
Figure 8.20 shows the process of modulation and demodulation performed by the modem. You
may refer to further readings for more details on modulation and demodulation techniques.

Figure-8.20: Modulation and Demodulation process by Modem

Check Your Progress 3

1. Explain webcam and its major benefits.

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2. How characters are recognized by voice-based input devices? I/O Technology
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3. Compare impact and non-impact printers.
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4. Explain Interpolated resolution.
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5. How many pixels can be captured by a scanner with 600 dpi optical resolution?
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8.12 SUMMARY
This unit discussed several input/output devices and the technologies behind them. This unit
covers different input device along with different components or types or features. It is
discussed Mouse and classifications of Mice, Keyboard along with its features, voice-based
input devices, scanners and webcam its different types. This unit also discussed output devices
along with other components or types or features. It discussed computer monitors with three
different categories i.e., CRT, LCD and TFT screens. The printers with their different
categories have also been discussed. The video cards have also been discussed with their
characteristics like resolution, color depth, video memory, refresh rates, graphic accelerators
and video card interfaces. It also discussed sound cards with its functions and different
characteristics. At last, the modem device is discussed in brief manner.

8.13 SOLUTIONS/ ANSWERS

Check Your Progress 1
1. Mechanical mouse has a rubber or metal ball in middle, which is used to control the
movement of cursor. The sensors inside the ball detect the rotation of ball. When the ball
rolls with the movement of mouse, it causes sensors to detect the rotation of ball along the
two axes which consequently send signals to monitor screen. Figure 8.1(a) depicts the
mechanical mouse.
Optical mice use light emitting diodes (LEDs), optical sensors and digital image
processing. The optical mouse detects by sensing the changes in the reflected light. The
change in reflected light is measured by analyzing the images and the cursor moves on
screen accordingly. Figure 8.1(b) shows the optical mouse.

2. Scan Codes-When a key is pressed on a keyboard, it transfers the scan code relating to
those keys to the processor. Scan code of every key is unique. The scan codes are used to
communicate the desired data or action to the processor. A keyboard of processor is
connected through interrupt driven I/O mechanism. Therefore, when a key or several keys
are pressed together on the keyboard, it interrupts the processor, provided processor has
enabled interrupts. The processor receives the scan code/codes and identifies the key or
keys that were pressed using the scan code table stored in the ROM BIOS.

3. LCD monitors and LED monitors differ only in terms of backlighting; typical LCD
monitors uses fluorescent backlights whereas an LED monitor uses light-emitting diodes.
The earlier LCD monitors used CCFL instead of LEDs to illuminate the screen.

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1. The display memory which is used to store the data for images is known as frame buffer.
At any moment, the frame buffer consists of data for bit-map representation of current
image on screen and the next image. The frames are read dozens of times per second and
sent to the monitor using a cable in serial manner. Upon receiving the stream of data, the
monitor forms and displays it on the screen by scanning raster movement from first up to
down one row at a time. Based on this raster movement CRT, the monitor will illuminate
its small phosphor dots.

2. Refer text 8.5.4

3. The minimum required video memory is computed as follows-

Number of Pixels = 7680  4320 = 33,177,600

Color Depth (16-colours = 24) = 4-bits
Minimum Memory = 132,710,400 bits (16,588,800 bytes)
= 16,200 KB = 15.82 MB

4. Sound card is used to convert digital audio data into analog audio in order to play back
through the speakers or headphones. The Sound card can either integrated into
motherboard (built-in sound card) or connected through expansion slot. The major
functions of a modern sound card are as follows:
a) Conversion from digital sound signals to analog form to play back the sound.
b) Amplifiers to augment the strength of sound signals
c) Sound recording.
d) Built-in synthesizer
e) Sound mixer circuits.

Check Your Progress 3

1. A digital camera without storage connected to computer system or network is referred as
Webcam. In modern computers, the webcam can either be a separate component which is
plugged into the computer or be an in-built integrated camera. The webcam can be used
for video conference or video calling or online meeting using Google Meet, Zoom, MS
Team and others services.

2. These devices recognize spoken words in two ways. The spoken words can either be
recognized from a pre-defined vocabulary or be recognized from a known speaker after
training of the input device. Whenever speaker utters a word from the pre-defined
vocabulary, the Voice Based Input device may display the characters on monitor screen
for verification by the speaker. However, some of these devices may process the speech
without verification from the speaker.

3. Impact printer uses mechanical components for printing i.e., the characters and graphics
are produced on a paper by striking whereas non-impact printer don’t strike or impact the
ribbon to print on paper. Impact printers produce banging noise during printing while non-
impact printers work silently.

4. Refer text 8.10.1

5. The scanner can capture 360000 pixels per square inch

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