Programmable Logic

PAL, PLA
 PALs

• Programmable Array Logic

 a fixed OR array.

Inputs

Dense array of Dense array of

AND gates Produc t OR gates
terms

Outputs

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PAL
inputs

1st output
section

2nd output Only functions with

section at most four
products can be
implemented
3rd output
section

4th output
section

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 PAL

x
x

W = ABC + CD
X = ABC + ACD + ACD + BCD
Y = ACD + ACD + ABD

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PAL IC

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PAL

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Examples of PAL Implementatioin

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 PLAs
Programmable Logic Array

 Pre-fabricated building block of many

AND/OR gates (or NOR, NAND)
"Personalized" by making/ breaking
connections among the gates.

 General purpose logic building blocks.

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 PLA

Inputs

Dense array of Dense array of

AND gates Produc t OR gates
terms

Outputs

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PLA

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 PLA

• A 3×2 PLA with 4 product terms.

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Full Adder using PLA

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 Design for PLA:
Example
 Implement the following functions using PLA
F0 = A + B' C'
F1 = A C' + A B Input Side:
F2 = B' C' + A B
F3 = B' C + A 1 = asserted in term
0 = negated in term
- = does not participate
Personality Matrix
Product Inputs Outputs
term A B C F0 F1 F2 F3 Output Side:
AB 1 1 - 0 1 1 0 1 = term connected to output
Reuse 0 = no connection to output
BC - 0 1 0 0 0 1
AC 1 - 0 0 1 0 0 of
terms
BC - 0 0 1 0 1 0
A 1 - - 1 0 0 1

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 Example: Continued
A B C

F0 = A + B' C' AB
F1 = A C' + A B
F2 = B' C' + A B B’C
F3 = B' C + A
AC’
B’C’

Personality Matrix A

Produc t Inputs Outputs

term A B C F0 F1 F2 F3
AB 1 1 - 0 1 1 0 F0 F1 F2 F3
BC - 0 1 0 0 0 1 Reuse
AC 1 - 0 0 1 0 0 of
1 0 1 0 terms
BC - 0 0
A 1 - - 1 0 0 1

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 Constants
 Sometimes a PLA output
must be programmed to
be a constant 1 or a
constant 0.
− P1 is always 1
because its product
line is connected to
no inputs and is
therefore always
pulled HIGH;
− this constant-1 term
drives the O1 output.
 No product term drives
the O2 output, which is
therefore always 0.
 Another method of
obtaining a constant-0
output is shown for O3.

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 BCD to Gray Code Converter
A B C D W X Y Z A A
0 0 0 0 0 0 0 0 AB AB
0 0 0 1 0 0 0 1 CD 00 01 11 10 CD 00 01 11 10
0 0 1 0 0 0 1 1 00 0 0 X 1 00 0 1 X 0
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 1 1 1 0 01 0 1 X 1 01 0 1 X 0
0 1 1 0 1 0 1 0 D D
0 1 1 1 1 0 1 1 11 0 1 X X 11 0 0 X X
1 0 0 0 1 0 0 1 C C
1 0 0 1 1 0 0 0 10 0 1 X X 10 0 0 X X
1 0 1 0 X X X X
1 0 1 1 X X X X B B
1 1 0 0 X X X X
K-map for W K-map for X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X A A
AB AB
CD 00 01 11 10 CD 00 01 11 10

00 0 1 X 0 00 0 0 X 1

Minimized Functions: 01 0 1 X 0 01 1 0 X 0
D D
11 1 1 X X 11 0 1 X X
W=A+BD+BC C C
X = B C' 10 1 1 X X 10 1 0 X X
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C D' B B
K-map for Y K-map for Z

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 Implementation ofA BCD
B C D
to Gray code
A

BD

4 product terms per each OR gate BC

BC’

Product terms cannot be shared !

B
PLA achieves higher flexibility
C
at the cost of lower speed!

BCD
AD’

BCD’

W X Y Z
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