Embedded System and Programming
Embedded System and Programming
Unit II
1. discuss on the pull up resistance availabilty on the ports pins of 8051
and describe the function enabling by combing port 0 and 2 also
mention the specific or dedicated function of port 3 pins
The 8051 microcontroller has four I/O ports, Port 0, Port 1, Port 2, and Port
3. Each port has 8 pins, and these pins can be programmed as either
inputs or outputs.
Regarding the pull-up resistance availability on the port pins of 8051, it's
important to note that there are no internal pull-up resistors in the 8051
microcontroller. Therefore, to enable the pull-up resistor for any of the
port pins, an external resistor must be connected to the pin.
When it comes to combining Port 0 and Port 2, it's common to use them
together as an 8-bit bidirectional data bus. This is often done to interface
with external devices or peripherals that require data transfer. In this
configuration, Port 0 is used as the lower-order byte, while Port 2 is used
as the higher-order byte.
2. generate a square wave of 50% duty cycle on the p1.5 bit using timer 0 to
create time delay of 5 sec for the standard crystal frequency in ALP
ChatGPT
Sure, here's an example code in assembly language for 8051 microcontroller that
generates a square wave of 50% duty cycle on the P1.5 pin using Timer 0 to create a
time delay of 5 seconds for a standard crystal frequency:
DELAY:
DELAY_1:
DELAY_2:
DJNZ TH0, DELAY ; Decrement TH0 and jump to DELAY until TH0 = 0
END
In this code, the Timer 0 is set in mode 1, which is 16-bit timer mode. The Timer 0 is
used to generate a time delay of 5 seconds by repeatedly decrementing the TH0
register until it reaches zero.
During the delay, the P1.5 pin is toggled every time the TH0 register overflows,
creating a square wave with a 50% duty cycle.
Note that the crystal frequency is not specified in the question, so it is assumed to
be the standard frequency of 11.0592 MHz for the 8051 microcontroller. If a different
crystal frequency is used, the delay loop will need to be adjusted accordingly.
3. with a neat diagram explain the working principle of the blocks available in
8051 architecture
Sure, I can explain the working principle of the blocks available in the 8051
architecture along with a neat diagram.
1. CPU: The CPU (Central Processing Unit) is the main processing unit
of the 8051 microcontroller. It executes instructions fetched from
the program memory and performs arithmetic and logical
operations.
2. Program Memory: The program memory stores the instructions that
are executed by the CPU. The 8051 microcontroller has a Harvard
architecture, which means that it has separate program memory
and data memory. The program memory is usually implemented as
a ROM (Read-Only Memory) or a Flash memory.
3. Data Memory: The data memory stores the data that is used by the
CPU during program execution. The 8051 microcontroller has 128
bytes of RAM (Random Access Memory), which is divided into four
banks of 32 bytes each.
4. Timer/Counter: The 8051 microcontroller has two 16-bit
Timer/Counters, Timer 0 and Timer 1. These timers can be used to
generate delays, measure time intervals, or count external events.
5. Interrupt Controller: The interrupt controller manages the interrupt
requests generated by the 8051 microcontroller. It provides a
priority system for handling multiple interrupt requests and allows
the CPU to respond to these requests in a timely manner.
6. Serial Communication: The 8051 microcontroller has a built-in UART
(Universal Asynchronous Receiver Transmitter) that supports serial
communication. It can be used to communicate with other devices
or peripherals using standard communication protocols such as RS-
232 or UART.
7. I/O Ports: The 8051 microcontroller has four I/O ports, Port 0, Port 1,
Port 2, and Port 3. Each port has 8 pins, and these pins can be
programmed as either inputs or outputs.
8. Oscillator and Clock Circuit: The oscillator and clock circuit generate
the clock signals required by the 8051 microcontroller. The 8051
microcontroller can operate at different frequencies, depending on
the crystal frequency used.
1. Physical Layer: The physical layer is responsible for transmitting and receiving
data over the air. It uses radio frequency (RF) to transmit data between
devices. The Bluetooth standard uses the ISM (Industrial, Scientific, and
Medical) band at 2.4 GHz for communication.
2. Data Link Layer: The data link layer is responsible for managing the
connection between two Bluetooth devices. It provides error correction, flow
control, and packet synchronization. The Bluetooth data link layer uses a
protocol called the Bluetooth L2CAP (Logical Link Control and Adaptation
Protocol) to ensure reliable data transfer.
3. Application Layer: The application layer is responsible for defining the specific
services and features of Bluetooth. It includes profiles, which are sets of
protocols and features that enable specific types of applications, such as
audio streaming, file transfer, or device control.
1. Classic Mode: The classic mode is used for traditional Bluetooth applications,
such as audio streaming and file transfer. It has a range of up to 100 meters
and supports data transfer rates of up to 3 Mbps.
2. Low Energy Mode: The low energy mode, also known as Bluetooth Low Energy
(BLE), is designed for applications that require low power consumption and
long battery life, such as fitness trackers and smartwatches. It has a range of
up to 50 meters and supports data transfer rates of up to 1 Mbps.
The Bluetooth module is powered by a +5V power supply, while the 8051
microcontroller is powered by a +5V power supply or a battery. The
Bluetooth module has a built-in antenna for wireless communication.
ChatGPT
SPI (Serial Peripheral Interface) is a synchronous serial communication protocol that
is widely used for communication between microcontrollers and peripheral devices
such as sensors, displays, and memory devices. In SPI communication, devices can
be categorized as either a master or a slave. The master device initiates the
communication and controls the timing of the data transfer, while the slave device
responds to the master's commands and sends data back to the master.
Here's a brief explanation of the master and slave communication of the SPI
protocol:
Master Communication:
1. The master device initiates the communication by sending a start bit (called
the "chip select" or "CS" signal) to the slave device. This signal indicates that
the master device is ready to communicate with the slave device.
2. The master device then sends a clock signal to the slave device. The clock
signal determines the rate at which data is transmitted.
3. The master device sends a series of bits (usually 8 bits) to the slave device.
Each bit is sent on the rising or falling edge of the clock signal, depending on
the clock polarity and phase configuration.
4. After all the bits have been transmitted, the master device sends a stop bit to
indicate the end of the communication.
Slave Communication:
1. When the slave device receives the CS signal from the master device, it
knows that the master device wants to communicate with it.
2. The slave device waits for the clock signal from the master device.
3. When the clock signal arrives, the slave device reads the first bit of data from
the master device. The slave device sends its own response bit (if necessary)
on the next clock cycle.
4. The slave device continues to read and respond to each bit of data until the
end of the communication is signaled by the stop bit.
In SPI communication, the master device controls the timing of the data transfer and
initiates the communication, while the slave device responds to the master's
commands and sends data back to the master. This makes SPI communication well-
suited for applications that require fast and reliable data transfer, such as real-time
control systems, industrial automation, and communication with memory devices.
Unit iii
1. write an c program that displays a value value of "Y" at port 0 and "N" at
port 2 and also generate a sqaure wave of 10 khz, with timer 0 in mode 2
at port pin p1.2 XTAL = 22Mhz
Sure, here's a sample C program that displays the value "Y" at port 0 and "N" at
port 2 of an 8051 microcontroller, and generates a square wave of 10 kHz on port
pin P1.2 using Timer 0 in Mode 2. The crystal frequency used in this example is
22 MHz.
#include <reg51.h>
void main()
P0 = 0x00;
P2 = 0x00;
// Main loop
while (1)
{
P0 = 0x59;
P2 = 0x4E;
2 writa an 8051 c program to send letter ' M' , 'D' , and 'E' to the lcd using delays
ChatGPT
Sure, here's a sample C program that sends the letters 'M', 'D', and 'E' to an LCD
display using delays on an 8051 microcontroller:
#include <reg51.h>
#include <stdio.h>
sbit RS = P2^0;
sbit EN = P2^1;
sbit D4 = P1^4;
sbit D5 = P1^5;
sbit D6 = P1^6;
sbit D7 = P1^7;
// LCD Functions
void lcd_init();
void main()
lcd_data('M');
lcd_data('D');
lcd_data('E');
}
// LCD Initialization Function
void lcd_init()
D6 = (dat &
3 explain with the neat sketch about the interfacinf of 7 segment display with 8051
micro controller
ChatGPT
Interfacing a 7-segment display with an 8051 microcontroller is a common and
useful application. A 7-segment display is a simple and commonly used electronic
display device that can display numbers and some characters. The display consists
of seven segments that can be lit in different combinations to represent different
numbers.
Here is a basic schematic diagram of the 7-segment display interfaced with an 8051
microcontroller:
+----------------+
| |
P1.0 ---->| a |
P1.1 ---->| b |
P1.2 ---->| c |
P1.3 ---->| d |
P1.4 ---->| e |
P1.5 ---->| f |
P1.6 ---->| g |
| |
+----------------+
#include <reg51.h>
void main()
{
// Set Port 1 pins as outputs
P1 = 0x00;
In this example, we set Port 1 as outputs and then set the appropriate bits
to light up the b and c segments, which represent the number 1. The
program then enters an infinite loop to keep the number displayed on the
7-segment display.
4 explain the interrupt structura and its priority level of 8051 micro controller along
with the interrupt priority level its stack vector address and flags affected
ChatGPT
Interrupts are an essential part of any microcontroller-based system. The 8051
microcontroller has five interrupt sources that can be used to trigger interrupt
service routines (ISRs). These interrupt sources are:
Each interrupt source has a corresponding interrupt flag bit. When an interrupt
occurs, the corresponding flag bit is set in the interrupt flag register. The interrupt
flag register is a special register that is used to indicate which interrupt sources have
occurred.
When an interrupt occurs, the microcontroller saves the current program counter
(PC) and status register (PSW) on the stack. It then jumps to the interrupt vector
table to get the address of the interrupt service routine for the interrupt source that
occurred. The microcontroller then executes the interrupt service routine.
The interrupt service routine must save any registers that it uses on the stack and
restore them before returning. When the interrupt service routine is finished, it
executes the RETI instruction, which restores the PC and PSW from the stack and
returns control to the main program.
The stack vector addresses for each interrupt source are as follows:
1. External interrupt 0 (INT0) - the interrupt flag bit, the PSW register
2. Timer 0 interrupt - the interrupt flag bit, the PSW register, the timer 0
registers
3. External interrupt 1 (INT1) - the interrupt flag bit, the PSW register
4. Timer 1 interrupt - the interrupt flag bit, the PSW register, the timer 1
registers
5. Serial communication interrupt - the interrupt flag bit, the PSW register, the
serial communication registers
+5V
|
-----
| |
| | +-----------+
| | | |
| |<----AIN0-| |
| | | ADC0804 |
| |<----WR--| |
| | | |
| |<----CS--| |
| | | |
| |<----RD--| |
| | +-----------+
| |
-----
|
GND
+-----------+
| |
| 8051 MCU |
| |
In summary, the ADC0804 can be interfaced with the 8051
microcontroller to convert analog signals into digital values. The
microcontroller controls the conversion process by setting the
start pin of the ADC0804 high, and reads the digital output value
from the ADC0804's digital output pins. This digital value can then
be used by the microcontroller for further processing or display.
Regene
6 write a c code to interface the sensor with adc to the 8051 micro controller
ChatGPT
To interface a sensor with an ADC to an 8051 microcontroller, you need to follow
these steps:
1. Connect the analog output of the sensor to one of the analog input pins (AIN0-
AIN7) of the ADC.
2. Connect the control lines (CS, RD, WR) of the ADC to three port pins of the
microcontroller.
3. Write a function to read the ADC value. This function should start the
conversion process by setting the start pin of the ADC high, then wait for the
conversion to complete. Once the conversion is complete, the function should
read the digital output value from the ADC and return it.
4. Write a function to read the analog value from the sensor. This function
should use the ADC reading function to convert the analog value to a digital
value, then convert that digital value back to an analog value using the
appropriate formula for your sensor.
#include <reg51.h>
CS = 0;
P0 = channel;
// Start conversion
WR = 0;
WR = 1;
RD = 0;
while (RD);
// Read result
result = P0;
CS = 1;
return result;
float analog_value;
adc_value = read_adc(channel);
analog_value = (adc_value * 5.0) / 1024.0; // Convert ADC value to
analog voltage (assuming a 5V reference voltage)
return sensor_value;
void main() {
while (1) {
In this code, the read_adc function reads the ADC value from a given channel using
the control lines connected to the microcontroller. The read_sensor function then
reads the analog value from the sensor using the read_adc function, converts it to a
sensor value using the appropriate formula, and returns the result. The main loop of
the program continuously reads the sensor value and does something with it.
Unit iv
1 Draw the architectural block diagram of ARM7 and explain data flow referring
each unit.
ChatGPT
Here is the architectural block diagram of ARM7:
The ARM7 consists of three main components: the CPU core, memory, and
peripherals. The CPU core is responsible for executing instructions and
performing arithmetic and logical operations on data. The memory
provides storage for program instructions and data, and the peripherals
are devices that allow the ARM7 to communicate with the outside world.
Data flows between these components via the data bus, which is a set of
wires that connect the CPU core, memory, and peripherals. The CPU core
sends instructions and data to memory and peripherals, and reads data
from them, through the data bus. Similarly, memory and peripherals send
data to the CPU core and receive data from it through the data bus.
The CPU core includes a data processing unit (DPU) and an arithmetic
logic unit (ALU). The DPU performs data operations such as shifting,
rotating, and logical operations, while the ALU performs arithmetic
operations such as addition, subtraction, multiplication, and division. The
CPU core also includes registers that hold data and control information,
such as the program counter (PC), stack pointer (SP), and status register
(PSR).
ChatGPT
An addressing mode is a technique used in computer architecture to specify the
effective memory address of an operand. The effective address is calculated by
combining a base address and an offset or index value.
ARM7 processors support several addressing modes, which allow flexible and
efficient access to memory operands. Here are four addressing modes supported by
ARM7 processors:
4. Draw and explain the functions of the barrel shift register and the flags associated
with it.
ChatGPT
A barrel shifter is a combinational digital circuit that can shift a binary number by a
specified number of bits in a single clock cycle. It is often used in microprocessors to
perform arithmetic and logical operations, such as multiplication and division.
The barrel shifter consists of a set of shift registers arranged in a circular fashion,
with each register capable of shifting its contents to the next register in the
sequence. The shift amount is determined by a control signal that selects the
appropriate shift register.
The barrel shifter in ARM processors is capable of shifting 32-bit data by 0 to 31 bits.
It has two modes of operation: logical shift and arithmetic shift. In logical shift mode,
the bits that are shifted out of the data word are always set to 0, while in arithmetic
shift mode, the most significant bit is duplicated to maintain the sign of the number.
The barrel shifter also sets several flags based on the result of the shift operation:
1. Carry flag (C): This flag is set if the shift operation results in a carry out of the
most significant bit.
2. Zero flag (Z): This flag is set if the result of the shift operation is zero.
3. Negative flag (N): This flag is set if the result of the shift operation has the
most significant bit set.
4. Overflow flag (V): This flag is set if the shift operation results in an overflow.
The barrel shifter is an important component of modern microprocessors, as it
enables efficient execution of arithmetic and logical operations on large data sets. Its
ability to shift data by variable amounts in a single clock cycle makes it an essential
building block for high-performance computing.
Both branch and data processing instructions are essential for building complex
programs in the ARM processor architecture. They provide the basic building blocks
for controlling program flow and performing operations on data.
6. Explain the need for a fast interrupt service and a normal interrupt service in ARM7
programmer model with proper diagram.
ChatGPT
The ARM7 processor supports two types of interrupt service routines: fast interrupt
service routine (FIQ) and normal interrupt service routine (IRQ).
FIQ is designed to handle high-priority interrupts that require a fast response time. In
contrast, IRQ is designed to handle lower priority interrupts that do not require
immediate attention.
The need for separate FIQ and IRQ handlers arises because both types of interrupts
may occur simultaneously, and the ARM processor architecture provides only one
interrupt signal. To handle this situation, the ARM processor uses a priority-based
interrupt system where FIQ has a higher priority than IRQ.
The diagram below illustrates the ARM7 programmer model with separate FIQ and
IRQ handlers:
+---------------+
| Memory |
+---------------+
| |
| |
| |
+---------------+
| Registers |
+---------------+
| FIQ Handler |
+---------------+
| IRQ Handler |
+---------------+
| User Program |
+---------------+
+---------------+
| Memory |
+---------------+
| |
| |
| |
+---------------+
| Registers |
+---------------+
| FIQ Handler |
+---------------+
| IRQ Handler |
+---------------+
| User Program |
When an interrupt occurs, the processor first checks the FIQ signal. If it is
asserted, the processor immediately branches to the FIQ handler, which is
designed to complete quickly to minimize the delay in returning to the
interrupted program.
If the FIQ signal is not asserted, the processor checks the IRQ signal. If it is
asserted, the processor branches to the IRQ handler, which is designed to
handle lower priority interrupts that do not require immediate attention.
Both the FIQ and IRQ handlers can access the same memory and registers
as the user program, but they are separate functions with their own stack
pointers and return addresses.
In summary, the need for a fast interrupt service routine and a normal
interrupt service routine in ARM7 programmer model is to provide a
mechanism for handling high-priority interrupts that require a fast
response time separately from lower priority interrupts that do not require
immediate attention. The separate handlers help to minimize the delay in
returning to the interrupted program and ensure that the system is
responsive to both high and low priority interrupts.