VLSI Design

MODULE 2
CMOS Fabrication
◼ CMOS transistors are fabricated on silicon wafer

◼ Wafers diameters (200-300 mm)

◼ Lithography process similar to printing press

◼ On each step, different materials are deposited, or

patterned or etched

◼ Easiest to understand by viewing both top and cross-

section of wafer in a simplified manufacturing process
Inverter Cross-section
◼ Typically use p-type substrate for nMOS transistors
◼ Requires to make an n-well for body of pMOS transistors
 Inverter Top-View
→ The source of the nMOS transistor is connected to a metal ground line

→ The source of the pMOS transistor is connected to a metal VDD line.

→ The drains of the two transistors are connected with metal to form the
output Y.
Cross-section and Top- view combined
 Fabrication Steps
◼ Start with blank wafer (typically p-type where NMOS is created)
◼ Build inverter from the bottom up
◼ First step will be to form the n-well (where PMOS would reside)
◼ Cover wafer with protective layer of SiO2 (oxide)
◼ Remove oxide layer where n-well should be built
◼ Strip off SiO2
◼ Implant or diffuse n dopants into exposed wafer to form n-well

p substrate
Oxidation
◼ Grow SiO2 on top of Si wafer
◼ 900 – 1200 C with H2O or O2 in oxidation
furnace

SiO 2

p substrate
Photoresist
◼ Spin on photoresist
◼ Photoresist is a light-sensitive organic polymer
◼ Property changes where exposed to light

◼ Two types of photoresists (positive or negative)

◼ Positive resists can be removed if exposed to UV light
◼ Negative resists cannot be removed if exposed to UV light
◼ Hardens when UV light is passed through it.

Photoresist
SiO 2
_

p substrate
Lithography
◼ Expose photoresist to Ultra-violate (UV) light
through the n-well mask
◼ Strip off exposed photoresist with chemicals

Photoresist
SiO 2

p substrate
Etch
◼ Etch oxide with hydrofluoric acid (HF)
◼ Only attacks oxide where resist has been
exposed
◼ N-well pattern is transferred from the mask to
silicon-di-oxide surface.
◼ Creates an opening to the silicon surface

Photoresist
SiO 2

p substrate
Strip Photoresist
◼ Strip off remaining photoresist
◼ Use mixture of acids called piranah etch
◼ Necessary so resist doesn’t melt in next step

SiO 2

p substrate
n-well
◼ n-well is formed with diffusion or ion implantation
◼ Diffusion
◼ Place wafer in furnace with arsenic-rich gas
◼ Heat until As atoms diffuse into exposed Si

◼ Ion Implanatation
◼ Blast wafer with beam of As ions
◼ Ions blocked by SiO2, only enter exposed Si
◼ SiO2 shields (or masks) areas which remain p-type

SiO 2

n well
Strip Oxide
◼ Strip off the remaining oxide using HF
◼ Back to bare wafer with n-well
◼ Subsequent steps involve similar series of
steps

n well
p substrate
Polysilicon
(self-aligned gate technology)

◼ Deposit very thin layer of gate oxide

◼ < 20 Å (6-7 atomic layers)
◼ Chemical Vapor Deposition (CVD) of silicon
layer
◼ Place wafer in furnace with Silane gas (SiH4)
◼ Forms many small crystals called polysilicon
◼ Heavily doped to be good conductor
Polysilicon
Thin gate oxide

n well
p substrate
Polysilicon Patterning
◼ Use same lithography process discussed
earlier to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate
Self-Aligned Process
◼ Use gate-oxide/polysilicon and masking to
expose where n+ dopants should be diffused
or implanted
◼ N-diffusion forms nMOS source, drain, and n-
well contact

n well
p substrate
N-diffusion/implantation
◼ Pattern oxide and form n+ regions
◼ Self-aligned process where gate blocks n-dopants
◼ Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate
N-diffusion/implantation cont.
◼ Historically dopants were diffused
◼ Usually high energy ion-implantation used
today
◼ But n+ regions are still called diffusion

n+ n+ n+
n well
p substrate
N-diffusion cont.
◼ Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate
P-Diffusion/implantation
◼ Similar set of steps form p+ “diffusion”
regions for PMOS source and drain and
substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate
Contacts
◼ Now we need to wire together the devices
◼ Cover chip with thick field oxide (FO)
◼ Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+
n well
p substrate
 Metalization
◼ Sputter on aluminum over whole wafer
◼ Copper is used in newer technology
◼ Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate
Physical Layout Design Rules
◼ Chips are specified with set of masks
◼ Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
◼ Feature size f = distance between source and drain
◼ Set by minimum width of polysilicon wire
◼ Feature size improves 30% every 3 years or so
◼ Normalize for feature size when describing design
rules
◼ For 180nm → 0.18microns (Poly width) → 0.09um3
◼ Express rules in terms of  = f/2
◼ E.g.  = 0.3 m in 0.6 m process
Simplified Design Rules
 Simplified Design Rules
◼ Conservative rules to get you started
→ Metal and diffusion have minimum width and spacing of 4 λ

→ Contacts are 2 λ× 2 λ and must be surrounded by 1 λ on the layers

above and below.

→ Polysilicon uses a width of 2 λ.

→ Polysilicon overlaps diffusion by 2 λ where a transistor is desired and

has a spacing of 1 λ away where no transistor is desired.

→ Polysilicon and contacts have a spacing of 3 λ from other polysilicon or

contacts

→ N-well surrounds pMOS transistors by 6 λ and avoids nMOS transistors

by 6 λ.
 Inverter Layout
◼ Transistor dimensions specified as
Width / Length
◼ Minimum size is 4/ 2 Unit
transistor
◼ pMOS transistors are often wider
than nMOS transistors
◼ holes move more slowly than
electrons so the transistor has to be
wider to deliver the same current.
Gate Layouts
INVERTER
Gate Layouts
3 INPUT NAND
 Stick Diagrams
→ Designers need fast ways to plan cells and estimate area before committing
to a full layout.

→ Stick diagrams are easy to draw because they do not need to be drawn to
scale.
Stick Diagrams
Stick Diagrams
Summary
◼ MOS Transistors are stack of gate, oxide,
silicon
and p-n junctions
◼ Can be viewed as electrically controlled
switches
◼ Build logic gates out of switches
◼ Draw masks to specify layout of transistors
◼ Now you know everything necessary to start
designing schematics and layout for a simple
chip!
MOSFET SCALING EFFECTS
◼ The design of high density chips
◼ Packing density must be as high as possible.
◼ Transistor size is as small as possible.

◼ The reduction of size of MOSFET is commonly called as

scaling.

◼ Operational Characteristics will also change with the reduction

of the dimensions.

◼ Two types of Scaling size-reduction strategies

◼ Full scaling (also called constant- field scaling)
◼ Constant- voltage scaling

◼ scaling approaches will be shown to have unique effects upon

the operating characteristics of the MOS transistor.
MOSFET SCALING EFFECTS
◼ To describe device scaling, we use a constant scaling factor

S>1
◼ All the horizontal and vertical dimensions are divided by the
scaling factor.
◼
MOSFET SCALING EFFECTS
◼ This scaling option attempts to preserve the magnitude of
internal electric fields in the MOSFET.
◼ While the dimensions are scaled down by a factor of S.
◼ All potentials must be scaled down proportionally, by the same
scaling factor.
◼ Scaling also affects the threshold voltage VTO.
MOSFET SCALING EFFECTS
Full Scaling
MOSFET SCALING EFFECTS

Effects of full scaling upon key device characteristics.

MOSFET SCALING EFFECTS
Constant- Voltage Scaling
MOSFET SCALING EFFECTS
Non- Ideal IV Effects
→The non-ideal IV for MOSFET are, Effects or Short
Channel Effects
→Channel Length Modulation
→Mobility Degradation(Surface Scattering)
→Velocity Saturation
→Body Effect(Back Gate Effect)
→Leakage Current Effects
→ Sub- threshold Conduction
→ Gate Tunneling
→ Reverse Bias Diode Current(Junction leakage)
Channel Length Modulation

→ Ideally, Ids is independent of Vds for a transistor

in saturation, making the transistor a perfect current
source.

→When Vgs is kept constant, as we keep increasing

the Vds, the depletion region near to the drain
keeps increasing, which will in- turn make the
channel length decrease in length.

→Thus, when Vgs is constant, with increase in Vds,

the channel length decreases.
Non- Ideal IV Effects

Vds
Mobility Degradation(Surface Scattering)

→ Practically, the electrons travel from source to

drain in an nMOS do not follow a straight path.

→ A high voltage at the gate of the transistor attracts

the carriers to the edge of the channel, causing
collisions with the oxide interface (carriers
scattering off the silicon lattice) that slows the
carriers.

→This is called mobility degradation.

Velocity Saturation

→ At high field strength the carrier velocity ceases to

increase linearly with the increase in field strength.

→This is called velocity saturation

Body Effect(Back Gate Effect)
→ In Long Channel IV Characteristics it was assumed that the
source and the body will be shorted and connected t ground.

→ But, practically not every time the source will be connected

to the bulk or body.

→This will effect the threshold voltage of the MOSFET.

→The effect of change of threshold voltage is called the

“Body Effect” or the “Back Gate Effect”
Leakage Current Effects
→ There are certain Non- Ideal effects that result in leakage of
some undesired currents in MOSFET.

→ We can have Non- Zero values of current through the

different terminals of the MOSFET even when we ideally
expect them to be Zero.

→ These non- ideal effects are important in estimating the

power consumed or the energy efficiency of the circuit
composed of large number of transistors.
Sub- threshold Conduction
→Several sources of leakage result in current flow in
nominally OFF transistors.

→When Vgs < Vt , the current drops off exponentially

rather than abruptly becoming zero.

→This is called subthreshold conduction.

Gate Tunneling
→ In ideal case, it was assumed that the current going
from the drain is equal to the current reaching the
source.

→ As the oxide layer is an insulating material, there is

no current that can flow into the channel from the
gate terminal. This will be true for large enough
oxide thickness.

→When the size of the transistor is reduced, the oxide

layer thickness is also reduced.
Gate Tunneling
Reverse Bias Diode Current
(Junction leakage)
→ In nMOS Transistors, the source and drain are made from n-
type semiconductor and the substrate is made up of p- type
semiconductor.

→If a general biasing scheme is considered for analysis, the

source and body are connected to ground but the potential
applied at the drain terminal is positive with respect to the
body.

→The p-n junction formed by the body- drain junction is under

reverse biased.

→Still Some current flows, this is called Reverse Bias Diode

Current.
MOSFET Capacitances
◼ MOSFET capacitances reduces the speed of
operation of the Integrated Circuits.
◼ The Capacitances are classified as
◼ Lumped
◼ Distributed – Discussed further.
MOSFET Capacitances
MOSFET Capacitances
◼ The mask length (drawn length) of the gate is indicated by LM,
and the actual channel length is indicated by L.
◼ The extent of both the gate-source and the gate-drain overlap are
LD; thus, the channel length is given by
L= LM -2 LD
The source and drain overlap region lengths are usually equal to each other because of the symmetry of the
MOSFET structure.

◼ The gate electrode overlaps both the source region and the
drain region at the edges.
◼ The two overlap capacitances that arise as a result of this structural
arrangement are called CGD(overlap) and CGS(overlap),
respectively. – Both are Voltage Independent
◼ Assuming that both the source and the drain diffusion regions have
the same width W.
◼ The overlap capacitances can be found as
CGS(overlap)=Cox * W * LD
CGD(overlap)=Cox * W * LD
MOSFET Capacitances
◼ Since the channel region is connected to the
source, the drain, and the substrate
Cgs, Cgd and Cgb

◼ By observing the conditions in the channel

region during cut-off, linear, and saturation
modes the Voltage- Dependence can be
obtained.
MOSFET Capacitances
– Cut-off Mode
◼ In cut-off mode, the surface is not inverted.
◼ There is no conducting channel that links the
surface to the source and to the drain.
◼ Therefore, the gate-to-source and the gate-
to-drain capacitances are both equal to zero:
Cgs = Cgd= 0
◼ The gate-to-substrate capacitance can be
approximated by
MOSFET Capacitances
– Cut-off Mode

Representation of MOSFET oxide capacitances

MOSFET Capacitances
– Linear Mode
◼ In linear-mode operation, the inverted
channel extends across the MOSFET,
between the source and the drain.
◼ This conducting inversion layer on the
surface effectively shields the substrate from
the gate electric field; thus, Cgb = 0.
◼ In this case, the distributed gate-to-channel
capacitance may be viewed as being shared
equally between the source and the drain
MOSFET Capacitances
– Linear Mode

Representation of MOSFET oxide capacitances

MOSFET Capacitances
– Saturation Mode
◼ When the MOSFET is operating in saturation mode,
the inversion layer on the surface does not extend to
the drain, but it is pinched off.
◼ The gate-to-drain capacitance component is
therefore equal to zero (Cgd = 0) .
◼ Since the source is still linked to the conducting
channel, its shielding effect also forces the gate-to-
substrate capacitance to be zero, Cgb = 0.
◼ Finally, the distributed gate-to-channel capacitance
as seen between the gate and the source can be
approximated by
MOSFET Capacitances
– Saturation Mode

Representation of MOSFET oxide capacitances