LCD DRIVER

Data Sheet

AX6963
Dot Matrix LCD CONTROL LSI

AsLic Microelectronics Corporation 2003 Apr 09

LCD Controller Version: 3.0

This data sheet is subject to change

without notice. Please contact AsLic
for the latest version of this document.
ASLIC AX6963

DOT MATRIX LCD CONTROL LSI

The AX6963 is an LCD controller designed to be used with LCD control driver LSIs and data display
memories. The device has an 8-bit parallel data bus and control lines for reading or writing through an
MPU interface.It can be directly connected to a TMPZ-80.
It has a 128-word character generator ROM which can control an external display RAM of up to 64
Kbytes.Allocation of text, graphics and external character generator RAM can be made easily and the
display window can be moved freely within the allocated memory range.
The device supports a very broad range of LCD formats by allowing selection of different combinations
via a set of programmable inputs.It can be used in text, graphic and combination text-and-graphic modes,
and includes various attribute functions.

FEATURES
iDisplay format (pin-selectable)
Columns : 32, 40, 64, 80
Lines : 2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32
The combination of number of columns and number of lines must not cause the frequency to
exceed 6 MHz. (See Fig.2)
iCharacter font (pin-selectable)
Horizontal dots : 5, 6, 7, 8
Vertical dots : 8 (fixed)
It is necessary to set a character font in Graphic mode just as in Text mode.The oscillation fre-
quency does not change with the font selection.
iDisplay duty : 1/16 to 1/128
iA 128-word character generator ROM (code 0101) AX6963-0101 is built in as standard.
iExternal display memory : 64 KB Max
The addresses in display memory of the text area, graphic area and external character generator
area are determined by software.
iRead or Write operations from the CPU do not disturb the display.

iA crystal oscillator circuit is built in. The oscillation frequency is adjusted according to the
display size.If using an external clock, use the XI pin as the clock input. (XO open.)
External capacitors Crystal oscillation : 20 to 30 pF
Ceramic oscillation : 30 to 100 pF
Built-in feedback resistor : 900 k (typ.)
iExternal display RAM must be static RAM. The AX6963 cannot refresh D-RAM.
iThe attribute functions can only be used in Text mode.They cannot be used in Graphic or
Combination character mode.

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BLOCK DIAGRAM

CDATA, LP, FR, HSCP, LSCP ED, HOD, LOD ad0 to ad15 (TO SRAM) d0 to d7 (TO / FROM SRAM)

LCD TIMING LCD DATA TEXT GRAPHIC ADDRESS CG RAM RAM DATA RAM DATA
GENERATOR CONTROL POINT POINT POINT POINT BUFFER LATCH

SERIALIZER

GRAPHIC ADDRESS
DATA LATCH CONTROL

DISPLAY
SELECTOR
CG ROM CHARACTER CODE
LATCH
TEXT
DATA LATCH

CURSOR
CONTROL

COPY CONTROL

COMMAND DEFINITIONS CURSOR

POINT
TIMING CONTROL

INSTRUCTION
STATUS INTERNAL DATA LATCH
DECODE

STATUS DATA INSTRUCTION DATA

DATA & INSTRUCTION Control
BUFFER BUFFER LATCH LATCH

WR RD CE C/D
D0 to D7 (TO / FROM CPU )

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PIN ASSIGNMENT

DUAL
HSCP

HOD

ad15
ad14
ad13
ad12
ad11
ad10
ad9
ad8
ad7
ad6
ad5
ad4
ad3
ad2
ad1
ce1
ce0

ad0
ED
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
LP 55
CDATA 56
FR 57 32 ce
CH1 58 31 r/w
CH2 59 30 d7
DSOPN 60 29 d6
VDD 61 AX6963 d5
28
SDSEL 62 27 VDD
VSS 63 26 d4
T2 64 25 d3
T1 65 24 d2
XI 66 23 d1
XO 67 22 d0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
FS0

WR
HALT
RESET

CE
MDS

RD

C/D
MD0
MD1
MD2
MD3

FS1

D1
D0

D2
D3
D4
D5
D6
D7
PIN FUNCTIONS
PIN NAME I/O FUNCTIONS

Pins for selection of LCD size

DUAL H H H H H H H H L L L L L L L L
MDS L L L L H H H H L L L L H H H H
MDS MD1 H H L L H H L L H H L L H H L L
MD0 Input
MD1 MD0 H L H L H L H L H L H L H L H L
LINES 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
V-DOTS 16 32 48 64 80 96 112 128 32 64 96 128 160 192 224 256
1 SCREEN 2 SCREENS

MD2 H L H L
MD2 Input Pins for selection of number of columns MD3 H H L L
MD3
Columns 32 40 64 80

FS0 H L H L
FS0 FS1 H H L L
Input Pins for selection of font
FS1
Font 5*8 6*8 7*8 8*8

D0 to D7 I/O Data I/O pins between CPU and AX6963 (D7 is MSB)

WR Input Data Write.Write data into AX6963 when WR=L.

RD Input Data Read.Read data from AX6963 when RD=L.

CE Input Chip Enable for AX6963.CE must be L when CPU communicates with AX6963.

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PIN NAME I/O FUNCTIONS

C/D Input WR=L ...... C/D = H : Command Write C/D=L : Data Write
RD =L ...... C/D = H : Status Read C/D=L : Data Read

HALT Input H ...... Normal, L ...... Stops the oscillation of the clock

H ...... Normal (AX6963 has internal pull-up resistor)

RESET Input
L ...... Initialize AX6963.Text and graphic have addresses and text and graphic

Control pin for external DC/DC.DSPON is L when HALT is L or RESET is L.

DSPON Output
(When DSPON goes H,the column drivers are cleared.)

H ...... Single-Scan DUAL H H L L

DUAL Input
L ...... Dual-Scan
SDSEL H L H L

H ...... Sending data by odd/even separation

L ...... Sending data by simple serial method
SDSEL Input Upper screen HOD, ED ED HOD, ED ED
Lower screen _ _ LOD, ED ED

ce0 ce0 at DUAL=H Chip enable pin for display memory in the address range 0000h to
Output 07FFH
(LOD) LOD at DUAL=L Serial data output for odd columns in lower area of LCD

ce1 ce1 at DUAL=H Chip enable pin for display memory in the address range 0800h to
Output 0FFFH
(LSCP) LSCP at DUAL=L Shift clock pulse output for column drivers in lower area of LCD

ce Output Chip enable pin for display memory of any address

d0 to d7 I/O Data I/O pins for display memory

Address outputs for display memory

ad0 to ad15 Output
(ad15=L : for upper area of LCD, ad15=H : for lower area of LCD)

R/W Output Read/Write signal for display memory

SDSEL=H : Data output for even columns in both upper and lower areas of LCD
ED Output
SDSEL=L : Date output for columns in both upper and lower areas of LCD
HOD Output Date output for odd columns in upper area of LCD

CDATA Output Synchronous signal for row driver

HSCP Output Shift clock pulse for column driver of upper area of LCD

LP Output Latch pulse for column driver.Shift clock pulse for row driver

FR Output Frame signal

XI Input Crystal oscillator input

XO Output Crystal oscillator output

CH1, CH2 Output Check signal

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T1, T2 Input Test input.Usually open

VDD _ Power supply (5.0V)

VSS _ Power supply (0V)

FUNCTIONAL DEFINITION
iAfter power on, it is necessary to reset. RESET is kept L between 5 clocks up (oscillation clock).
iWhen HALT =L, the oscillation stops.The power supply for the LCD must now be turned off, to protect
the LCD from DC bias.
iThe HALT function includes the RESET function.
iThe column/line counter and display register are cleared by RESET.(Other registers are not cleared.)
Disable the display using the clear-display register.
iThe status must be checked before data or commands are sent. The MSB=0 status check must be done in
particular. There is a possibility of erroneous operation due to a hard interrupt.
iSTA0 and STA1 must be checked at the same time. When a command is executed, data transmission
errors may occur.
iThe AX6963 can only handle one byte per machine cycle (16 clocks).It is impossible to send more than
two data in a machine cycle.
iWhen using a command with operand data, it important to send the data first, and then execute the
command.
iThe character codes used by the AX6963 are different from ASCII codes.

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iState after RESET/HALT (Fig.1)

TERMINAL HALT RESET

D0 toD7 F F

do to d7 F F

r/w H H

ce H (Note1) H (Note1)

ad0 to ad15 H (Note2) H (Note2)

ce0, ce1 H (Note1) H (Note1)

ED, HOD Final data Final data

HSCP L L

LP L L

CDATA H H

FR H H

CH1 L K0

CH2 L VEND

DSPON L L

XO H OSC clock

H : Level H
L : Level L
F : Floating (high impedance)
K0 : Test signal
VEND : Test signal
(Note 1) : In Attribute mode, H or L according to state of graphic pointer
(Note 2) : In Attribute mode, data of graphic pointer

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iThe relationship between number of row / column and oscillation clock (Fig.2)
The frequency of the crystal oscillator is adjusted by the following formula.
fOSC : Frequency of oscillation
fSCP : Frequency of shift clock (fSCP = fOSC/2)
fR : Frequency of Frame
M : Number of characters on one line (number of dots on one line = 8M)
For all font sizes (e.g. 7*8, 6*8, 5*8) the oscillation frequency remains constant.
N : Number of rows (duty = 1/8N)
8M 1
--------- × 8N = ----
fscp fR
-

fOSC = fR*64*2*M*N
(fR = 60Hz)
Unit : [MHz]

N M 32 40 64 80 Duty

0.492 0.614 0.983 1.229

2 0.983 1.229 1.966 2.458 1/16

0.983 1.229 1.966 2.458
4 1/32
1.966 2.458 3.932 4.915

1.475 1.843 2.949 3.686

6 1/48
2.949 3.686 5.898 7.372

1.966 2.458 3.932 4.915

8 1/64
3.932 4.915 7.864 9.830

2.458 3.072 4.915 6.144

10 1/80
4.915 6.144 9.830 12.288

2.949 3.686 5.898 7.373

12 1/96
5.898 7.373 11.776 14.746

3.440 4.300 6.881 8.602

14 1/112
6.881 8.601 13.763 17.203

3.932 4.915 7.864 9.830

16 1/128
7.864 9.830 15.729 19.660

(Note 1) : Upper ... Single-Scan, lower ... Dual-Scan at fR = 60Hz Upper

Lower

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iRAM Interface
The external RAM is used to store display data (text, graphic and external CG data).
With single-scan,text data, graphic data and external CG data can be freely allocated to the memory area
(64 KB max).
With dual-scan, LCD I is allocated to 0000H to 7FFFH (32 KB max) , LCD II is allocated to 8000H to
FFFFH (32 KB max).Text data,graphic data and external CG date can be freely allocated in LCD I.In
LCD II, the same addresses must be allocated as in LCD I, except ad15.ad15 determines selection of
LCD I or LCD II.
It can be use the address decoded signals ce0 (0000 to 07FFH), ce1 (0800 to0FFFH) within 4 KB.
ce0 and ce1 allow decoding of addresses in the ranges (0000 to 07FFH) and (0800 to 0FFFH)
respectively within a 4-KB memory space.

(Example)
(1) Single-Scan (2) Dual-Scan

0000H 0000H TEXT 8000H

TEXT
TEXT AREA AREA
3FFFH BFFFH
AREA GRAPHIC GRAPHIC
7FFFH AREA AREA
77FFH F7FFH
GRAPHIC CG RAM CG RAM
7FFFH AREA FFFFH AREA
AREA
F7FFH
CG RAM
CG : Character Generator
FFFFH AREA

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iFlowchart of communications with MPU

A status check must be performed before data is read or written.
Status check
The Status of AX6963 can be read from the data lines.
RD L
WR H
CE L
C/D H
D0 to D7 Status word
(1) Status Read
The AX6963 status word format is as follows:

MSB LSB
STA7 STA6 STA5 STA4 STA3 STA2 STA1 STA0
D7 D6 D5 D4 D3 D2 D1 D0

0 : Disable
STA0 Check command execution capability 1 : enable
0 : Disable
STA1 Check data read / write capability 1 : enable
STA2 Check Auto mode data read capability 0 : Disable
1 : enable
0 : Disable
STA3 Check Auto mode data write capability 1 : enable
STA4 Not used

STA5 Check controller operation capability 0 : Disable

1 : enable
0 : No error
STA6 Error flag.Used for Screen Peek and Screen copy commands 1 : error
STA7 Check the blink condition 0 : Display off
1 : Normal display

(Note 1) : It is necessary to check STA0 and STA1 at the same time.

. There is a possibility of erroneous operation due to a hardware interrupt.
(Note 2) : For most modes STA0/STA1 are used as a status check
(Note 3) : STA2 and STA3 are valid in Auto mode; STA0 and STA1 are invalid.

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Status checking flow

a) b)
STATUS AUTO MODE STATUS

(*1)
STA2=1 (Read)
or
STA0=1 (*1)
NO STA3=1 (Write)
STA1=1 NO

YES YES

RETURN RETURN

(Note 4) : When using the MSB=0 command, a Status Read must be performed.
If a status check is not carried out, the AX6963 cannot operate normally, even after a delay time.
The hardware interrupt occurs during the address calculation period (at the end of each line).
If a MSB=0 command is sent to the AX6963 during this period, the AX6963 enters wait status.
If a status check is not carried out in this state before the next command is sent, there is the
possibility that the command or data will not be received.

(2) Setting data

When using the AX6963, first set the data,then set the command.
Procedure for sending a command
a)The case of 1 data b)The case of 2 data

Send Command Send Command

Status check STA0, 1 Status check STA0, 1

Data write Data write

Status check Status check

Command write Date write

END Status check

Command write

END

(Note) : When sending more than two data,the last datum (or last two data ) is valid.
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FUNCTIONAL DEFINITION
COMMAND CODE D1 D2 FUNCTION

00100001 X address Y address Set Cursor Pointer

REGISTERS SETTING 00100010 Data 00H Set Offset Register
00100100 Low address High address Set Address Pointer
01000000 Low address High address Set Text Home Address
01000001 Columns 00H Set Text Area
SET CONTROL WORD
01000010 Low address High address Set Graphic Home Address
01000011 Columns 00H Set Graphic Area
1000*000 - - OR mode
1000*001 - - EXOR mode
MODE SET 1000*011 - - AND mode
1000*100 - - Text Attribute mode
10000*** - - Internal CG ROM mode
10001*** - - External CG RAM mode

10010000 - - Display off

1001**10 - - Cusor on, blink off
1001**11 - - Cursor on, blink on
DISPLAY MODE
100101** - - Text on, graphic off
100110** - - Text off, graphic on
100111** - - Text on, graphic on
10100000 - - 1-line cursor
10100001 - - 2-line cursor
10100010 - - 3-line cursor
CURSOR PATTERN 10100011 - - 4-line cursor
SELECT 10100100 - - 5-line cursor
10100101 - - 6-line cursor
10100110 - - 7-line cursor
10100111 - - 8-line cursor

DATA AUTO READ/ 10110000 - - Set Data Auto Write

WRITE 10110001 - - Set Data Auto Read
10110010 - - Auto Reset
11000000 Data - Data Write and Increment ADP
11000001 - - Data Read and Increment ADP
DATA READ/WRITE 11000010 Data - Data Write and Decrement ADP
11000011 - - Data Read and Decrement ADP
11000100 Data - Data Write and Nonvariable ADP
11000101 - - Data Read and Nonvariable ADP
SCREEN PEEK 11100000 - - Screen Peek

SCREEN COPY 11101000 Screen Copy

11110*** - - Bit Reset
11111*** - - Bit Set
1111*000 - - Bit 0 (LSB)
1111*001 - - Bit 1
1111*010 - - Bit 2
BIT SET/RESET 1111*011 - - Bit 3
1111*100 - - Bit 4
1111*101 - - Bit 5
1111*110 - - Bit 6
1111*111 - - Bit 7 (MSB)

* : invalid

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iSetting registers
CODE HEX. FUNCTION D1 D2

00100001 21H SET CURSOR POINTER X ADRS Y ADRS

00100010 22H SET OFFSET REGISTER DATA 00H

00100100 24H SET ADDRESS POINTER LOW ADRS HIGH ADRS

(1) Set Cursor Pointer

The position of the cursor is specified by X ADRS and Y ADRS. The cursor position can only be
moved by this command. Data read/ write from the MPU never changes the cursor pointer.X ADRS
and Y ADRS are specified as follows.
X ADRS 00H to 4FH (lower 7 bits are valid)
Y ADRS 00H to 1FH (lower 5 bits are valid)

a)Single-Scan b)Dual-Scan
X ADRS 00 to 4 FH X ADRS 00H to 4 FH

Y ADRS 00H to 0FH

Y ADRS 00H to 0FH Upper screen

Y ADRS 10H to 1FH

Lower screen

(2) Set Offset Register

The offset register is used to determine the external character generator RAM area.
The AX6963 has a 16-bit address bus as follows:

MSB LSB
ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0

Offset Register Data Character Code Line Scan

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AX6963 assign External character generator, when character code set 80H to FFH in using inernal charac
ter generator. Character code 00H to 80H assign External character generator, when External generator
mode.
The senior five bits define the start address in external memory of the CG RAM area. The next eight bits
represent the character code of the character. In internal CG ROM mode, character codes 00H to 7 FH rep
resent the predefined internal CG ROM characters, and codes 80H to FFH represent the user,s own
external characters. In external CG RAM mode,all 256 codes from 00H to FFH can be used to repre
sent the user,s own characters.The three least significant bits indicate one of the eight rows of eight dots
that define the character,s shape.
The relationship between display RAM address and offset register
Offset register data CG RAM hex.address (start to end)
00000 0000 to 07FFH
00001 0800 to 0FFFH
00010 1000 to 17FFH

11100 E000 to E7FFH

11101 E800 to EFFFH
11110 F000 to F7FFH
11111 F800 to FFFFH

(Example 1)
Offset register 02H
Character code 80H
Character generator RAM start address 0001 0100 0000 0000
1 4 0 0 H
(address) (data)
1400H 00H
1401H 0EH
1402H 11H
1403H 11H
1404H 1FH
1405H 11H
1406H 11H
1407H 00H

(Example 2) The relationship between display RAM data and display characters.

(RAM DATA) (Character)

ABγDEζGHIJKLM 21H A
22H B
_ _ _ _ _

83H γ
24H D
25H E
86H ζ
Display character

γ and ζ are displayed by character generator RAM.

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(3) Set Address Pointer

The Set Address Pointer command is used to indicate the start address for writing to (or reading from)
external RAM.

The Flowchart for Set Address Pointer command

Set Address Pointer

Status check STA0, 1

Set Address data

(lower 8 bits)

Status check

Set Address data

(upper 8 bits)

Status check

Send command 24H Send Set Address Pointer command

END

iSet Control Word

CODE HEX. FUNCTION D1 D2

01000000 40H Set Text Home Address Low address High address

01000001 41H Set Text Area Columns 00H

01000010 42H Set Graphic Home Address Low address High address

01000011 43H Set Graphic Area Columns 00H

The home address and column size are defined by this command.

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(1) Set Text Home Address

The starting address in the external dislay RAM for text display is defined by this command.The text
home address indicates the leftmost and uppermost position.
The relationship between external display RAM address and display position
TH TH+CL
TH+TA TH+TA+CL
(TH+TA)+TA TH+2TA+CL
(TH+2TA)+TA TH+3TA+CL

TH+(n-1)TA TH+(n-1)TA+CL

TH : Text home address

TA : Text area number (columns)
CL : Columns are fixed by hardware (pin-programmable)

(Example)
Text home address : 0000H
Text area : 0020H
MD2 = H, MD3 = H : 32columns
DUAL = H, MDS = L, MD0 = L, MD1 = H : 4 lines

0000H 0001H 001EH 001FH

0020H 0021H 003EH 002FH
0040H 0041H 005EH 005FH
0060H 0061H 007EH 007FH

(2) Set Graphic Home Address

The starting address of the external display RAM used for graphic display is defined by this command.
The graphic home address indicates the leftmost and uppermost position.
The relationship between external display RAM address and display position.

GH GH+CL
GH+GA GH+GA+CL
(GH+GA)+GA GH+2GA+CL
(GH+2GA)+GA GH+3GA+CL

GH+(n-1)GA GH+(n-1)GA+CL

GH : Graphic home address

GA : Graphic area number (columns)
CL : Columns are fixed by hardware (pin-programmable)

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(Example)
Graphic home address : 0000H
Graphic area : 0020H
MD2 = H, MD3 = H : 32columns
DUAL = H, MDS = L, MD0 = H, MD1 = H : 2 lines

0000H 0001H 001EH 001FH

0020H 0021H 003EH 003FH
0040H 0041H 005EH 005FH
0060H 0061H 007EH 007FH
0080H 0081H 009EH 009FH
00A0H 00A1H 00BEH 00BFH
00C0H 00C1H 00DEH 00DFH
00E0H 00E1H 00FEH 00FFH
0100H 0101H 011EH 011FH
0120H 0121H 013EH 013FH
0140H 0141H 015EH 015FH
0160H 0161H 017EH 017FH
0180H 0181H 019EH 019FH
01A0H 01A1H 01BEH 01BFH
01C0H 01C1H 01DEH 01DFH
01E0H 01E1H 01FEH 01FFH

(3) Set Text Area

The display columns are defined by the hardware setting. This command can be used to adjust the
columns of the display.
(Example)
LCD size : 20 columns, 4 lines
Text home address : 0000H
Text area : 0014H
MD2 = H, MD3 = H : 32 columns
DUAL = H, MDS = L, MD0 = L, MD1 = H : 4 lins

0000 0001 ......... 0013 0014 ......... 001F

0014 0015 ......... 0027 0028 ......... 0033
0028 0029 ......... 003B 003C ......... 0047
003C 003D ......... 004F 0050 ......... 005B

LCD

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(4)Set Graphic Area

The display columns are defined by the hardware setting. This command can be used to adjust the
columns of the graphic display.
(Example)
LCD size : 20 columns, 2 lines
Graphic home address : 0000H
Graphic area : 0014H
MD2 = H, MD3 = H : 32 columns
DUAL = H, MDS = L, MD0 = H, MD1 = H : 2 lines

0000 0001 ......... 0013 0014 ......... 001F

0014 0015 ......... 0027 0028 ......... 0033
0028 0029 ......... 003B 003C ......... 0047
003C 003D ......... 004F 0050 ......... 005B
0050 0051 ......... 0063 0064 ......... 006F
0064 0065 ......... 0077 0078 ......... 0083
0078 0079 ......... 008B 008C ......... 0097
008C 008D ......... 009F 00A0 ......... 00AB
00A0 00A1 ......... 00B3 00B4 ......... 00BF
00B4 00B5 ......... 00C7 00C8 ......... 00D3
00C8 00C9 ......... 00DB 00DC ......... 00E7
00DC 00DD ......... 00EF 00F0 ......... 00FD
00F0 00F1 ......... 0103 0104 ......... 011F
0104 0105 ......... 0127 0128 ......... 0123
0128 0129 ......... 013B 013C ......... 0147
013C 013D ......... 014F 0150 ......... 015B

LCD

If the graphic area setting is set to match the desired number of columns on the LCD, the addressing
scheme will be automatically modified so that the start address of each line equals the end address of
the previous line +1.

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i Mode set
CODE FUNCTION OPERAND
1000*000 OR Mode _
1000*001 EXOR Mode _
1000*011 AND Mode _
1000*100 TEXT ATTRIBUTE Mode _
10000*** Internal Character Generator Mode _
10001*** External Character Generator Mode _ * : invalid

The display mode is defined by this command.The display mode does not change until the next
command is sent. The logical OR, EXOR, AND of text or graphic display can be displayed.
In Internal Character Generator mode, character codes 00H to 7FH are assigned to the built-in character
generator ROM.The character codes 80H to FFH are automatically assigned to the external character
generator RAM.

(Example)

GRAPHIC TEXT

"OR" "AND" "EXOR"

(Note) : Attribute functions can only be applied to text display, since the attribute data is placed in the
graphic RAM area.

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Attribute function
The attribute operations are Reverse display, Character blink and Inhibit. The attribute data is written
into the graphic area which was defined by the Set Control Word command. Only text display is
possible in Attribute Function mode; graphic display is automatically disabled. However, the Display
Mode command must be used to turn both Text and Graphic on in order for the Attribute function to
be available.
The attribute data for each character in the text area is written to the same address in the graphic area.
The Attribute function is defined as follows.

Attribute RAM 1byte * * * * d3 d2 d1 d0

d3 d2 d1 d0 FUNCTION
0 0 0 0 Normal display
0 1 0 1 Reverse display
0 0 1 1 Inhibit display
1 0 0 0 Blink of normal display
1 1 0 1 Blink of reverse display
1 0 1 1 Blink of inhibit display * : invalid

iDisplay mode
CODE FUNCTION OPERAND
10010000 Display off -
1001**10 Cursor on, blink off -
1001**11 Cursor on, blink off -
100101** Text on, graphic off -
100110** Text off, graphic on -
100111** Text on, graphic on - * : invalid

1 0 0 1 D3 D2 D1 D0

Cursor blink on : 1, off : 0

Cursor display on : 1, off : 0
Text display on : 1, off : 0
Graphic display on : 1, off : 0

(Note) : It is necessary to turn on "Text dispaly" and "Graphic display" in the following cases.
a) Combination of text / graphic display
b) Attribute function

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ASLIC AX6963

iCursor pattern select

CODE FUNCTION OPERAND
10100000 1-line cursor _
10100001 2-line cursor _
10100010 3-line cursor _
10100011 4-line cursor _
10100100 5-line cursor _
10100101 6-line cursor _
10100110 7-line cursor _
10100111 8-line cursor _

When cursor display is ON, this command selects the cursor pattern in the range 1 line to 8 lines.
The cursor address is defined by the Cursor Pointer Set command.

1-line cursor 2-line cursor 8-line cursor

iData Auto Read/Write

CODE HEX. FUNCTION OPERAND
10110000 B0H Set Data Auto Write _
10110001 B1H Set Data Auto Read _
10110010 B2H Auto Reset _

This command is convenient for sending a full screen of data from the external display RAM.After
setting Auto mode, a Data Write (or Read) command is need not be sent between each datum.A Data
Auto Write (or Read) command must be sent after a Set Address Pointer command.After this command,
the address pointer is automatically incremented by 1 after each datum. In auto mode, the AX6963
cannot accept any other commands.
The Auto Reset command must be sent to the AX6963 after all data has been sent, to clear Auto mode.

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(Note) : A Status check for Auto mode

(STA2, STA3 should be checked between sending of each datum. Auto Reset should be
performed after checking STA3=1 (STA2=1).Refer to the following flowchart.

a) Auto Read mode b) Auto Write mode

Auto read start Auto write start

Set Address Pointer Set Address Pointer

Status check 1 Status check 1 STA0, 1

STA0, 1

Auto read B1H Auto write B0H

Status check 2 STA2 Status check 2 STA3

Data read Data write

Status check 2 Status check 2

Repetition Repetition
Data read Data write

Status check 2 Status check 2

Auto reset B2H Auto reset B2H

END END

Set Address Pointer

Status check 1 Status check 2

Status check 1 STA0, 1

Set Address data NO NO STA2=1,

STA0=1,
(lower 8 bits) (STA3=1)?
STA1=1?

Status check 1
YES YES

Set Address data RETURN RETURN

(upper 8 bits)

Status check 1

Set Address Pointer Send Set Address Pointer command

END

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iData Read/Write
CODE HEX. FUNCTION OPERAND
11000000 C0H Data Write and Increment ADP Data
11000001 C1H Data Read and Increment ADP _
11000010 C2H Data Write and Decrement ADP Data
11000011 C3H Data Read and Decrement ADP _
11000100 C4H Data Write and Nonvariable ADP Data
11000101 C5H Data Read and Nonvariable ADP _

This command is used for writing data from the MPU to external display RAM, and reading data from
external display RAM to the MPU.Data Write/Data Read should be executed after setting address using
Set Address Pointer command. The address pointer can be automatically incremented or decremented
using this command.
(Note) : This command is necessary for each 1-byte datum.
Refer to the following flowchart.

Data write start

(Example)
Set Address Pointer Address pointer = 1000H

Status check 1 STA0, 1

(Example)
Set write data
Data = AAH

Status check 1

Data write C0H AAH is written in 1000H address.

Address pointer is 1001H

END

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iScreen Peek
CODE HEX. FUNCTION OPERAND
11100000 E0H Screen Peek -

This command is used to transfer 1 byte of displayed data to the data stack;this byte can then be read from
the MPU by data access.The logical combination of text and graphic display data on the LCD screen can
be read by this command.
The status (STA6) should be checked just after the Screen Peek command.If the address determined by
the Set Address Pointer command is not in the graphic area, this command is ignored and a status
flag (STA6) is set.
Refer to the following flowchart.

Screen peek start

Set Address Pointer

Status check 1 STA0, 1

Screen peek E0H

No
(*) (*) Status check STA6 = 0?

Yes
Status check 1

Data access

END

(Note) : This command is available when hardware column number and software column mumber are the
same.
Hardware column number is related to MD2 and MD3 setting.
Software column number is related to Set Text Area and Set Graphic Area command.
The data read command must be performed after screen peek command.

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iScreen Copy

CODE HEX. FUNCTION OPERAND

11101000 E8H Screen Copy -

This command copies a single raster line of data to the graphic area.
The start point must be set using the Set Address Pointer command.
(Note 1) : If the attribute function is being used, this command is not available.
(With Attribute data is graphic area data.)
(Note 2) : With Dual-Scan, this command cannot be used (because the AX6963 cannot separate the
upper screen data and lower screen data).
Refer to the following flowchart.

Screen copy start

Set Address Pointer

Status check 1 STA0, 1

Screen copy E8H

YES
(*1) (*1) Status check STA6 = 1
NO (*2) Status check STA0/1 = 1
NO
(*2)
YES
END

(Note) : This command is available when hardware column number and software column number are
the same.
Hardware column number is related to MD2 and MD3 setting.
Software column number is related to Set Text Area and Set Graphic Area command.

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iBit Set / Reset

CODE FUNCTION OPERAND

11110*** Bit Reset -
11111*** Bit Set -
1111*000 Bit 0 (LSB) -
1111*001 Bit 1 -
1111*010 Bit 2 -
1111*011 Bit 3 -
1111*100 Bit 4 -
1111*101 Bit 5 -
1111*110 Bit 6 -
1111*111 Bit 7 (MSB) - * : invalid

This command use to set or reset a bit of the byte specified by the address pointer.Only one bit
can be set/ reset at a time.
Refer to the following flowchart.

Bit Set/Reset

Set Address pointer

Status check 1 STA0, 1

Set write date

Status check 1

Bit set (reset)

END

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 ASLIC

Version 3.0
Character Code Map
The relation between character codes and character pattern (CG ROM TYPE 0101)
LSB
0 1 2 3 4 5 6 7 8 9 A B C D E F
MSB

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3

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AX6963
 ASLIC

Character Code Map

The relation between character codes and character pattern (CG ROM TYPE 0201)
LSB
0 1 2 3 4 5 6 7 8 9 A B C D E F
MSB

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AX6963
ASLIC AX6963

Absolute Maximum Ratings (Ta=25 )

ITEM SYMBOL RATING UNIT

Supply Voltage VDD (Note) -0.3 to 7.0 V

Input Voltage VIN (Note) -0.3 to VDD+0.3 V

Operating Temperature Topr -20 to 70

Storage Temperature Tstg -55 to 125

(Note) : Refernced to VSS = 0V.

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
TEST CONDITIONS (Unless otherwise noted, VSS = 0V, VDD = 5.0 10%, Ta = -20 to 75 )
Test
Item Symbol Cir- Test Condition Min Typ. Max Unit Pin Name
cuit

Operating Voltage VDD _ _ 3.0 5.0 5.5 V V DD

H Level VIH _ 0.8VDD _ VDD V Input pins

Input _
L Level VIL _ 0 _ 0.8 V Input pins

H Level VOH _ VDD - 0.4 _ VDD V Output pins

Output _
Voltage
L Leval VOL _ 0 _ 0.3 V Output pins

H Level ROH VOUT = VDD - 0.5V _ _ 300 Output pins

Output
Resistance
L Level ROL VOUT = 0.5V _ _ 300 Output pins

Input Pull-up
RPU _ _ 50 100 200 k (Note 1)
Resistance

Operating Frequency fOSC _ _ 0.4 _ 12 MHz

Current Consumption VDD = 5.0V (Note 2)

IDD(1) _ _ 3.3 6 mA VDD
(Operating) fOSC = 3.0MHz

Current Consumption
IDD(2) _ VDD = 5.0V _ _ 3 A VDD
(Halt)

(Note 1) : Applied T1, T2, RESET

(Note 2) : MDS=L, MD0=L, MD1=L, MD2=H, MD3=H, FS0=L, FS1=L, SDSEL=L, DUAL=H,
D7 to D0 = LHLHLHLH

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Ac Characteristics
iSwitching Characteristics (1)

tCWH

SCP
tr tf tCWH tDHD
tLHD tDSU

tLSU
LP

DATA
td

FR

CDATA tCSU tCHD

Test Conditions(Unless Otherwise Noted,VDD =5.0 10%,Vss =0V,Ta=-20 to 75 )

Item Symbol Test Conditions Min Max Unit
Operating Frequency fSCP Ta = -10~70 _ 3 MHz
SCP Pulse Width tCWH, tCWL _ 150 _ ns
SCP Rise/Fall Time tr , t f _ _ 25 ns
LP Set-up Time tLSU _ 160 290 ns
LP Hold Time tLHD _ 5 40 ns
Data Set-up Time tDSU _ 220 _ ns
Data Hold Time tDHD _ 80 _ ns
FR Delay Time td _ 0 50 ns
CDATA Hikd Time tCSU _ 500 850 ns
CDATA Hold Time tCHD _ 450 950 ns

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Test Conditions(Unless Otherwise Noted,VDD =3.0,Vss =0V,Ta=-20 to 75 )

Item Symbol Test Conditions Min Max Unit
Operating Frequency fSCP Ta = -10~70 _ 3 MHz
SCP Pulse Width tCWH, tCWL _ 150 _ ns
SCP Rise/Fall Time t r, t f _ _ 25 ns
LP Set-up Time tLSU _ 180 330 ns
LP Hold Time tLHD _ 6 60 ns
Data Set-up Time tDSU _ 230 _ ns
Data Hold Time tDHD _ 90 _ ns
FR Delay Time td _ 0 70 ns
CDATA Set-up Time tCSU _ 520 850 ns
CDATA Hold Time tCHD _ 470 950 ns

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ASLIC AX6963

iSwitching Characteristics (2)

Bus Timing

C/D
tCDS tCDH

CE

tCE, tRD, tWR

RD, WR

tDS

D0 to D7
(WRITE)
tDH

D0 to D7
(READ)
tACC tOH

Test Conditions(Unless Otherwise Noted,VDD =5.0 10%,Vss =0V,Ta=-20 to 75 )

Item Symbol Test Conditions Min Max Unit
C/D Set-up Time tCDS _ 100 _ ns
C/DHold Time tCDH _ 10 _ ns
CE, RD, WR Pulse Width tCE, tRD, tWR _ 80 _ ns
Data Set-up Time tDS _ 80 _ ns
Data Hold Time tDH _ 40 _ ns
Access Time tACC _ _ 150 ns
Output Hold Time tOH _ 10 50 ns

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Test Conditions(Unless Otherwise Noted,VDD =3.0,Vss =0V,Ta=-20 to 75 )

Item Symbol Test Conditions Min Max Unit
C/D Set-up Time tCDS _ 150 _ ns
C/DHold Time tCDH _ 20 _ ns
CE, RD, WR Pulse Width tCE, tRD, tWR _ 100 _ ns
Data Set-up Time tDS _ 100 _ ns
Data Hold Time tDH _ 50 _ ns
Access Time tACC _ _ 250 ns
Output Hold Time tOH _ 20 80 ns

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iSwitching Characteristics (3)

(1) External RAM Read mode

CLOCK (XI)

ad0 to ad15
td1 td1

ce
td2
td3
r/w

d0 to d7

tDS tDH

(2) External RAM Write mode

CLOCK (XI)

ad0 to ad15
td1 td1
ce

td4 td5
r/w
td6
td7

d0 to d7
td8
td9

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Item Symbol Test Conditions Min Max Unit

Address Delay time td1 _ _ 250 ns

ce Fall Delay Time (Read) td2 _ _ 180 ns

ce Rise Delay Time (Read) td3 _ _ 180 ns

Data Set-up Time tDS _ 0 _ ns

Data Hold Time tDH _ 30 _ ns

ce Fall Delay Time (Write) td4 _ _ 200 ns

ce Rise Delay Time (Write) td5 _ _ 200 ns

r/w Fall Delay Time td6 _ _ 180 ns

r/w Rise Delay Time td7 _ _ 180 ns

Data Stable Time td8 _ _ 450 ns

Data Hold Time td9 _ _ 200 ns

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Test Conditions (Unless Otherwise Noted, VDD = 3.0, VSS = 0V, Ta = -20 to 70 )
Item Symbol Test Conditions Min Max Unit

Address Delay time td1 _ _ 300 ns

ce Fall Delay Time (Read) td2 _ _ 200 ns

ce Rise Delay Time (Read) td3 _ _ 200 ns

Data Set-up Time tDS _ 0 _ ns

Data Hold Time tDH _ 30 _ ns

ce Fall Delay Time (Write) td4 _ _ 220 ns

ce Rise Delay Time (Write) td5 _ _ 220 ns

r/w Fall Delay Time td6 _ _ 200 ns

r/w Rise Delay Time td7 _ _ 200 ns

Data Seable Time td8 _ _ 550 ns

Data Hold Time td9 _ _ 280 ns

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AX6963 Example of Application Circuit

The AX6963 can be directly connected to a TMPZ84C00A (Z80 (Note 1) CMOS).The AX6963 can be used
with a TMPZ84C00A as shown in the following application circuit.
iMPU memory address mapping
Data is transferred to the AX6963 using a memory request signal.
Address
DATA (I/O) ****H
Command / Status ****+1H

A15 TC74HC244
----------

Address CE
Decoder

A0 C/D

TMPZ84C00P AX6963
TC74HC245

D7 D7
-----

-----
D0 D0

MREQ WR
WR
RD RD

(Note 1) : Z80 is a trademark of Zliog Inc.

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ASLIC AX6963

iMPU I/O addressing

Data is transferred to the AX6963 using an I/O request signal.
I/O Address
DATA **H
Command / Status **+1H

A15

TC74HC244
----------

CE

A8

TMPZ84C00P AX6963
A7
TC74HC244
----------

Address
Decoder

A0 C/D
TC74HC245

D7 D7
-----

-----

8
D0 D0

IORQ WR
WR
RD RD

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ASLIC AX6963

iWhen using PPI LSI (TMP82C55)

The AX6963 can be connected to a PPI LSI.
The port A connects to the data bus.
The port C connects to the control bus. (C/D, CE, WR, RD)

A15

TC74HC244
PC7 CE
----------

PC6 C/D
PC5 WR
PC4 RD
A8

TMPZ84C00P TMP82C55 AX6963

A7 Address
TC74HC244

CS
Decoder
----------

A1
A0 A0
TC74HC245

D7 D7 PA7 D7
-----

-----

-----
-----

8 8
D0 D0 PA0 D0

IORQ
WR
WR
RD RD

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 ASLIC AX6963

Application Circuit (1)

MEMORY FOR
UPPER DISPLAY
A0~12
R/W 6264
13 I/O1~8
ad0~ad12
8 CE1 SRAM
r/w
D0~D7 D0~D7 d0~d7 MEMORY FOR
LOWER DISPLAY
MDS ce A0~12
MD0 R/W 6264
MD1 ad15 I/O1~8
MD2 CE1 SRAM
TMPZ
MD3
84C00P
FS0
FS1
SDSEL

SDI

SDI
P/S

CP
P/S
DI1
DI2

LOAD
DI3

DI1
DI2
DI3
CP
M

LOAD
M
AX6963
CDI CDO CDI CDO
HALT
AX6940 AX6940
DUAL HSCP
IORQ O1....O80 O1....O80
WR CDATA
WR
RD DIO1
RD LP CP
O1
AX6942
....

FR M LCD 64*320 dot

A0 C/D O64
RS/LS
I/O
A1~A7 ADDRESS CE LSCP O1....O80 O1....O80
DECODER
ED
RESET AX6940 AX6940
CDI CDO CDI CDO
LOAD

LOAD
XI XO
SDI

SDI
DI1
DI2
DI3

DI2
DI3
DI1
P/S

P/S
CP
CP
M

RESET VDD VSS

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Application Circuit (2)

EXTERNAL
MEMORY
13
A0~12
R/W 6264
I/O1~8
ad0~ad12
8 CE1 SRAM
r/w
D0~D7 D0~D7 d0~d7
MDS ce
MD0
MD1
MD2
TMPZ
MD3
84C00P
FS0
FS1
SDSEL

AX6963
HALT
DUAL
IORQ WR CDATA
WR
RD DIO1
RD LP CP
O1
AX6942
....

FR M LCD 64*160 dot

A0 C/D O64
RS/LS
I/O
A1~A7 ADDRESS CE HSCP O1....O80 O1....O80
DECODER
ED
RESET AX6940 AX6940
CDI CDO CDI CDO
LOAD

LOAD
XI XO
SDI

SDI
DI1
DI2
DI3

DI2
DI3
DI1
P/S

P/S
CP
CP
M

RESET VDD VSS

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Package Dimensions

Symbol MIN NOM MAX

D
D1 A -- -- 1.80
1.2TYP.
2.0TYP. A1 0.05 -- 0.25
54 33
A2 1.35 1.40 1.45
2.2TYP.

3.8TYP.
b 0.20 0.30 0.40
55

D 24.10 BASIC

32
D1 20.00 BASIC

E1
E
e 0.8 BASIC
E 18.10 BASIC
E1 14.00 BASIC
67

22

L 1.15 1.35 1.55

2.2TYP.
2.2TYP.

1
b 21 L1 2.5 REF.
2.0TYP.
e 2.0TYP.
θ° 0 3.5 7
UNT: mm

NOTES:
A2 A 1.JEDEC:N/A.
2.DATUM PLANE H IS LOCATED AT THE BOTTOM
A1 OF THE MOLD PARTING LINE COINCIDENT WITH
0.076 MAX WHERE THE LEAD EXITS THE BODY.
3.DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION.ALLOWABLE PROTRUSION IS 0.25 mm
PER SIDE.DIMENSIONS D1 AND E1 DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT DATUM
PLANE H .
4.DIMENSION b DOES NOT INCLUDE DAMBAR
GAGE PLANE
SEATING PLANE PROTRUSION.

0.25 L

L1

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