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DIGITAL LOGIC DESIGN LABORATORY

LAB 3

MSI COMBINATIONAL
LOGIC
CIRCUIT

Date: 8 / 5 / 2024 Group: 8.

Student’s Name: Tạ Thanh Vũ . ID: ITITIU21352.
Student’s Name: Lê Ngọc Đăng Khoa . ID: ITITIU20230.
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I/ OBJECTIVES
Upon completion of this experiment, you are able to know:

• The operation of some combinational ICs such as: full adder, parity
generator/checker, comparator, multiplexer, demultiplexer, encoder, decoder.

• How to design combinational circuits using MUX, DEMUX.

II/ COMPONENTS REQUIRED

1. IC 74LS00 : NAND Gates.

2. IC 74LS85 : Four-Bit Magnitude Comparators.

3. IC 74LS86 : XOR Gates

4. IC 74LS148 : 8-to-3 Priority Encoder.

5. IC 74LS138 : 3-to-8 Decoder

III/ CONTENTS
1. Four-bit binary Adder - IC74LS83.

2. Four-bit Magnitude comparator - IC 74LS85

3. Design eight-bit Magnitude comparator by using IC 74LS85 4. Design four bit

Parity Generator/Checker using 74LS86

5. 8-to-3 Priority Encoder - IC74LS148.

6. 2 → 4 Decoder - IC74LS139

7. 3 → 8 Decoder - IC74LS138

8. Design combinational circuits using decoders and NAND gates

IV/ PRE-LAB
- Pre-labincludes reading the lab assignment in advance, answering the questions or
doing the calculations, and if necessary reviewing the material in the textbook. All
pre-lab preparation must be recorded and dated in the pre-lab sheet prior doing the
lab. The lab instructor will check your pre-lab write-up and sign your pre-lab sheet.

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- Answering all the questions, fulfill the truth table and present diagram on this
experiment before doing the lab.

- If you don’t prepare the pre-lab, you are not allowed to experiment.

V/ EXPERIMENT 1. 4-BIT MAGNITUDE COMPARATOR - IC

74LS85
2
3 A < B (ALTBI)
4 A = B (AEQBI)
A > B (AGTBI)
10
12 A0
A 13 A1
A2
15
A3 7
A < B (ALTBO) 6
A = B (AEQBO) 5
A >B (AGTBO)
9
11 B0
B 14
1
B1
B2
B3

74LS85

FIGURE 1 - MAGNITUDE COMPARATORS - IC 74LS85

- A and B are connected to data switches.

- Experiment to verify the truth table of IC 74LS85.

Comparing Input Cascading Input Output

A3,B3 A2,B2 A1,B1 A0,B0 A>B A<B A=B A>B A<B A=B

A3>B3 X X X X X X 1 0 0
A3<B3 X X X X X X 0 1 0
A3 =B3 A2>B2 X X X X X 1 0 0
A3 =B3 A2<B2 X X X X X 0 1 0
A3 =B3 A2=B2 A1>B1 X X X X 1 0 0
A3 =B3 A2=B2 A1<B1 X X X X 0 1 0
A3 =B3 A2=B2 A1=B1 A0>B0 X X X 1 0 0
A3 =B3 A2=B2 A1=B1 A0<B0 X X X 0 1 0
A3 =B3 A2=B2 A1=B1 A0=B0 1 0 0 1 0 0
A3 =B3 A2=B2 A1=B1 A0=B0 0 1 0 0 1 0
A3 =B3 A2=B2 A1=B1 A0=B0 X X 1 0 0 1
A3 =B3 A2=B2 A1=B1 A0=B0 0 0 0 0 0 0
A3 =B3 A2=B2 A1=B1 A0=B0 1 1 0 1 1 0

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2. DESIGN EIGHT-BIT MAGNITUDE COMPARATOR USING IC

74LS85

Figure 2 - Eight-bit magnitude comparator

- Build the circuit in figure 3.

- Data of X and Y are driven using switches. - Fulfill the following table.

Result
X Y
LED1 LED2 LED3
0101 0101 0101 0111 1 0 0
1111 0101 0101 0111 1 0 1
1111 0101 1111 0100 1 1 0
1001 0110 0101 1000 1 1 1
- What is the purpose of the cascading inputs of 74LS85(II)?

Cascading Inputs of 74LS85

Purpose: Allows for the extension of the comparison capability beyond 4 bits. By using
cascading inputs:

A>B, A<B, A=B: These inputs are fed from one 74LS85 to another to integrate comparison
results from lower bit levels to higher, allowing comprehensive multi-bit comparisons.

By aligning your LEDs to these outputs, you can visualize the comparison results for
different input configurations and understand how cascading inputs influence the overall
comparison across multiple ICs. This setup will demonstrate the effectiveness of
cascading in handling complex, multi-bit comparisons in digital electronics.

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3. DESIGN FOUR BIT PARITY GENERATOR/CHECKER USING

74LS86
- Conduct the truth table of the four bit parity generator/checker
A B C D Even Output Odd Output
0 0 0 0 0 1
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0 1
1 0 1 0 0 1
1 0 1 1 1 0
1 1 0 0 0 1
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 0 1

- Implement the circuit four bit parity generator/checker using XOR gates
4. 8-TO-3 PRIORITY ENCODER (INTERRUPT SORTER) - IC74LS148

A. CONDUCT THE TRUTH TABLE OF 74LS148

SW1 - 8

10 9
11 D0 A0 7
12 D1 A1 6
13 D2 A2
D3 LED_DISPLAY
1
2 D4
3 D5 14
4 D6 GS LED
D7
5 15
SW9 EI EO LED
74LS148

FIGURE 3 – ENCODER 8-TO-3 IC 74LS148

- The outputs are connected to LED display to determine the logic levels.

- Choose the input data D0  D7 by switches in the order from SW0 to SW7.

- Control EI by using switch.

- Observe the results and fulfill the truth table of 74LS148.

- GS and EO?
What are the functions of
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+ When any input is LOW, (GS)' is active LOW; this signifies when any
input is active. When all inputs are HIGH, (EO)' is active LOW.

Input Output

EI D0 D1 D2 D3 D4 D5 D6 D7 GS A2 A1 A0 E0
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 X X X X X X X 0 0 0 0 0 1
0 X X X X X X 0 1 0 0 0 1 1
0 X X X X X 0 1 1 0 0 1 0 1
0 X X X X 0 1 1 1 0 0 1 1 1
0 X X X 0 1 1 1 1 0 1 0 0 1
0 X X 0 1 1 1 1 1 0 1 0 1 1
0 X 0 1 1 1 1 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 1 0 1 1 1 1

B. PRIORITY ENCODER
Let’s EI equal to 0, how are the outputs A2, A1, A0 in the following cases?

A2 A1 A0
Case 1: 1 0 0
I3 = I2 = I1 = 0
I7 = I6 = I5 = I4 = I0 = 1.

Case 2: 0 0 0
I7 = I2 = 0.
I6 = I5 = I4 = I3 = I1= I0 =1

Case 3: 0 0 0
All 8 inputs are equal to 0.

Make comment on results

Case 1:

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Case 2:

Case 3:

5. 2-TO-4 DECODER - IC74LS139

2 4
3 A Y0 5
B Y1 6
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Y3
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1
G
LED DISPLAY (1,2,3,4)
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SW3

SW1 74LS139

FIGURE 4 – DECODER 2-LINE-TO-4-LINE IC 74LS139

- 4 outputs (Y0-Y3) are connected to LED display (Led 1-4).

- The data inputs (A, B) and control input (G) are connected to switches. -
Change the states of inputs to fulfill the truth table of IC 74LS139.

Inputs
Outputs
Control Data
G B A Y0 Y1 Y2 Y3
0 0 0 0 1 1 1
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 1 1 1 0
1 X X 0 0 0 0

6. 3-TO-8 DECODER (IC 74LS138)

1 15
SW1 2 A Y0 14
SW2 3 B Y1 13
SW3 C Y2 12
Y3 11
6 Y4 10
SW4 4 G1 Y5 9
SW5 5 G2A Y6 7
SW6 G2B Y7
LED_DISPLAY
74LS138

FIGURE 5 – 3-TO-8 DECODER

- 8 outputs are observed by using LEDs.

- The inputs are controlled by switches.

- Fulfill the following table:

INPUT OUTPUT

G1 G2A G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
B
1 0 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 0 1 1 0 1 1 1 1 1 1
1 0 0 0 1 0 1 1 0 1 1 1 1 1
1 0 0 0 1 1 1 1 1 0 1 1 1 1
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1 0 0 1 0 0 1 1 1 1 0 1 1 1
1 0 0 1 0 1 1 1 1 1 1 0 1 1
1 0 0 1 1 0 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1

7. DESIGN COMBINATIONAL CIRCUITS USING DECODERS AND

NAND GATES
Implement Boolean expression using IC 74LS138 & 74LS00.
- Using 74LS00 combined with the appropriate outputs of 74LS138 to implement the
function f = ∑ x , y , z (1 , 3 ,5).

f= ∑ x , y , z (1 , 3 ,5)= m1 + m3 + m5 = m 1+ m3+m 5 = m 1. m 3. m 5
= m 1.m 3. m5 => Y 1.Y 3. Y 5

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