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Assignment 1

Uploaded by

bhanduom
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© © All Rights Reserved
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CMOS VLSI Design

Assignment 1
Name: Bandhavya.O.M.
Reg. No: 2022BECE07AED030
Question: Design and verify the four bits sequence 1110 detector using
Verilog coding Using Mealy FSM.
Solution:
Definition of FSM:
FSM- Finite State Machine. A Finite State Machine is the mathematical model of
computation which is used to represent the system which has finite number of
state and transitions. Some of the characteristics are:
1. States: FSMs have finite number of states, which are the conditions of
existence.
2. Transitions: FSMs have finite number of transitions that are triggered by
events,
3. Representation: FSMs are often represented as graphs, with nodes
representing states and arcs representing transitions.
State Diagram:

State table:
State Input Next State Output
S0 0 S0 0
S0 1 S1 0
S1 0 S0 0
S1 1 S2 0
S2 0 S0 0
S2 1 S3 0
S3 0 S0 0
S3 1 S3 1

Code:
Verilog code:
module seq_detector_1110(input bit clk, rst_n, x, output z);
parameter A = 4'h1;
parameter B = 4'h2;
parameter C = 4'h3;
parameter D = 4'h4;
parameter E = 4'h5;
bit [3:0] state, next_state;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= A;
end
else state <= next_state;
end
always @(state or x) begin
case(state)
A: begin
if(x == 1) next_state = B;
else next_state = A;
end
B: begin
if(x == 1) next_state = C;
else next_state = A;
end
C: begin
if(x == 1) next_state = D;
else next_state = A;
end
D: begin
if(x == 0) next_state = E;
else next_state = A;
end
E: begin 3
if(x == 1) next_state = B;
else next_state = A;
end
default: next_state = A;
endcase
end
assign z = (state == E) ? 1 : 0;
endmodule

Test bench:
module tb_seq_detector_1110;
reg clk;
reg rst_n;
reg x;
wire z;
seq_detector_1110 uut (
.clk(clk),
.rst_n(rst_n),
.x(x),
.z(z)
);
always #5 clk = ~clk;
initial begin
clk = 0;
rst_n = 0;
x = 0;
#10;
rst_n = 1;
#10 x = 1;
#10 x = 1; 4
#10 x = 0;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#50;
$finish;
end
initial begin
$monitor("Time: %0t, x: %b, z: %b", $time, x, z);
end
endmodule

Schematic Representation of the Circuit:


Waveform:

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