Dayananda Sagar Academy of Technology & Management

(Autonomous Institute under VTU)

Semester : 3rd Semester

Course Title : Digital Design and Computer Organization
Course Code :
Course Type Integrated
:
(Theory/ Practical/ Integrated)
Category : IPCC
Stream : Information Science and CIE : 50
Engineering
Teaching hours/ week (L:T:P:S) : 3:0:2:0 SEE : 50

Total Hours : 40+20 SEE : 3 Hours

Credits : 4 Duration

Course Learning Objectives: Students will be able to:

Sl. No Course Objectives
1 Understand the requirement of digital system and the basic structure of computer.
2 Apply combinational and sequential circuits in the design of digital systems.

3 Analyze digital circuits, encompassing storage elements and different computer architectures,
to gauge their operational effectiveness.
4 Demonstrate different data types on simple arithmetic and logical unit and the functions of
basic processing unit, Parallel processing.
5 Design digital circuits and create corresponding HDL codes.

Teaching-Learning Process
Pedagogical Initiatives:
Some sample strategies to accelerate the attainment of various course outcomes are listed below:
 Adopt different teaching methods to attain the course outcomes.
 Include videos to demonstrate various concepts in C.
 Encourage collaborative (Group) Learning to encourage team building.
 Ask at least three HOTS (Higher-order Thinking Skills) module-wise questions to promote critical
thinking.
 Adopt Problem-Based Learning (PBL), which fosters students’ analytical skills, and develops thinking
skills such as evaluating, generalizing, and analyzing information rather than simply recalling it.
 Show different ways to solve a problem and encourage the students to come up with creative and optimal
solutions.
 Discuss various case studies to map with real-world scenarios and improve the understanding.
 Devise innovative pedagogy to improve Teaching-Learning Process (TLP).

Scheme of Teaching and Examinations for BE Programme -2024-25

DSATM
 Outcome Based Education and Choice Based Credit System (CBCS)
(Effective from the Academic Year 2024-25)
COURSE CURRICULUM
Module Topics Hours
No.
BASIC CONCEPTS OF DIGITAL SYSTEMS: Sum-of-Products simplifications, Karnaugh
1 Map, Pairs Quads, and Octets, Karnaugh Simplifications, Don’t-care Conditions, Product- 8
of-sums simplifications, NAND and NOR Implementation, Simplification by Quine-McClusky
Method.
Introduction to HDL: HDL Implementation Models.
Textbook 1: Chapter 3: 3.1, 3.2 ,3.3 ,3.4 ,3.5,3.6,3.9

Pedagogy Problem Solving

DESIGN OF COMBINATIONAL LOGIC CIRCUITS: Introduction, Combinational Circuits,
Decimal Adder; Decoders, Encoders; Multiplexers, De-multiplexers; Magnitude 8
2 Comparator; HDL Models of Combinational Circuits.
SEQUENTIAL CIRCUITS-I: Introduction, Sequential Circuits, Storage Elements: Latches,
Flip-Flops: SR, JK, D, T and Master-Slave Flip-Flop – Characteristic table and equation.
Textbook 1: Chapter 4: 4.1, 4.2 ,4.6 ,4.8 ,4.9, 4.10,4.11,4.12 Chapter 5: 5.1,5.2,5.3,5.4
Pedagogy Virtual Lab, Think Pair and Share
SEQUENTIAL CIRCUITS-II: Registers-Types of Registers, Asynchronous-Ripple Counter 8
and Synchronous Counters.
3
HDL MODELS OF SEQUENTIAL CIRCUITS: Flip-flop, Register and Counters.
Textbook 1: Chapter 5: 5.6 Chapter 6: 6.1, 6.2, 6.3, 6.4,6.6
Pedagogy Problem Solving, Virtual Lab
BASIC STRUCTURE OF COMPUTERS: Functional Units, Basic Operational Concepts,
Bus structure, Performance – Processor Clock, Basic Performance Equation, Clock Rate, 8
4 Performance Measurement.
MACHINE INSTRUCTIONS AND PROGRAMS: Memory Location and Addresses, Memory
Operations, Instruction and Instruction sequencing, Addressing Modes.
Textbook 2: Chapter 1: 1.2, 1.3, 1.4, 1.6, Chapter 2: 2.2, 2.3, 2.4, 2.5

Pedagogy Poster Presentation

INPUT/OUTPUT ORGANIZATION: Accessing I/O Devices, Interrupts – Interrupt Hardware,
5 Enabling and Disabling Interrupts, Handling Multiple Devices, Direct Memory Access: Bus 8
Arbitration, Speed, size, and Cost of memory systems.
BASIC PROCESSING UNIT: Some Fundamental Concepts: Register Transfers,
Performing ALU operations, fetching a word from Memory, Storing a word in memory.
Execution of a Complete Instruction.
 Textbook 2: Chapter 4: 4.1, 4.2.1, 4.2.2, 4.2.3, 4.4 Chapter 5: 5.4, 5.5.1 Chapter 7: 7.1, 7.2
Poster Presentation
Pedagogical Initiatives (Not limited to):
 Think Pair and Share (Blended Learning): provides an opportunity for students to learn from
one another
 Problem Solving: encourages cognitive thinking and enables creative problem solving
 Poster Presentation: allows students to represent the concepts visually to understand the
topics easily.
 Case studies: maps different domains in real time applications
 Demonstration: exhibits the implementation process

List of Programs:

Sl. No. Experiments/Programs COs

Simulation packages preferred: Multisim, Modelsim, PSpice or any other relevant
1 a. Given a 4-variable logic expression, simplify it using appropriate technique using basic
gates.
CO5
b. Design and develop the HDL code for a 4-variable logic expression. Simulate and verify it’s
working.
2 a. Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the
simplified logic expression using 8:1 multiplexer IC. CO5
b. Design and develop the HDL code for an 8:1 multiplexer. Simulate and verify it’s working.
3 a. Design and verify the Truth Table of 3×8 decoder using basic logic gates.
CO5
b. Design and develop the HDL code for a 3×8 decoder. Simulate and verify it’s working.
4 a. Design and verify the Truth Table of 8×3 encoder using basic logic gates.
CO5
b. Design and develop the HDL code for a 8×3 encoder. Simulate and verify it’s working.
5 a. Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity Checker using
basic Logic Gates with an even parity bit. CO5
b. Design and develop the HDL code 3-bit Parity Generator. Simulate and verify it’s working.
6 a. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth-table.
b. Design and develop the HDL code for D Flip-Flop with positive-edge triggering. Simulate CO5
and verify it’s working.
7 a. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and
demonstrate its working. CO5
b. Design and develop the HDL code for mod-8 up counter. Simulate and verify it’s working.
8 Design and implement an asynchronous counter using decade counter IC to count-up from 0
CO5
to n (n<=9) and demonstrate on 7-segment display (using IC- 7447).
Open ended Programs
Design a 4/8-bit CPU using the LOGISIM simulator, for the following specifications.
1 Implement the following instructions namely: MOV, ADD, SUB, LOAD, STORE, AND, XOR,
CO4
NOT, BRANCH, BRANCH ON CONDITION.
2 Result to be displayed on 7‐segment displays / reg tab of LOGISIM CO4
3 ALU (to support 4-bit integer arithmetic operations & 4-bit logical operations) CO4
4 Instruction Register (Assume instruction size as 16 bit) CO4
NOTE: Students can utilize this link to enhance their understanding
https://cse11-iiith.vlabs.ac.in/

Text Books
 Sl. No. Title of the Book/Name of the author/Name of the publisher/Edition and Year

1 “Digital Design with an Introduction to Verilog Design”, M. Morris Mano & Michael D. Ciletti, 5e,
Pearson Education.
2 “ Computer Organization”, Carl Hamacher, Zvonko Vranesic, SafwatZaky, 5th Edition, Tata McGraw-
Hill.
Reference Books

1
Digital Principles and Design, Donald D.Givone, Tata McGraw-Hill, 2003.
2 Digital Principles and Applications, Donald P Leach, Malvoni, GautamSaha Tata McGraw Hill, 7th
Edition 2010
3
Fundamentals of logic design, Charles H Roth, Larry N. Kinney, Cengage Learning, 7 th Ed., 2014.
4 Computer Organization and Design, David A. Patterson and John L. Hennessy, Elsevier, 5th Edition,
2014
5 William Stallings “Computer Organization and Architecture”, Seventh Edition, Pearson Education,
2006.

Course Outcomes: At the end of the course, the student will be able to:
RBT Level
CO Course Outcomes RBT
Indicator
Level
CO Understand the functionalities of binary logic system and the computer
organization. U L2
1
CO Apply principles of digital systems to design and optimize circuits, and manage
input/output operations in computer systems A L3
2
CO Analyze digital circuits, including storage elements and system process, to
assess their functionality and efficiency. An L4
3

CO Evaluate different data types on a simple arithmetic and logical unit, and assess
E L5
4 the functions of a basic processing unit.

CO Design digital circuits and develop corresponding HDL codes. C L6

5

Weblinks and Video Lectures (e-Resources)

1 https://www.youtube.com/watch?v=wk6O1OuAZn0&list=PLwdnzlV3ogoVlY7iVqr-FhWUQEX7JDdiP&index=4 (nptel)

2 https://www.youtube.com/watch?v=QXOVwIoPGsM&list=PLwdnzlV3ogoVlY7iVqr-FhWUQEX7JDdiP&index=9

3 https://www.youtube.com/watch?v=PqhTjBdiMk4&list=PLwdnzlV3ogoVlY7iVqr-FhWUQEX7JDdiP&index=10
4 https://www.youtube.com/watch?v=mv-3hPgkNzM&list=PLwdnzlV3ogoVlY7iVqr-FhWUQEX7JDdiP&index=12

5 https://www.youtube.com/watch?v=YXzgX8gyMFs&list=PLwdnzlV3ogoVlY7iVqr-FhWUQEX7JDdiP&index=23

6 https://www.youtube.com/watch?v=9KzOApr5gKw&list=PLwdnzlV3ogoVlY7iVqr-FhWUQEX7JDdiP&index=24

7 https://www.youtube.com/watch?v=qaTUzzysVew&list=PLwdnzlV3ogoVlY7iVqr-FhWUQEX7JDdiP&index=27

8 https://www.youtube.com/watch?v=Ubp_L-7lucw&list=PLwdnzlV3ogoVlY7iVqr-FhWUQEX7JDdiP&index=28

9 https://www.youtube.com/watch?v=3Jppx70tVp0&list=PLwdnzlV3ogoVlY7iVqr-FhWUQEX7JDdiP&index=30

10 https://www.youtube.com/watch?v=POKtkWJI6KU&list=PLwdnzlV3ogoVlY7iVqr-FhWUQEX7JDdiP&index=34

11 https://www.youtube.com/watch?v=Y17TLZCSe4M&list=RDQMbn7C5WgGghA&index=24

12 https://www.youtube.com/watch?v=4goj-ajnpOQ&list=RDQMbn7C5WgGghA&index=1

13 https://www.youtube.com/watch?v=p9wxyIx-j-c&list=PL1A5A6AE8AFC187B7&index=12

14 https://cse11-iiith.vlabs.ac.in/

15 https://nptel.ac.in/courses/108105113