ATmega32A

• Bit 4 – TWSTO: TWI STOP Condition Bit

Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire Serial Bus. When
the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the
TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI
returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.

• Bit 3 – TWWC: TWI Write Collision Flag

The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is low. This flag is
cleared by writing the TWDR Register when TWINT is high.

• Bit 2 – TWEN: TWI Enable Bit

The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI
takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters.
If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any
ongoing operation.

• Bit 1 – Reserved
This bit is a reserved bit and will always read as zero.

• Bit 0 – TWIE: TWI Interrupt Enable

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as
the TWINT Flag is high.

21.9.3 TWSR – TWI Status Register

Bit 7 6 5 4 3 2 1 0
TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 TWSR
Read/Write R R R R R R R/W R/W
Initial Value 1 1 1 1 1 0 0 0

• Bits 7:3 – TWS: TWI Status

These five bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status codes are
described later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-
bit prescaler value. The application designer should mask the prescaler bits to zero when checking the Status bits.
This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless oth-
erwise noted.

• Bit 2 – Reserved
This bit is reserved and will always read as zero.

• Bits 1:0 – TWPS: TWI Prescaler Bits

These bits can be read and written, and control the bit rate prescaler.

Table 21-7. TWI Bit Rate Prescaler

TWPS1 TWPS0 Prescaler Value
0 0 1
0 1 4
1 0 16
1 1 64

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 ATmega32A

To calculate bit rates, see “Bit Rate Generator Unit” on page 177. The value of TWPS1:0 is used in the equation.

21.9.4 TWDR – TWI Data Register

Bit 7 6 5 4 3 2 1 0
TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 TWDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 1 1 1 1 1 1 1 1

In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last
byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt
Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first inter-
rupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus
is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a
sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitra-
tion, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the
TWI logic, the CPU cannot access the ACK bit directly.

• Bits 7:0 – TWD: TWI Data Register

These eight bits contin the next data byte to be transmitted, or the latest data byte received on the Two-wire Serial
Bus.

21.9.5 TWAR – TWI (Slave) Address Register

Bit 7 6 5 4 3 2 1 0
TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 1 1 1 1 1 1 1 0

The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the
TWI will respond when programmed as a slave transmitter or receiver. In multimaster systems, TWAR must be set
in masters which can be addressed as slaves by other masters.
The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address
comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a
match is found, an interrupt request is generated.

• Bits 7:1 – TWA: TWI (Slave) Address Register

These seven bits constitute the slave address of the TWI unit.

• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus.

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 ATmega32A

22. Analog Comparator

22.1 Overview
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the volt-
age on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output,
ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition,
the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt
triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is
shown in Figure 22-1.

Figure 22-1. Analog Comparator Block Diagram(1)(2)

BANDGAP
REFERENCE

ACBG

ACME
ADEN

ADC MULTIPLEXER
OUTPUT (1)

Notes: 1. See Table 22-1 on page 198.

2. Refer to Figure 1-1 on page 10 and Table 13-6 on page 64 for Analog Comparator pin placement.

22.2 Analog Comparator Multiplexed Input

It is possible to select any of the ADC7:0 pins to replace the negative input to the Analog Comparator. The ADC
multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the
Analog Comparator Multiplexer Enable bit (ACME in SFIOR) is set and the ADC is switched off (ADEN in ADCSRA
is zero), MUX2:0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown
in Table 22-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator.

Table 22-1. Analog Comparator Multiplexed Input

ACME ADEN MUX2:0 Analog Comparator Negative Input
0 x xxx AIN1
1 1 xxx AIN1
1 0 000 ADC0
1 0 001 ADC1
1 0 010 ADC2

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 ATmega32A

Table 22-1. Analog Comparator Multiplexed Input (Continued)

ACME ADEN MUX2:0 Analog Comparator Negative Input
1 0 011 ADC3
1 0 100 ADC4
1 0 101 ADC5
1 0 110 ADC6
1 0 111 ADC7

22.3 Register Description

22.3.1 SFIOR – Special Function IO Register

Bit 7 6 5 4 3 2 1 0
ADTS2 ADTS1 ADTS0 – ACME PUD PSR2 PSR10 SFIOR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 3 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer
selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the neg-
ative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed
Input” on page 198.

22.3.2 ACSR – Analog Comparator Control and Status Register

Bit 7 6 5 4 3 2 1 0
ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 N/A 0 0 0 0 0

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any
time to turn off the Analog Comparator. This will reduce power consumption in active and Idle mode. When chang-
ing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an
interrupt can occur when the bit is changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When
this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference”
on page 47.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization
introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and
ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI
is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by
writing a logic one to the flag.

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 ATmega32A

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator Interrupt is
activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog
Comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making
the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt.
When written logic zero, no connection between the Analog Comparator and the Input Capture function exists. To
make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask
Register (TIMSK) must be set.

• Bits 1:0 – ACIS[1:0]: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings
are shown in Table 22-2.

Table 22-2. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode
0 0 Comparator Interrupt on Output Toggle
0 1 Reserved
1 0 Comparator Interrupt on Falling Output Edge
1 1 Comparator Interrupt on Rising Output Edge

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt
Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.

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 ATmega32A

23. Analog to Digital Converter

23.1 Features
• 10-bit Resolution
• 0.5 LSB Integral Non-linearity
• ±2 LSB Absolute Accuracy
• 13 - 260 µs Conversion Time
• Up to 15kSPS at Maximum Resolution
• 8 Multiplexed Single Ended Input Channels
• 7 Differential Input Channels
• 2 Differential Input Channels with Optional Gain of 10x and 200x
• Optional Left adjustment for ADC Result Readout
• 0 - VCC ADC Input Voltage Range
• Selectable 2.56V ADC Reference Voltage
• Free Running or Single Conversion Mode
• ADC Start Conversion by Auto Triggering on Interrupt Sources
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler

23.2 Overview
The ATmega32A features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog
Multiplexer which allows 8 single-ended voltage inputs constructed from the pins of Port A. The single-ended volt-
age inputs refer to 0V (GND).
The device also supports 16 differential voltage input combinations. Two of the differential inputs (ADC1, ADC0
and ADC3, ADC2) are equipped with a programmable gain stage, providing amplification steps of 0 dB (1x), 20 dB
(10x), or 46 dB (200x) on the differential input voltage before the A/D conversion. Seven differential analog input
channels share a common negative terminal (ADC1), while any other ADC input can be selected as the positive
input terminal. If 1x or 10x gain is used, 8-bit resolution can be expected. If 200x gain is used, 7-bit resolution can
be expected.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant
level during conversion. A block diagram of the ADC is shown in Figure 23-1.
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ±0.3V from VCC. See
the paragraph “ADC Noise Canceler” on page 208 on how to connect this pin.
Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage reference may be exter-
nally decoupled at the AREF pin by a capacitor for better noise performance.

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 ATmega32A

Figure 23-1. Analog to Digital Converter Block Schematic

ADC CONVERSION
COMPLETE IRQ

INTERRUPT
FLAGS

ADTS[2:0]

8-BIT DATA BUS

ADIE
ADIF
15 0
ADC MULTIPLEXER ADC CTRL. & STATUS ADC DATA REGISTER
SELECT (ADMUX) REGISTER (ADCSRA) (ADCH/ADCL)

REFS1

ADLAR

MUX4

MUX3

MUX2

MUX1

MUX0
REFS0

ADATE

ADPS2

ADPS1

ADPS0
ADEN

ADSC

ADIF

ADC[9:0]
TRIGGER
SELECT

MUX DECODER
PRESCALER

CHANNEL SELECTION
START

GAIN SELECTION
CONVERSION LOGIC
AVCC

INTERNAL 2.56V
REFERENCE SAMPLE & HOLD
COMPARATOR
AREF
10-BIT DAC -
+

GND

BANDGAP
REFERENCE

ADC7
SINGLE ENDED / DIFFERENTIAL SELECTION
ADC6

POS. ADC MULTIPLEXER

ADC5 INPUT OUTPUT
MUX
ADC4

ADC3 GAIN
AMPLIFIER
+
ADC2
-
ADC1

ADC0

NEG.
INPUT
MUX

23.3 Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The mini-
mum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB.
Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the
REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capaci-
tor at the AREF pin to improve noise immunity.
The analog input channel and differential gain are selected by writing to the MUX bits in ADMUX. Any of the ADC
input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the
ADC. A selection of ADC input pins can be selected as positive and negative inputs to the differential gain
amplifier.
If differential channels are selected, the differential gain stage amplifies the voltage difference between the
selected input channel pair by the selected gain factor. This amplified value then becomes the analog input to the
ADC. If single ended channels are used, the gain amplifier is bypassed altogether.

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 ATmega32A

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selec-
tions will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is
recommended to switch off the ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default,
the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in
ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise,
ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conver-
sion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and
a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost.
When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the
Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.

23.4 Starting a Conversion

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as
long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a differ-
ent data channel is selected while a conversion is in progress, the ADC will finish the current conversion before
performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting
the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger
Select bits, ADTS in SFIOR (see description of the ADTS bits for a list of the trigger sources). When a positive
edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a
method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a
new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge
will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the global interrupt
enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Inter-
rupt Flag must be cleared in order to trigger a new conversion at the next interrupt event.

Figure 23-2. ADC Auto Trigger Logic

ADTS[2:0]
PRESCALER

START CLKADC
ADIF ADATE
SOURCE 1
. CONVERSION
. LOGIC
.
. EDGE
SOURCE n DETECTOR

ADSC

Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing
conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the
ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In

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 ATmega32A

this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is
cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can
also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion,
independently of how the conversion was started.

23.5 Prescaling and Conversion Timing

Figure 23-3. ADC Prescaler

ADEN
START Reset
7-BIT ADC PRESCALER
CK

CK/128
CK/64
CK/32
CK/16
CK/2
CK/4
CK/8
ADPS0
ADPS1
ADPS2

ADC CLOCK SOURCE

By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to
get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be
higher than 200kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU fre-
quency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the
moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as
the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the follow-
ing rising edge of the ADC clock cycle. See “Differential Gain Channels” on page 206 for details on differential
conversion timing.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADC-
SRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC
clock cycles after the start of a first conversion. When a conversion is complete, the result is written to the ADC
Data Registers, and ADIF is set. In single conversion mode, ADSC is cleared simultaneously. The software may
then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from
the trigger event to the start of conversion. In this mode, the sample-and-hold takes place 2 ADC clock cycles after
the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic.
When using Differential mode, along with Auto Trigging from a source other than the ADC Conversion Complete,
each conversion will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after every
conversion.

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 ATmega32A

In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC
remains high. For a summary of conversion times, see Table 23-1.

Figure 23-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
First Conversion Conversion

Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3

ADC Clock

ADEN

ADSC

ADIF

ADCH MSB of Result

ADCL LSB of Result

MUX and REFS Conversion

Update Sample & Hold Complete MUX and REFS
Update

Figure 23-5. ADC Timing Diagram, Single Conversion

One Conversion Next Conversion

Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3

ADC Clock

ADSC

ADIF

ADCH MSB of Result

ADCL LSB of Result

Sample & Hold Conversion

MUX and REFS Complete MUX and REFS
Update Update

Figure 23-6. ADC Timing Diagram, Auto Triggered Conversion

One Conversion Next Conversion

Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2

ADC Clock

Trigger
Source

ADATE

ADIF

ADCH MSB of Result

ADCL LSB of Result

Sample & Hold Conversion Prescaler

Prescaler Reset
Complete
Reset
MUX and REFS
Update

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 ATmega32A

Figure 23-7. ADC Timing Diagram, Free Running Conversion

One Conversion Next Conversion

11 12 13 1 2 3 4
Cycle Number

ADC Clock

ADSC

ADIF

ADCH MSB of Result

ADCL LSB of Result

Conversion Sample & Hold

Complete MUX and REFS
Update

Table 23-1. ADC Conversion Time

Sample & Hold (Cycles
Condition from Start of Conversion) Conversion Time (Cycles)
First conversion 13.5 25
Normal conversions, single ended 1.5 13
Auto Triggered conversions 2 13.5
Normal conversions, differential 1.5/2.5 13/14

23.5.1 Differential Gain Channels

When using differential gain channels, certain aspects of the conversion need to be taken into consideration.
Differential conversions are synchronized to the internal clock CKADC2 equal to half the ADC clock. This synchroni-
zation is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a specific
phase of CKADC2. A conversion initiated by the user (that is, all single conversions, and the first free running con-
version) when CKADC2 is low will take the same amount of time as a single ended conversion (13 ADC clock cycles
from the next prescaled clock cycle). A conversion initiated by the user when CKADC2 is high will take 14 ADC clock
cycles due to the synchronization mechanism. In Free Running mode, a new conversion is initiated immediately
after the previous conversion completes, and since CKADC2 is high at this time, all automatically started (that is, all
but the first) free running conversions will take 14 ADC clock cycles.
The gain stage is optimized for a bandwidth of 4kHz at all gain settings. Higher frequencies may be subjected to
non-linear amplification. An external low-pass filter should be used if the input signal contains higher frequency
components than the gain stage bandwidth. Note that the ADC clock frequency is independent of the gain stage
bandwidth limitation. For example, the ADC clock period may be 6 µs, allowing a channel to be sampled at
12kSPS, regardless of the bandwidth of this channel.
If differential gain channels are used and conversions are started by Auto Triggering, the ADC must be switched off
between conversions. When Auto Triggering is used, the ADC prescaler is reset before the conversion is started.
Since the gain stage is dependent of a stable ADC clock prior to the conversion, this conversion will not be valid.
By disabling and then re-enabling the ADC between each conversion (writing ADEN in ADCSRA to “0” then to “1”),
only extended conversions are performed. The result from the extended conversions will be valid. See “Prescaling
and Conversion Timing” on page 204 for timing details.

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23.6 Changing Channel or Reference Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the
CPU has random access. This ensures that the channels and reference selection only takes place at a safe point
during the conversion. The channel and reference selection is continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for
the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The
user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle
after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken
when updating the ADMUX Register, in order to control which conversion will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is
changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX
can be safely updated in the following ways:
1. When ADATE or ADEN is cleared.
2. During conversion, minimum one ADC clock cycle after the trigger event.
3. After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
Special care should be taken when changing differential channels. Once a differential channel has been selected,
the gain stage may take as much as 125 µs to stabilize to the new value. Thus conversions should not be started
within the first 125 µs after selecting a new differential channel. Alternatively, conversion results obtained within
this period should be discarded.
The same settling time should be observed for the first differential conversion after changing ADC reference (by
changing the REFS1:0 bits in ADMUX).

23.6.1 ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure that the correct
channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The channel selection may
be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the con-
version to complete before changing the channel selection.
In Free Running mode, always select the channel before starting the first conversion. The channel selection may
be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first
conversion to complete, and then change the channel selection. Since the next conversion has already started
automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the
new channel selection.
When switching to a differential gain channel, the first conversion result may have a poor accuracy due to the
required settling time for the automatic offset cancellation circuitry. The user should preferably disregard the first
conversion result.

23.6.2 ADC Voltage Reference

The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that
exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 2.56V reference, or
external AREF pin.

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 ATmega32A

AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the inter-
nal bandgap reference (V BG ) through an internal amplifier. In either case, the external AREF pin is directly
connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor
between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedant voltmeter.
Note that VREF is a high impedant source, and only a capacitive load should be connected in a system.
If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage
options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the
AREF pin, the user may switch between AVCC and 2.56V as reference selection. The first ADC conversion result
after switching reference voltage source may be inaccurate, and the user is advised to discard this result.
If differential channels are used, the selected reference should not be closer to AVCC than indicated in Table 28-6
on page 293.

23.7 ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the
CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To
make use of this feature, the following procedure should be used:
1. Make sure that the ADC is enabled and is not busy converting. Single Conversion Mode must be selected
and the ADC conversion complete interrupt must be enabled.
2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has
been halted.
3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU
and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU
before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete
interrupt request will be generated when the ADC conversion completes. The CPU will remain in active
mode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC
Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid
excessive power consumption. If the ADC is enabled in such sleep modes and the user wants to perform differen-
tial conversions, the user is advised to switch the ADC off and on after waking up from sleep to prompt an
extended conversion to get a valid result.

23.7.1 Analog Input Circuitry

The Analog Input Circuitry for single ended channels is illustrated in Figure 22-8. An analog source applied to
ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is
selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the
series resistance (combined resistance in the input path).
The ADC is optimized for analog signals with an output impedance of approximately 10 k or less. If such a source
is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will
depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recom-
mended to only use low impedant sources with slowly varying signals, since this minimizes the required charge
transfer to the S/H capacitor.
If differential gain channels are used, the input circuitry looks somewhat different, although source impedances of a
few hundred k or less is recommended.
Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to
avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components
with a low-pass filter before applying the signals as inputs to the ADC.

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 ATmega32A

Figure 23-8. Analog Input Circuitry

IIH

ADCn
1..100 kΩ
CS/H= 14 pF
IIL
VCC/2

23.7.2 Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measure-
ments. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques:
1. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground
plane, and keep them well away from high-speed switching digital tracks.
2. The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network as
shown in Figure 23-9.
3. Use the ADC noise canceler function to reduce induced noise from the CPU.
4. If any ADC port pins are used as digital outputs, it is essential that these do not switch while a conversion
is in progress.

Figure 23-9. ADC Power Connections

Analog Ground Plane

PA3 (ADC3)
PA0 (ADC0)

PA1 (ADC1)

PA2 (ADC2)
VCC
GND

PA4 (ADC4)

PA5 (ADC5)

PA6 (ADC6)

PA7 (ADC7)
10μH

AREF

GND
100nF

AVCC

PC7

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 ATmega32A

23.7.3 Offset Compensation Schemes

The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much
as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for
both differential inputs. This offset residue can be then subtracted in software from the measurement results. Using
this kind of software based offset correction, offset on any channel can be reduced below one LSB.

23.7.4 ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code
is read as 0, and the highest code is read as 2n-1.
Several parameters describe the deviation from the ideal behavior:
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal
value: 0 LSB.

Figure 23-10. Offset Error

Output Code

Ideal ADC

Actual ADC

Offset
Error
VREF Input Voltage

• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to
0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB

Figure 23-11. Gain Error

Output Code Gain
Error

Ideal ADC
Actual ADC

VREF Input Voltage

• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an
actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.

 2018 Microchip Technology Inc. Data Sheet Complete DS40002072A-page 210