MODULE II

Programming of 8086 & Interrupt Processing

Interrupt

• Interrupt is the method of creating a temporary halt during

program execution

• The meaning of interrupt is break the sequence of operation

• While the microprocessor is executing a program an interrupt

breaks the normal sequence of execution of instruction, diverts
its execution to some other program called Interrupt Service
Routine(ISR)

• ISR tells the processor what to do when an interrupt occurs

• After executing ISR,IRET returns the control back again to the

main program

Need For Interrupt

• Interrupts are useful when interfacing I/O devices that provide

or require data at relatively low data transfer rate

Sources Of Interrupt

An interrupt for 8086 can come from any of three interrupt

sources

1.Hardware Interrupt

Hardware interrupt is caused by any peripheral device by sending a

signal through a specified pin to the microprocessor.

The 8086 has two hardware interrupt pins, i.e. NMI and INTR.
NMI is a non-maskable interrupt and INTR is a maskable interrupt
having lower priority

2.Software Interrupt

When the normal program execution of a mp` interrupted by a

special instruction, it is called software interrupt

3.Interrupt raised due to some error condition produced in 8086

instruction execution process(Divide by zero,overflow error etc

Types Of Interrupt

Interrupts are classified into three categories

1.Hardware and software interrupt

2.Maskable and non maskable interrupt

3.Vectored and non vectored interrupt

1.Hardware Interrupt & Software Interrupts

NMI and INTR are the hardware interrupts of 8086

• NMI is a single non-maskable interrupt pin having higher

priority than the maskable interrupt request pin (INTR)and it is
of type 2 interrupt.

• The INTR is a maskable interrupt because the microprocessor

will be interrupted only if interrupts are enabled using set
interrupt flag instruction.

• An Interrupt that can be disabled or ignored by the instructions

of CPU are called as Maskable

• The INTR interrupt is activated by an I/O port

 Software Interrupt

• These are generated by inserting INT instruction in a program

• Any of the 256 interrupt can be generated by specifying the

interrupt type after INT instruction (INTn)

• The instruction INTO generates only overflow interrupt.

• It is used after an arithmetic instruction

Intel Predefined (or Dedicated) Interrupts

TYPE 0 or INTO interrupt represents division by zero situation.

TYPE 1 interrupt represents single-step execution during the

debugging of a program.

TYPE 2 interrupt represents non-maskable NMI interrupt.

TYPE 3 interrupt represents break-point interrupt.

TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other

advanced microprocessors,

Interrupts from 32 to Type 255 are available for hardware and

software interrupts.

2.Maskable &Non maskable interrupt

• An Interrupt that can be disabled or ignored by the instructions

of processor is called as Maskable Interrupt.

• The interrupts are either edge-triggered or level-triggered

• An interrupt that cannot be disabled or ignored by the

instructions of CPU are called as Non-Maskable Interrupt.
 • A Non-maskable interrupt is often used when response time is
critical

3.Vectored and Non vectored Interrupt

When an interrupt signal is accepted by the mp,if the program

control automatically branches to a specified address ,called
vectored address ,the interrupt is called vectored interrupt

The automatic branching to vector address is predefined by the

manufactures of the processors

In non-vectored interrupts the interrupt device should supply the

address of the interrupt service subroutine (ISS/ISR) to be executed
in response to the interrupt

All the 8086 interrupts are vectored interrupts.

Interrupt Vector Table

• In 8086 the first 1Kbyte of memory from 00000H to 0003FFH is

set aside as a table for storing the starting addresses of
interrupt procedure

• The table can hold the starting addresses for up to 256

interrupt procedures

• The starting address of an interrupt service procedure stored

in the table is called interrupt vector table or interrupt pointer
table

• To store the starting address of each ISS four bytes of memory

space is required

• 2 bytes for CS and 2 bytes for IP

 • The 1 kB memory space acts as a table to store the starting
addresses of ISS

• This table is also called vector address table

• Each double word interrupt pointer is identified by a number

from 0 to 255

• Intel calls this number the type of interrupt

• Lowest five type are dedicated to specific interrupts (divide by

zero and non maskable interrupt)

• Next 27 interrupts ( type 5 to 31) are reserved by Intel for

future microprocessors

• Upper 224 interrupt(type 32 to 255) are available to use for

hardware and software

Servicing an Interrupt by 8086

• If an interrupt request is identified, then the mp respond to the

interrupt by performing the following operations

1. The SP is decremented by 2 and content of flag reg are pushed on

to stack

2. The interrupt system is disabled by clearing the IF

3. The single step trap flag is disabled by clearing the trap flag TF

4. The SP is decremented by 2and the content of CS are pushed on to

the stack

5. Again the SP is decremented by 2and the content of IP are pushed

on to the stack
6.If the interrupt is through INTR pin, the processor runs an interrupt
acknowledge cycle to get the interrupt type number. For software
interrupt, the type number is specified in the instruction itself. For
NMI and exceptions, the type number is defined by Intel

7. The MP generate 20 bit memory addresses by multiplying the type

number by 4.This memory address is the address of the interrupt
vector table

8. PA of ISS=(10* content of CS)+content of IP

9. The processor executes the ISS to service the interrupt

10. The ISS will be terminated by IRET instruction

11. The stack top is popped to IP, CS and flag reg one by one word.

12. Thus at the end of ISS, the previous status of the processor is
restored and so the processor will resume execution of normal
program from the instruction where it was suspended

Priorities Of Interrupts

• When two or more interrupts occur simultaneously, interrupts

are taken one by one

• For this purpose ,priority is assigned to interrupts

 • The interrupt of the highest priority is serviced first and then
the interrupt of next highest priority is taken up

Interrupt Priority

• Divide error,INT n,INTO Highest

• NMI

• INTR

• Single step Lowest

Addressing modes of 8086

The way of specifying data to be operated by an instruction is known

as addressing modes

Types of addressing modes:

1.Register addressing mode

 In this type of addressing mode both the operands are

registers.

 All registers except IP can be used in this mode

MOV AX,CX

ADD AX,DX

2. Immediate Addressing Mode:

 In this type of addressing mode the source operand is a 8 bit or

16 bit data.

 Destination operand can never be immediate data.

Eg: MOV AX, 0016H

 MOV CL, 0AH

3. Direct Addressing Mode

 In the direct addressing mode, a 16-bit memory address (offset)

is directly specified in the instruction as a part of it.

•Eg: MOV AX,[5000H]

–Effective address= 10H*DS +5000H

4 Register Indirect:

 The address of the memory location which contains data or

operand is determined in an indirect way, using the offset
registers.

 This mode of addressing is known as register indirect mode

 In this addressing mode, the offset address of data is in either

BX or SI or DI register.

 The default segment is either DS or ES.

 •Eg: MOV AX,[BX]

 Effective address is 10H*DS+[BX]

5 Indexed:

 In this addressing mode, offset of the operand is stored in one

of the Index registers.

 DS is the default segment for index registers SI and DI

 In the case of string instructions DS and ES are default

segments for SI and DI respectively.

Eg: MOV AX,[SI]

 –effective address is 10H*DS+[SI]

6 Register Relative:

 In this addressing mode, the data is available at an effective

address formed by adding an 8-bit or 16-bit displacement with
the content of any one of the registers BX, BP, SI and DI in the
default (either DS or ES) segment.

Eg: MOV AX,50H[BX]

–Effective address is 10H*DS+50H+[BX]

7 Based Indexed:

 The effective address of the data is formed, in this addressing

mode, by adding the content of a base register (any one of BX
or BP) to the content of an index register (any one of SI or DI)

 The default segment register may be DS or ES

–Eg: MOV AX,[BX][SI]

Effective address is 10H*DS +[BX]+[SI]

8 Relative Based Indexed:

 The effective address is formed by adding an 8-bit or 16-bit

displacement with the sum of contents of anyone of the base
registers (BX or BP) and any one of the index registers (SI or DI),
in a default segment. Eg: MOV AX,50H[BX][SI]

–Effective address is 10H* DS+[BX]+[SI]+50H

Instruction Set of 8086

 An instruction is a binary pattern designed inside a

microprocessor to perform a specific function.
  The entire group of instructions that a microprocessor supports
is called Instruction Set.

 8086 has more than 20,000 instructions

The instruction set of 8086 is divided into 7 types

1.Arithmetic Instructions and Logical Instruction

2. Data Transfer Instructions

3. Branch and Loop Instruction

4. M/C control Instruction

5. Flag Manipulation Instructions

6. Shift and Rotate Instruction

7. String Instructions

1,Arithmetic And Logical Instructions

ADD Des, Src:

 It adds a byte to byte or a word to word.

 It effects AF, CF, OF, PF, SF, ZF flags.

E.g.:

 ADD AL, 74H

 ADD DX, AX

 ADD AX, [BX]

ADC Des, Src:

It adds the two operands with CF.

It effects AF, CF, OF, PF, SF, ZF flags.

E.g.:

ADC AL, 74H

ADC DX, AX

ADC AX, [BX]

SUB Des, Src:

 It subtracts a byte from byte or a word from word.

 It affects AF, CF, OF, PF, SF, ZF flags.

 For subtraction, CF acts as borrow flag.

 E.g.:

 SUB AL, 74H

 SUB DX, AX

 SUB AX, [BX]

SBB Des, Src:

 It subtracts the two operands and also the borrow from

the result.

 It effects AF, CF, OF, PF, SF, ZF flags.

 E.g.:

 SBB AL, 74H

 SBB DX, AX

 SBB AX, [BX]

 CBW (Convert Byte to Word):

 This instruction converts byte in AL to word in AX.

  The conversion is done by extending the sign bit of AL
throughout AH.

 CWD (Convert Word to Double Word):

This instruction converts word in AX to double word in DX : AX.

The conversion is done by extending the sign bit of AX throughout

DX.

 CMP Des, Src:

 It compares two specified bytes or words.

 The Src and Des can be a constant, register or memory location.

 Both operands cannot be a memory location at the same time.

 The comparison is done simply by internally subtracting the

source from destination.

 The value of source and destination does not change, but the
flags CF, ZF, SF are modified to indicate the result.

 NEG Src:

 It creates 2’s complement of a given number.

 That means, it changes the sign of a number

 DAA (Decimal Adjust after Addition)

 It is used to make sure that the result of adding two BCD

numbers is adjusted to be a correct BCD number.

 It only works on AL register.

 For Subtraction : DAS (Decimal Adjust after Subtraction)

LOGICAL INSTRUCTIONS
NOT Src:

 It complements each bit of Src to produce 1’s

complement of the specified operand.

 The operand can be a register or memory location.

 e,.g NOT AX

AND Des, Src:

 It performs AND operation of Des and Src.

 Src can be immediate number, register or memory

location.

 Des can be register or memory location.

 Both operands cannot be memory locations at the same

time.

 CF and OF become zero after the operation.

 PF, SF and ZF are updated.

OR Des, Src:

 It performs OR operation of Des and Src.

 Src can be immediate number, register or memory

location.

 Des can be register or memory location.

 Both operands cannot be memory locations at the same

time.

 CF and OF become zero after the operation.

 PF, SF and ZF are updated.

  XOR Des, Src:

 It performs XOR operation of Des and Src.

 Src can be immediate number, register or memory

location.

 Des can be register or memory location.

 Both operands cannot be memory locations at the same

time.

 CF and OF become zero after the operation.

 PF, SF and ZF are updated.

 TEST Des, Src:

 It performs AND operation of Des and Src.

 Src can be immediate number, and src/Des can be

register or memory location.

 It is Non-Destructive And means Dest is not modified only

flags are affected.

 Both operands cannot be memory locations at the same

time.

 CF and OF become zero after the operation.

PF, SF and ZF are updated

2. Data Transfer Instructions

 MOV Des, Src:

 It is used to copy the content of Src to Des

  Src operand can be register, memory location or
immediate operand.

 Des can be register or memory operand.

 Both Src and Des cannot be memory location at the same

time.

 E.g.:

 MOV CX, 037A H

 MOV AL, BL

 MOV BX, [0301 H]

 PUSH Operand:

 It pushes the operand into top of stack.

 E.g.: PUSH BX

 POP Des:

 It pops the operand from top of stack to Des.

 Des can be a general purpose register, segment register

(except CS) or memory location.

 E.g.: POP AX

 XCHG Des, Src:

 This instruction exchanges Src with Des.

 It cannot exchange two memory locations directly.

 E.g.: XCHG DX, AX

 IN Accumulator, Port Address:

  It transfers the operand from specified port to
accumulator register.

 E.g.: IN AX, 0028 H

 OUT Port Address, Accumulator:

 It transfers the operand from accumulator to specified

port.

 E.g.: OUT 0028 H, AX

 LEA Register, Src:

 It loads a 16-bit register with the offset address of the

data specified by the Src.

 E.g.: LEA BX, [DI]

 This instruction loads the contents of DI (offset) into

the BX register.

 LES Des, Src:

 It loads 32-bit pointer from memory source to destination

register and ES.

 The Word is placed in the destination register and the

segment is placed in ES.

 This instruction is very similar to LDS except that it

initializes ES instead of DS.

 E.g.: LES BX, [0301 H]

 LDS Des, Src:

 It loads 32-bit pointer from memory source to destination

register and DS.
  The word is placed in the destination register and the
segment is placed in DS.

 This instruction Copies the word at the lower memory

address to the Des reg and the word at the higher address
to the segment reg i.e. DS.

 E.g.: LDS BX, [0301 H]

 LAHF:

 It copies the lower byte of flag register to AH.

 SAHF:

 It copies the contents of AH to lower byte of flag register.

 PUSHF:

 Pushes flag register to top of stack.

 POPF:

 Pops the stack top to flag register.

Branch/Program Execution Transfer Instructions

 These instructions cause change in the sequence of the

execution of instruction.

 This change can be a conditional or sometimes unconditional.

 The conditions are represented by flags.

 CALL Des:

 This instruction is used to call a subroutine or function or

procedure.
  The address of next instruction after CALL is saved onto
stack.

 RET:

 It returns the control from procedure to calling program.

 Every CALL instruction should have a RET.

 JMP Des:

 This instruction is used for unconditional jump from one

place to another.

 Jxx Des (Conditional Jump):

All the conditional jumps follow some conditional statements

or any instruction that affects the flag

Mnemonic Meaning Jump

Condition

JA Jump if Above CF = 0 and

ZF = 0

JAE Jump if Above or CF = 0

Equal

JB Jump if Below CF = 1

JBE Jump if Below or CF = 1 or ZF

Equal =1
JC Jump if Carry CF = 1

JE Jump if Equal ZF = 1

JNC Jump if Not Carry CF = 0

JNE Jump if Not Equal ZF = 0

JNZ Jump if Not Zero ZF = 0

JPE Jump if Parity PF = 1

Even

JPO Jump if Parity Odd PF = 0

JZ Jump if Zero ZF = 1