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4 Bitgenadder

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2022.surel.sanap
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6 views2 pages

4 Bitgenadder

Uploaded by

2022.surel.sanap
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Name of the Student: Surel Sanap

Class/ Roll Number: D14A / 53


Department: EXTC
Description of Program: The 4-bit generic adder is a Verilog module that dynamically computes
the sum of two 4-bit binary numbers, incorporating a carry input to handle overflow. It utilizes
multiple instances of a 1-bit full adder, organized in a generate block for scalability and
flexibility in width configuration.
Tool used: Xilinx Vivado

RTL Code:
module gen4adder(
a_in,
b_in,
c_in,
sum,
carry
);
parameter width = 4;
input [width-1:0] a_in, b_in;
input c_in;
output [width-1:0] sum;
output carry;
wire [width:0] c_sig;

assign c_sig[0] = c_in;

genvar i;
generate
for (i = 0; i < width; i = i + 1)
begin : add_gen
full_adder_1 UUT(a_in[i], b_in[i], c_sig[i], sum[i],
c_sig[i+1]);
end
endgenerate

assign carry = c_sig[width];

endmodule
Testbench Code:

module tb_gen4adder();
reg [3:0] a_in, b_in;
reg c_in;
wire [3:0] sum;
wire carry;

gen4adder UUT (
.a_in(a_in),
.b_in(b_in),
.c_in(c_in),
.sum(sum),
.carry(carry)
);

initial begin
a_in = 4'b0000;
b_in = 4'b0000;
c_in = 1'b0;
end

always #5 c_in = ~c_in;


always #10 b_in = b_in + 1;
always #160 a_in = a_in + 1;

endmodule

Utilization Summary:

RTL Schematric:

Synthesis Schematic:

Simulation Waveform:

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