VES Institute of Technology

VIVEKANAND EDUCATION SOCIETY’S INSTITUTE OF TECHNOLOGY

DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION ENGINEERING

DIGITAL VLSI
T.E. SEM – V/D14-A
Academic Year 2024-25

Subject Teacher
Mr. Mrugendra Vasmatkar
Asst. Professor,
EXTC Dept.
VESIT

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VIVEKANAND EDUCATION SOCIETY’S INSTITUTE OF TECHNOLOGY

DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION ENGINEERING

Faculty In charge : Mr. Mrugendra M Vasmatkar

Subject : DIGITAL VLSI -LAB
Branch : TE (D14-A)-EXTC (Semester V)
Academic Year : 2024-25

VISION

Towards developing a center of excellence in the field of Electronics and Telecommunication and
to nurture students to become technocrats with a humane outlook

MISSION

 To empower students to meet the growing challenges of industry.

 To promote a cutting-edge research to benefit the society locally and globally.
 To develop young engineers with human and social intellectual qualities required for practices
responsible engineers.

Program Outcomes {PO}:-

Engineering Graduates will be able to:
PO1) Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.

PO2) Problem Analysis: identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.

PO3) Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate consideration
for the public health and safety, and the cultural, societal, and environmental considerations.

PO4) Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.

PO5) Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.

PO6) The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.

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PO7) Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.

PO8) Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.

PO9) Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.

PO10) Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive clear
instructions.

PO11) Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and leader in
a team, to manage projects and in multidisciplinary environments.

PO12) Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

Program Specific Outcomes (PSO)

The EXTC graduates will be able to

i. Apply their electronics and communication fundamentals to develop prototypes using

analysis, synthesis, programming skills and realization.
ii. To demonstrate the ability to develop engineering solutions for modern electronics and
communication problems of the industry.
Recommended Books
1. Sung-Mo Kang and Yusuf Leblebici, ―CMOS Digital Integrated Circuits Analysis and
Design‖, Tata McGraw Hill, 3rd Edition, 2012.
2. P. Uyemura, ―Introduction to VLSI Circuits and Systems‖, John Wiley & Sons.
3. Frank Vahid, ― Digital Design with RTL design, VHDL and VERILOG‖, John Wiley and
Sons Publisher 2011
4. Volnei A. Pedroni ,―Circuit Design and Simulation with VHDL‖, MIT Press, 2nd Edition

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Course Objective:-

1. To become familiar with open source circuit simulation tools like Ngspice, Magic etc.
2. To perform various type of analysis of combinational and sequential CMOS circuits
3. To evaluate performance of given combinational and sequential CMOS circuits
4. To design, implement and verify combinational and sequential CMOS circuits using open
source VLSI design tools.

Course Outcome {CO}:-

After successful completion of the course student will be able to

1. Write spice code for given combinational and sequential CMOS circuits.
2. Perform various analysis like operating point, dc, transient etc of given CMSO circuits.
3. Evaluate performance of given CMOS circuits.
4. Draw layout of given CMOS circuit and also able extract various parasitic using open source
layout tool like Magic.
5. Design, simulate, and verify CMOS circuit for given specifications.

1. Mapping of CO with PO:-

CO/PO PO PO PO PO PO PO PO PO PO PO PO PO
1 2 3 4 5 6 7 8 9 10 11 12
CO-1 3 3 3 3 3 3 - 1 1 3 2 1
CO-2 3 3 3 3 3 3 - 1 1 3 2 -
CO-3 3 3 3 3 3 3 - 1 1 3 2 -
CO-4 3 3 3 3 3 3 - 1 1 3 2 -
CO-5 3 3 3 3 3 3 - 1 1 3 2 -
Total 3 3 3 3 3 3 - 1 1 3 2 1

2. Mapping of CO with PSO:-

PSO/CO CO-1 CO-2 CO-3 CO-4

PSO-1 0 3 3 3
PSO-2 2 2 2 2

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Sr.
Module Contents CO PO/PSO Book
No*
PART A- INTRODUCTION TO XILINX VIVADO and VERILOG CODING
Introduction to VIVADO tool flow – Program, Implement
1. 1,3,4,5 1,2,3,4,5,11,12/1,2 R2
and simulate Full adder VERILOG HDL

2. Program and implement Verilog code for 4-bit adder 1,3,4,5 1,2,3,4,5,11,12/1,2 R2
Program and implement Verilog code for n-bit generic
3. 1,3,4,5 1,2,3,4,5,11,12/1,2 R2
adder
Program and implement Verilog code for Multiplexor and
4. 1,3,4,5 1,2,3,4,5,11,12/1,2 R2
Decoder

5. Program and implement Verilog code DFF and latch 1,3,4,5 1,2,3,4,5,11,12/1,2 R2

Design and implement Verilog program for counter 1,3,45 1,2,3,4,5,11,12/1,2 R2

6.

1,3,45 R2
7. Design and implement Verilog program for shift register 1,2,3,4,5,11,12/1,2

Design and Implement Verilog program for ADD 1,3,5 R2

8. 1,2,3,4,5,11,12/1,2
Accumulate unit
PART B - Schematic and Layout Design
R1
9. Design and implement CMOS inverter schematic, layout. 1,2,3 1,2,3,5/1,2

1,2,3,5/1,2 R1
10. Design and implement CMOS NAND,NOR gate layout 1,2,3

11. Design and implement Transmission Gate schematic, layout 1,3,4,5 1,2,3,4,5,11,12/1,2 R2

12. Design and implement 2:1 MUX schematic, layout 1,3,4,5 1,2,3,4,5,11,12/1,2 R2

13. Design and implement SR latch schematic, Layout 1,3,4,5 1,2,3,4,5,11,12/1,2 R2

*Sr. No – roughly Equivalent to week Number
Digital VLSI LAB CO-PO-PSO Mapping

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INDEX

Sr.
Grad
No Module Contents DOP DOS Sign
e
*
PART A- INTRODUCTION TO XILINX VIVADO and VERILOG CODING
Introduction to VIVADO tool flow – Program,
1.
Implement and simulate Full adder VERILOG HDL
Program and implement Verilog code for 4-bit
2.
adder
Program and implement Verilog code for n-bit
3.
generic adder
Program and implement Verilog code for
4.
Multiplexor and Decoder

5. Program and implement Verilog code DFF and latch

6. Design and implement Verilog program for counter

Design and implement Verilog program for shift

7.
register
Design and Implement Verilog program for ADD
8.
Accumulate unit
PART B - Schematic and Layout Design
Design and implement CMOS inverter schematic,
9.
layout.
Design and implement CMOS NAND,NOR gate
10.
layout
Design and implement Transmission Gate
11.
schematic, layout
12. Design and implement 2:1 MUX schematic, layout

13. Design and implement SR latch schematic, Layout

Subject Teacher

Mr. Mrugendra Vasmatkar

Assistant Professor, EXTC,VESIT

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Instructions to the students:

1. Print Pages from 1 to 7(back-to-back) and attach at the beginning of the

journal
2. Keep all the designs/programs in separate folders as per the format and or-
ganization taught in lab. Prepare your folder in your laptop/computer. Do
not put any data on desktop or C drive.
3. Print header on top of each Design/Program containing Name, Roll No. with
practical batch, Date, Time and Description of the Design. The sample
header shown below
__________________________________________________________________________
%% Name :- Write full name
%% Roll No:- Class:-D14-A/ Batch:-
%% Date :- Time :- Lab time
%% Purpose :-LAYOUT Design of INVERTER using Mentor Graphics
___________________________________________________________________________

4. Get signature of staff regularly after completion of practical and exercise

regularly. Show your journal when faculty asks for it.
5. This journal is divided in 2 parts
a. PART A- INTRODUCTION TO XILINX VIVADO - 50%
b. PART C - SCHEMATIC AND LAYOUT DESIGN - 50%
Total Marks ceiled to 15.
6. There are total 13 experiments.
7. Marks carried by each experiment is mentioned after lab number in each
experiment.
8. Attach prints of the program/schematics/layout/observation and the result
immediately after each lab as required and mentioned in the each lab.
9. Draw this table after each lab.

Format(2) Performance(10) Observation & Total Marks (15)

Conclusion(3)

Remark Signature with date

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