SCHOOL NAME

KIIT Deemed to be University

Bhubaneshwar ,Odisha , India

LABORATORY REPORT ON
TOPIC : ENCODER (OCTAL TO BINARY )

Submitted by :-
POUSHALI PATRA ( 23051517)
RAISA CHAKRABORTY (23051525)
SWASTI SUMAN (23051552)
TANVI MISHRA (23051554)
 OBJECTIVE

Design and Simulation of Octal to Binary Encoder using Verilog HDL.Hardware

implementation of Octal to Binary Encoder using logic gates.

INTRODUCTION

An octal to binary encoder is a digital circuit that converts octal numbers (base-8)
into their binary equivalents (base-2). It has eight inputs representing octal digits 0
to 7 and produces a 3-bit binary output. Encoders are essential in digital systems for
data compression, signal encoding, and interfacing between different systems. The
importance of this lab lies in understanding the fundamental principles of encoding
and the practical implementation of combinational logic circuits.

THEORY

DEFINITION OF AN ENCODER :

An encoder is a combinational circuit that converts multiple input signals into a

coded output signal.An encoder consists of a certain number of input and output
lines. Where, an encoder can have maximum of "2n" input lines whereas "n" output
lines. Hence, an encoder encodes information represented by "2n" input lines with
"n" bits. The block diagram of an encoder is shown in the following figure −
Some of the commonly used types of encoders in digital electronics −

 4 to 2 Encoder
 8 to 3 Encoder (Octal Encoder)
 Decimal to BCD Encoder

Here in this report we shall discuss about an Octal to Binary Encoder.

In the case of an octal to binary encoder, it reduces the number of input lines from
eight to three output lines, effectively encoding the octal digit into binary.This
component is essential in digital systems, especially when interfacing between
devices or systems that use different numbering bases. The fundamental principle
behind the Octal to Binary Encoder is rooted in the binary representation of numbers.
In octal notation, there are eight possible combinations of three bits (000 to 111),
each corresponding to a unique octal digit. The encoder's primary function is to map
each octal input to its corresponding binary output, allowing for seamless data
exchange between octal-based and binary-based systems.

The block diagram of an octal to binary encoder is shown in the following figure −
TRUTH TABLE :

One of the essential aspects of the Octal to Binary Encoder is its truth table, which
provides a systematic representation of the relationship between octal inputs and
binary outputs. The truth table consists of rows, each representing a unique octal
input value ranging from 0 to 7, and columns representing the individual binary bits
that constitute the output. For example, an octal input of 3 would correspond to the
binary output 001.

The following truth table describes the working of an octal to binary encoder -

This truth table serves as a crucial reference for both the design phase, aiding in the
logical circuitry layout, and the simulation phase, enabling the validation of the
Verilog HDL code. It ensures that the encoder accurately performs the conversion of
octal data into the corresponding binary representation, offering compatibility and
reliability in diverse digital applications .
From this truth table, we can write the Boolean expression for the outputs of the
octal to binary encoder as follows :

CIRCUIT DIAGRAM :

In the hardware implementation phase, the digital logic circuit representing the
Octal to Binary Encoder is realized using physical components, primarily logic gates
such as AND gates, OR gates, and NOT gates.
The logic circuit diagram of the octal to binary encoder is shown in the following
figure -
DESCRIPTION OF CIRCUIT COMPONENTS :

 Inputs (I0 to I7): These represent the octal digits.

 AND Gates: Used to combine multiple input signals to produce the necessary
output.
 OR Gates: Aggregate the outputs from the AND gates to form the final binary
output.

HARDWARE IMPLEMENTATION (CIRCUIT DESIGN) :

PIN CONFIGURATION OF 74LS32 QUAD 2-INPUT OR GATE:

The 74LS32 IC contains four independent 2-input OR gates. Each gate has two input
pins and one output pin.
IMPLEMENTATION OF THE ENCODER WITH 74LS32:

To implement the octal to binary encoder using the 74LS32 IC, we can connect the
input lines to the input pins of the OR gates. The output of each OR gate will
correspond to one of the binary output bits.

Breakdown of the connections -

 Input Lines (I0-I7): Connect these to the input pins of the OR gates.
 Output Lines (Y0, Y1, Y2): Connect the outputs of the OR gates to these lines.

Specific Connections -

 Output Y0: Connect the outputs of OR gates 1 and 2 to output Y0.

 Output Y1: Connect the outputs of OR gates 3 and 4 to output Y1.
 Output Y2: Connect the outputs of OR gates 5 and 6 to output Y2.

Note: The remaining OR gate can be left unused or used for other purposes.By
following this configuration, you can effectively implement an octal to binary
encoder using the 74LS32 IC.
 PROCEDURE

For Software Simulation:

a) Create a module with required number of variables and mention it’s input /
output.
b) Write the description of given Boolean function using operators or by using the
built in primitive gates.
c) Synthesize to create RTL Schematic.
d) Create another module referred as test bench to verify the functionality and to
obtain the waveform of input and output.
e) Follow the steps required to simulate the design and compare the obtained
output with the corresponding truth table.

For Hardware Implementation:

a) Turn off the power of the Trainer Kit before constructing any circuit.
b) Connect power supply (+ 5 V DC) pin and ground pin to the respective pins of the
trainer kit.
c) Place the ICs properly on the bread board in the Trainer Kit.
d) Connect VCC and GND pins of each chip to the power supply and ground bus
strips on the bread board.
e) Connect the input and output pins of chips to the input switches and output LEDs
respectively in the Trainer Kit.
f) Check the connections before you turn on the power.
g) Apply various combinations of inputs according to truth tables and observe
outputs of LEDs.
HDL CODE DEVELOPMENT :

Verilog Code for Octal to Binary Encoder using Gate Level Modelling :

module octal_to_binary_encoder (
output Y2,
output Y1,
output Y0,
input I0,
input I1,
input I2,
input I3,
input I4,
input I5,
input I6,
input I7
);
or or1(Y2, I4, I5, I6, I7);
or or2(Y1, I2, I3, I6, I7);
or or3(Y0, I1, I3, I5, I7);
endmodule
OBSERVATION/RESULT :

RTL SCHEMATIC OF OCTAL TO BINARY ENCODER :

TEST BENCH Code for Octal to Binary Encoder :

module test_octal_to_binary_encoder();
reg I0, I1, I2, I3, I4, I5, I6, I7;
wire Y2, Y1, Y0;
octal_to_binary_encoder CKT1(Y2, Y1, Y0, I0, I1, I2, I3, I4, I5, I6, I7); initial
begin
I0 = 1; I1 = 0; I2 = 0; I3 = 0; I4 = 0; I5 = 0; I6 = 0; I7 = 0; #10
I0 = 0; I1 = 1; I2 = 0; I3 = 0; I4 = 0; I5 = 0; I6 = 0; I7 = 0; #10
I0 = 0; I1 = 0; I2 = 1; I3 = 0; I4 = 0; I5 = 0; I6 = 0; I7 = 0; #10
I0 = 0; I1 = 0; I2 = 0; I3 = 1; I4 = 0; I5 = 0; I6 = 0; I7 = 0; #10
I0 = 0; I1 = 0; I2 = 0; I3 = 0; I4 = 1; I5 = 0; I6 = 0; I7 = 0; #10
I0 = 0; I1 = 0; I2 = 0; I3 = 0; I4 = 0; I5 = 1; I6 = 0; I7 = 0; #10
I0 = 0; I1 = 0; I2 = 0; I3 = 0; I4 = 0; I5 = 0; I6 = 1; I7 = 0; #10
I0 = 0; I1 = 0; I2 = 0; I3 = 0; I4 = 0; I5 = 0; I6 = 0; I7 = 1; #10
$finish; // End the simulation
end
endmodule
 OBSERVATION/RESULT

SIMULATED WAVEFORM OF OCTAL TO BINARY ENCODER :

DISCUSSION OF RESULTS :

Reasons of Error:
 Verilog Syntax Errors : A missing semicolon, misspelled keywords, or incorrect
port connections can lead to simulation failures.
 Incorrect Truth Table : If the truth table used to verify the design does not
accurately represent the expected behaviour of the Octal to Binary Encoder,
errors may go undetected.
 Component Failures : In the hardware implementation, components like logic
gates or wires may fail due to manufacturing defects or wear and tear, resulting
in errors.
 Logic Gate Misconfiguration : Errors can result from incorrect interconnections
or configurations of logic gates in the hardware implementation. Improper gate
selections, incorrect signal routing, or malfunctioning components may lead to
inaccurate conversions.
Here we observed that the circuit's performance was dependent on the
implementation method and components used. It's important to note that the
encoder assumes only one active input at a time.

CONCLUSION

This experiment successfully demonstrated the design and implementation of an

Octal to Binary Encoder, emphasizing its crucial role in digital systems. By utilizing
Verilog HDL in conjunction with traditional logic gates, we effectively created an
encoder capable of converting octal inputs into their binary equivalents.

The significance of octal to binary encoding lies in its efficiency in representing data.
Octal, being a base-8 system, serves as a more compact form of binary
representation, simplifying the handling of larger binary numbers. By employing
Verilog HDL for simulation and synthesis, we ensured a robust testing of the
encoder's performance and accuracy.

Ultimately, this experiment underscores the practical applications of octal to binary

encoding in modern digital systems. Its relevance is particularly evident in computing
and memory addressing, where effective data representation is essential for
optimizing performance. By bridging theoretical knowledge with practical
implementation, we highlighted how such encoders enhance data processing
efficiency and contribute to improved digital communication, paving the way for
further innovations in the field.
 STUDENT SIGNATURES

STUDENT NAME ROLL NO SIGNATURE

POUSHALI PATRA 23051517
RAISA CHAKRABORTY 23051525
SWASTI SUMAN 23051552
TANVI MISHRA 23051554

SIGNATURE OF THE CONCERNED LAB FACULTY MEMBER