Review on Analog Circuit Optimization using

Deep Learning algorithm

Ahmed Aziz Elwehili Dalenda Ben Aissa
Microwave Electronics research laboratory, Microwave Electronics research laboratory,
Faculty of Sciences of Tunis Faculty of Sciences of Tunis
Tunis El-Manar University Tunis El-Manar University
Tunis, Tunisia Tunis, Tunisia
[email protected] [email protected]

Abstract—Within many circumstances, analog circuits are technological components expand, innovating circuit designs
made up of intricate pairings of op-amps, resistors, capacitors, becomes more arduous. Figure 1 illustrates the design flow of
and several other fundamental electrical devices. Making analog circuit optimization, depicting the intricate process of
anything as completely flawless, usable, or beneficial as feasible refining and optimizing analog circuits.
is known as optimization. Recent developments in very large-
scale integration (VLSI) techniques have made it possible to
create sophisticated integrated circuits and systems. When it
comes to aspects and areas in wide variations, analog devices are
a significant part of integrated systems. On the other hand,
analog devices play an essential role in modern system
architecture. In this article, we reviewed a wide range of
different optimization approaches in deep learning (DL), analog
2023 22nd Mediterranean Microwave Symposium (MMS) | 979-8-3503-0847-1/23/$31.00 ©2023 IEEE | DOI: 10.1109/MMS59938.2023.10421610

circuit optimization, and its relevant applications. In addition,

significant criteria such as efficiency, latency, performance, and
accuracy are being considered when confirming the outcome. As
a direct consequence of this, the efficiency of deep learning
optimization for analog circuits may be evaluated.

Keywords—Analog circuit, deep learning, very large-

scale integration (VLSI), efficiency, latency, performance, Figure 1: Design flow of analog circuit optimization
accuracy
The advancement of sophisticated circuits necessitates
I. INTRODUCTION
considerable development time, primarily attributed to the
The complexity of advancements in the electronics industry intricate design guidelines and the prevalence of designing
continues to escalate, with a notable focus on the parasitic elements in complex processes. Typically,
development of sophisticated mixed-signal Systems-on-Chip individual designers, who wield significant influence in
(SOC). Given consistent investment and technical crafting such circuit systems, bear the responsibility for this
limitations, contemporary methodologies and approaches for extended development duration. In the quest for meeting
enhancing analog circuit design have been devised. The specified design requirements, professional circuit designers
primary emphasis in development work revolves around are compelled to devise algorithms and iterate over attributes
digitizing the circuit sizing process. This encompasses tasks until a satisfactory solution is achieved. Recognizing the need
ranging from design and configuration to production jobs, to streamline time-consuming processes in a computational
primarily motivated by the perception that circuit and efficient manner has become imperative to reduce time-
measurement constitutes a time-intensive process. Recent to-market. Despite its importance, the technology
years have witnessed validated progress in this domain. The surrounding analog circuit design currently lags behind that
challenge in analog circuit design stems from the absence of of digital systems. The design cycle is frequently impeded by
a clear and organized specification for conceptual design. the optimization of analog components. Analog creation
Despite being a challenging task with varying degrees of poses unique challenges, involving device scaling,
flexibility and diverse evaluation constraints, efforts have architectural considerations, and configuration design. The
predominantly concentrated on the digitalization of the sizing technique, a typically laborious and protracted
circuit size process. The tools and techniques employed to physical process, is reliant on the knowledge and expertise of
address this challenge are largely reliant on robust the developer. The expeditious creation of genuinely high-
mathematical optimization algorithms coupled with analysis performance devices hinges on the ability to automatically
algorithms to assess the potential value of analog circuit optimize the dimensions of analog components. Analog
candidates. These methods commonly involve framing or circuit optimization, encompassing diverse considerations,
modeling the design challenge as an optimization problem, introduces additional complexities. Consequently, we
subsequently resolved through an appropriate technique. undertook a comprehensive review of various approaches
Optimization techniques for analog circuit design, involving deep learning optimization techniques employed in
comprising optimization algorithms and assessment the design of analog circuits.
algorithms utilizing electrical simulations, are frequently
lauded for their unparalleled flexibility. They can be adapted II. RELATED WORK
to various circuit architectures and reliability standards, The article [1] suggested a "domain knowledge-infused
contingent on the chosen devices and systems. As reinforcement learning (DK-IRL)" approach that was

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 supplemented by graphing knowledge to execute the
analog circuit optimization techniques at the pre-layout step. In the study [7] they conducted a detailed review of the latest
This allowed them to locate system components that fulfilled optimization strategies that have been used to improve the
the required circuitry criteria. The method for learning via effectiveness of DNNs on a variety of challenges. This study
reinforcement requires a significant amount of data in also investigates the significance of optimization techniques
addition to a significant amount of computation. The general in the process of developing the ideal hyper-parameters and
equation of RL is given in equation (1) to predict the state architecture of DNNs when enormous amounts of
function of the system. information are considered. Because of the ever-increasing
𝐿𝜋 (𝑠) = 𝐷𝜋 [𝐺𝑡|𝑆𝑡 = 𝑠] (1) need for computational storage and power capacity, it might
The research [2] provided a "supervised pretraining strategy" be difficult to implement this strategy.
for learning circuit models which could be applied to novel The article [8] suggested techniques known as "ensemble
circuit complexity or unheard-of predicting challenges. This empirical mode decomposition (EEMD) and deep belief
method was developed to understand circuitry concepts. It network (DBN)" for the identification of periodic faults in
isn't possible for supervised learning to manage all analog circuits. In the research [9], they demonstrated an
complicated circuits. The mapping function for the improved approach for diagnosing faults in analog circuits
supervised learning strategies is depicted in equation (2) that are focused on a "deep residual network (DRN)". It
𝑝 = 𝑓(𝑞) (2) accomplishes the task of extracting the technical
P is the output variable and q are the input variable. The study specifications of an analog circuit using a ResNet and
[3] introduced RL as well as an outline of its uses in electrical determining the type of fault of a device to actualize the
design automation. Using a deep neural network (DNN), they process of defect detection for a circuit. The study [10]
constructed a hybrid RL and quantitative mixed-size placer, created a technique for defect separation and identification in
which allowed them to get significant benefits with less the circuits that utilized a "convolutional neural network
training process on both publicly available and privately held (CNN)" as well as spectrum analysis. CNN does not encrypt
criteria. In the research article [4], they developed a fault the location and direction in which the circuit is laid up.
diagnostic technique that used a "sine cosine algorithm and a Utilizing the DL approach, an investigation into the
support vector machine (TLSCA-SVM) with transfer categorization of electronic systems was performed
learning". The collection of fault circuits consumes a successfully. A brand-new architecture of CNN is suggested
significant amount of one's period, resources, and financial [11]. Figure 2 shows the general neural network's system
capital. The validity of the diagnosis is impacted because of flow.
these circumstances.
With the support of DL strategies, "analog beam forming"
designs for millimeter wave channels are created and
examined. These systems include large-scale antennas at the
intermediate nodes and small-scale antennas on the admin
console [5]. Analog equipment has emerged as a serious
challenge for the implementation of DL algorithms at the
boundary due to its quick processing rate and electricity
system. There are worries regarding the existence of
analog interference, which affects the strength of the
modeling techniques and produces system losses [6]. The
reinforcement learning algorithm is depicted below. Figure 2: General neural network's system flow
Algorithm 1: Reinforcement learning algorithm In the article [12], a Bayesian optimization approach has been
𝑃: 𝐿 × 𝑇 → ℝ used for design analog circuits. Within the framework of
Requirements: Bayesian optimization, the output assessment is included
Level 𝐿 = {1, … … , 𝑚𝑥 } in the iteration process. The research [13] recommended a
Tasks 𝑇 = {1, … … , 𝑚𝑡 }, 𝑇=𝐿⟹T surrogate-based optimization of analog circuits via the use of
Reward system 𝑅: 𝐿 × 𝑇 → 𝑅 several acquisition processes. It quickly developed into a
Black-box transitional role 𝑇𝑅: 𝐿 × 𝑇 → 𝐿 new issue in the realm of parallel processing.
Learning progression 𝛽 ∈ [0,1], typically 𝛽 = 0.1 The work presented in [14] explored the use of an artificial
Discounting component 𝛿 ∈ [0,1] neural network with supervised learning as a means of
Steps P (L, R, T, TR,𝛿, β) defining an analog and mixed-signal (AMS) regression
Start 𝑃: 𝐿 × 𝑇 → ℝ arbitrarily analysis. In the research study [15], they presented a "rule-
While 𝑃 is not converged do guided genetic algorithm (RG-GA)", for the evolution of
Start in state 𝑠 ∈ 𝐿 analog circuits. Nevertheless, optimizing difficult circuits
While s is not terminal do with restricted option areas continues to be a difficult task.
Calculate 𝜋 according to 𝑃 and exploration strategy The study [16] examined an evolutionary-based designing
𝑝 ← 𝜋(𝑠) approach for automating analog integrated circuit scaling
𝑞 ← 𝑅(𝑠, 𝑝) (ICs). It employed to construct analog integrated circuits with
𝑟′ ← 𝑇𝑅(𝑠, 𝑝) user-defined parameters that are realistic. An evolutionary
𝑃(𝑟 ′ , 𝑝) ← (1 − 𝛽). 𝛽. (𝑞 + 𝛿. 𝑚𝑎𝑥𝑝′ 𝑃(𝑟 ′ . 𝑝′ )) technique does not have an optimal solution. Figure 3
illustrates the working flow of analog circuit optimization.
𝑠 ← 𝑟′

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 The article [17] offered a "synergistic strategic plan" for the [19] Robots, Smart “Situ-in Silico Low energy
rapid development of photonic devices that seems to be sensors algorithm”
[20] Improving “in situ back High
an extremely effective, extremely capable, and accurate physical device Propagation” Computatio
result. This approach combines an "explicit equivalent- n time
circuit-intervened model" as the outline in the underlying DL In the study [19], they invented the concept of physics-aware
technique to prevent blind estimations. To get more accurate learning, which is a "hybrid in situ–in silico technique" that
results needs for a substantial amount of information must be uses a "backpropagation algorithm" to teach controlled
collected. The study article [18] developed a brand-new system components. Nevertheless, the quantity of energy that
method for identifying faults in electronic systems and consumes is becoming an extremely significant barrier to its
spinning equipment by training learnable wavelet scattering sustainability. In the research [20], they improved earlier
systems utilizing time-frequency approximations. methodological concepts by demonstrating in situ
Table 1 shows the summary of the optimization methods backpropagation to perform classification problems for the
published in recent years. initial period and evaluating a novel design to maintain the
Table 1: Summary of modeling of Analog Circuit complete gradient data and upgrade hardware voltage in the
Optimization with Deep Learning Optimization techniques analog domain. It produces costly equipment consequently.
Reference Application- Methods Gap
Device
[1] Game Creation “Reinforcement Need a lot of
learning Algorithm” data &
Computatio
n
[2] Increasing the “Supervised Time
Performance of Pretraining Method” complexity
the circuit
[3] Electronic “Reinforcement It reduces
design learning Algorithm” the Sizes of
automation the Circuits
[4] Fault diagnosis “Transfer learning” Less
accuracy
[5] Perfect “Analog beam Complexity
Antennas forming”
[6] Making perfect “Batch Noise
analog devices Normalization interference
layer”
[7] Deep neural “Optimization Low power
network method” and storage
application
[8] Fault free “empirical mode Performance
circuit decomposition and degradation
deep belief network"
[9] Fault diagnosis “Deep residual Difficult in
of the device network” the detection
of errors
[10] Fault detection "Convolutional It does not
in a circuit neural network" encode the Figure 3: The working flow of analog circuit
location of
the circuit
optimization
[11] Fast working of "Convolutional Lag in
the devices neural network" performance
[12] Efficient “Bayesian Expensive III. SURVEY ON DEEP LEARNING OPTIMIZATION
Working of the optimization Computatio TECHNIQUES-BASED ANALOG CIRCUIT
device technique” nal Cost APPLICATIONS
[13] Concentrate on “Surrogate-based Low
the Sizing of optimization” efficiency
the device The goal of deep learning is to reduce the number of instances
[14] Analog and “Artificial neural Lag in of generalized defects. To use it, designers need to be
mixed-signal network with performance
development supervised conscious of overloading and utilize the optimization
Learning” technique to reduce the number of errors that are introduced
[15] Speeding “Rule-guided Risk in during training. Methods of optimization based on deep
Analog genetic algorithm” Complicated learning are used in analog circuit applications to improve the
Circuits (RG-GA) circuits
[16] Automating the “Evolutionary-based More
system's overall effectiveness. The implementation of this
device for designing” complexity technology leads to robots, efficient transmitters, and sensors,
sizing among other things. Table 2 depicted the summary of the DL
[17] Photonic explicit equivalent- Need a large optimization techniques employed in analog circuit
circuit intervened amount of
applications.
model” data
[18] Fault diagnosis “Wavelet A large
of circuits Scattering” number of
Fault
Classes

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 Table 2: Summary of Deep Learning Optimization IV. COMPARATIVE ANALYSIS
techniques-based Analog Circuit applications The act of making comparisons to each other and identifying
Ref Applicatio Method( Advanta Disadva Contrib
n s) ges ntages ution how they are similar and distinct from one another is known
[21] Powerful rapid Fast No It is as comparative analysis. In this section, we analyze the
transmitter optimiza working change in crucial parameters such as efficiency, latency, performance, and
tion of performa for accuracy for the above-mentioned deep learning optimization
hybrid nce rate "multiple algorithms. They are "domain knowledge-infused
precoder -input
s multiple- reinforcement learning (DK-IRL)", "sine cosine algorithm
output and a support vector machine (TLSCA-SVM) with transfer
(MIMO)" learning", "ensemble empirical mode decomposition
[22] Develops batch increase Dimensio It utilizes (EEMD) and deep belief network (DBN)", "deep residual
multi-core Bayesian effectiven n of the a
environme Optimiz ess device sequentia network (DRN)" and "rule-guided genetic algorithm (RG-
nt. ation l GA)". Figure 5 depicts the performance analysis of the
techniqu updating reviewed techniques.
e technique
.
[23] For toolbox Many More It
simulation in analog time for employs
environme Matlab design computat Expert
nt options ion Design
Plan
[24] Intelligent edge decrease storage It does
robotics, artificial latency and not
wearable intellige processin require
sensors, nce g power cloud
etc. limitation transmiss
s ion
[25] For better Optimiz Designin Propagati It utilizes
5G ation g high- on loss the figure
networks techniqu power of merit
es amplifiers
[26] Advanced Evolutio High Greater It takes
mobile nary accuracy power 6th-
communic algorith consumpt generatio
ation ms ion n Figure 5: Performance analysis
networks
[27] Non- Neurom It is used It It
cognitive orphic in wider computes includes According to figure 5, the techniques DK-IRL, TLSCA-
application compute communi limited computat SVM, EEMD- DBN, DRN, and RG-GA have the efficiency
s rs cation tasks ional value of 95%, 85%, 70%, 78%, and 80% respectively.
kernels Further, latency for all the techniques is comparatively lower
[28] Analog to Sigma- enhancin It It uses
digital Delta g requires the than other optimization techniques. DK-IRL has 55% of
converters Modulat performa an artificial latency, TLSCA-SVM has 50% of latency, EEMD- DBN has
ors nce additiona intelligen 53% of latency, DRN has 45%, and RG-GA has 43% for a
l circuit. ce (AI) better performance of the system. Next to that, for
technique
. comparative analysis, it is essential to check the overall
[29] Object Deep Adequate Lag in It uses performance of the techniques. In that way, the overall
recognitio convolut in network Poisson performance of the system is 85%, 87%, 90%, 88%, and 80%
n ional performa operation encoding for DK-IRL, TLSCA-SVM, EEMD- DBN, DRN, and RG-
spiking nce and
neural convoluti
GA. Moreover, in terms of accuracy, all techniques are
network on effective. The accuracy of DK-IRL has 89%, TLSCA-SVM
encoding has 90%, EEMD- DBN has 92%, DRN has 94%, and RG-GA
strategies has 85%. Finally, the performances are analyzed for the deep
[30] For low- improve It works inadequat It
power d on low- e employed
learning optimization techniques.
circuits Chimps supply converge tunnel
optimize voltage nce field V. CONCLUSION
r effect To enable communication between physical objects and
algorith transistor
m (TFET) electronic equipment, analog circuits are employed to
for strengthen, function, and filter analog outputs before
efficient converting them to binary codes, or the other way around. In
working this article, we reviewed the different approaches of deep
of the
device
learning optimization for the application of analog circuits.
Further, we concentrate on the performance of the mentioned
approach. So, the performance effectiveness of the deep
learning optimization techniques was represented.
Algorithm development and improvement would not be

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