International Conference on Trends in Electronics and Informatics

ICEI 2017

FPGA based Traffic Light Controller

S. Venkata Kishore[1], Vasavi Sreeja[2], Vibhuti Gupta[3], V.Videesha[4], I. B. K. Raju[5] , K. Madhava Rao[6]
[1][2][3][4]
Undergraduate Students, [5] Professor, [6] Assistant Professor
Department of Electronics and Communication Engineering, B V Raju Institute of Technology, Telangana, India
[email protected], [email protected], [email protected] and [email protected].

Abstract— The main purpose of the traffic light control system is architecture of the traffic light controller, section III discusses
to control the congestion of vehicles at the junctions and also for about the hardware setup, section IV gives the obtained
safer pedestrian crossing. There have been many technologies simulation and synthesis results followed by the conclusion in
used for implementing a traffic light controller all over the world. the section V.
India being one of the densely populated countries, upgrading to
a new control system and imposing it all over is a tedious process. II. VLSI ARCHITECTURE FOR THE TRAFFIC LIGHT
This paper proposes the reconfigurable Traffic Light controller CONTROLLER
which can display the time of waiting in all the directions. It has
been observed that the designed traffic light controller is working The paper mainly works on the design of FPGA traffic
up to a maximum operating frequency of about 300 MHz. The light controller for a four-junction road, with two seven
coding has been done using the Verilog Hardware Descriptive segment displays each at the four directions and LED’s for the
Language. red and green lights. A traffic light controller system consists
of three lights (red, green and yellow) in each direction
Keywords— FPGA (Field Programmable Gate Array), Seven generally [11]. The red light indicates stop, green light
segment displays, LEDs (Light Emitting Diodes), traffic control indicates the flow of traffic and yellow light gives caution that
the traffic is going to be stopped in few seconds. In this the
I. INTRODUCTION yellow light is excluded and instead a timer circuit is
Traffic jamming is a critical crisis in many of the cities developed to specify the duration for which the traffic is
and towns all over the world [1]. The congestion of the traffic needed to wait [8]. The traffic light controller is a sequential
has become the cause for many difficulties and challenges in circuit and is modeled as a finite state machine. This contrast
the major and most occupied cities all over the globe. Travel is with respect to four junction road, shown in figure 1.
within the cities to the place of work or recreation has become
a huge issue. This has led to the people losing their time,
money and most essentially the energy resources getting
wearied due to the constant use in the automobiles and other
applications.
Previously, traffic light controller (TLC) has been
implemented using microcontroller. FPGA has many
advantages over the microcontroller that is, it is highly
configurable, performs high speed computations and has more
input output ports necessary for a traffic light controller design
[4].
The Traffic Light System proposed in this project aims
at minimizing the waiting times of vehicles at the traffic
signals [2]. Field programmable gate arrays (FPGAs) are
extensively used in electronic systems, for rapid prototyping
and verification of a conceptual design, especially when the
mass-production of a conventional integrated circuit becomes
prohibitively expensive due to the small quantity [6]. Many
electronic system designs that used to be built in conventional
silicon VLSI are now implemented in Field Programmable
Gate Arrays. Fig. 1. Signals at the Junction.
The paper mainly works on the design of FPGA traffic
light controller for a four-junction road, with two seven A. Proposed Traffic Light Controller
segment displays at the directions and LED’s for the red and
green lights. We have considered four junctions i.e. North, West, South
and East and five states. Initially the TLC is of reset state i.e.
The brief review of the remaining paper is- the section II all the junctions displays red light. When the enable switch
discusses the developed VLSI (Very large scale integration) which is turned on, the TLC will work by transition of states

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ICEI 2017

from S0 to S1for 30 second duration and this cyclic process traffic that needs to be waiting under RED Light is controlled
continues until enable switch is turned low (which is of active by the Timer.
low pin of FPGA).
A four junction road is being considered here– which
When TLC is in S0 state then green light will be turned could be of highway or country road. Equal duration of 30
on at North junction and simultaneously the red lights, along seconds is given to all the roads corresponding to the junction
with their corresponding timers get turned on, at the remaining (North, West, South and East) under GREEN light, in order to
directions. It can be seen that the down count of timer in West clear the corresponding junction’s traffic. This is done by
direction will be 30 seconds and that of South and East switching of the control from junction to another by Finite
directions will be 60 and 90 seconds respectively and this State Machine (FSM).
continues when there is a state transition. The switching of
states and reset button is controlled by the user which is one of In this process when one of the junction is turned on say
the important advantages of this project. Table 1 shows the North junction for 30 seconds GREEN controlled by FSM,
activity of traffic lights and timer across the each direction. then West, South and East are turned RED. The duration of
the traffic that needs to wait in those RED areas is controlled
Table 1–Signals at the junction by decay of Timer for 90, 60 and 30 seconds down count is
seen across the junction West, South and East. This is repeated
and is a cyclic process
STATE DIRECTIONS
In order to view the outputs on the FPGA board the ring
TRANSITIO
N
counter is being used to enable the tri-state buffers so that
NORTH WEST SOUTH EAST when one of the 8 bits of the ring counter value is turned on,
the corresponding buffer is turned on and the output of the
buffer drives the display of the FPGA.
RESET(0000) RED RED RED RED
Since the switching is done at 200 MHz frequency, which
is the input to ring counter, the entire display is seen to be
S0(1000) GREEN RED RED RED turned on of the corresponding junctions. The frequency of
200MHz clock is incorporated to control the ring counter in
(30) (30) (60) (90) order to attain the persistence of vision (Which is used for
multiplexing).
S1(0100) RED GREEN RED RED Once the desired results on FPGA are seen we are
realizing the outputs to TLC model (shown in figure 3) by
(90) (30) (30) (60) incorporating the external hardware (shown in figure 5) to
interface the signals coming out from FPGA board.
S2(0010) RED RED GREEN RED
(60) (90) (30) (30)

S3(0001) RED RED RED GREEN

(30) (60) (90) (30)

B. Internal Architecture of the Traffic Light Controller

The architecture incorporated in the development of the

Traffic Light Controller is shown in Figure 2. The different
internal components employed in the working of it are as
follows:
The system clock of the FPGA is 100MHz and traffic light
controller incorporates the clock of time period of 30 second
duration. This down conversion is taking place by: 100MHz
to1 second duration and from that to 30 second duration.
The 30 second duration signal is given to the Finite State
Machine (FSM) which controls the switching mechanism
across the different junctions.
Two standard signals of a traffic light controller are used
that is RED and GREEN, which carry their usual meanings
that of stop and go respectively. The time duration of the

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Fig. 3. State Diagram for traffic light controller.

III. HARDWARE IMPLEMENTATION

Nexys4 FPGA Develpomental Kit
This paper works on the design of traffic light
controller which is simulated and synthesized in the Xilinx
14.4 version and executed on the Artix7 NEXYS4™ FPGA
developmental kit.

Fig. 2. Internal Architecture of Traffic Light Controller.

Traffic Light Controller is designed on two assumptions. Fig. 4. Artix-7 Nexys4™ FPGA.
Initially Red signal is in all the directions. Now when the
Field Programmable Gate Array (FPGA) from Xilinx.
Reset is made high the North side traffic is allowed to move
With its large, high-capacity FPGA (Xilinx part number
and traffic in all the other directions are stopped. Later the
XC7A100T-1CSG324C), generous external memories, and
traffic in all the other directions is allowed to move in a cyclic
collection of USB, Ethernet, and other ports, the Nexys4 can
manner [3]. The advantage of this particular Traffic Light
host designs ranging from introductory combinational circuits
Controller, is that the modifications can be done easily as per
to powerful embedded processors. Several built-in peripherals,
the requirements i.e., suppose there is traffic on main road and
including an accelerometer, temperature sensor, MEMs digital
the side road, it can be controlled by changing the states
microphone, speaker amplifier and lots of I/O devices allow
accordingly, i.e., when the main road traffic is heavy when
the Nexys4 to be used for a wide range of designs without
compared to the traffic on the side road. Five states have been
needing any other components.
chosen for the finite state machine and the state diagram in
figure 3 depicts the transition from S1 to S0. The Artix-7 FPGA (shown in figure 4) is optimized for
high performance logic, and offers more capacity, higher
performance, and more resources than earlier designs. Artix-7
100T features include:
x 15,850 logic slices, each with four 6-input LUTs and 8
flip-flops
x 4,860 Kbits of fast block RAM
x Six clock management tiles, each with phase-locked
loop (PLL)
x 240 DSP slices
x Internal clock speeds exceeding 450MHz
x On-chip analog-to-digital converter (XADC)
The Nexys4 also offers an improved collection of ports
and peripherals, including:

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x 16 user switches
x USB-UART Bridge
x 12-bit VGA output
x 3-axis accelerometer
x 16Mbyte Cellular RAM
x Pmod for XADC signals
x 16 user LEDs
x Two tri-color LEDs
x PWM audio output
x Temperature sensor
x Serial Flash
x Digilent Adept USB port for programming and data
Fig. 5. External Hardware.
x Two 4-digit 7-segment displays
x Micro SD card connector
x PDM microphone
x 10/100 Ethernet PHY
x Four Pmod ports
x USB HID Host for mice, keyboards and memory sticks

Initially only 2 user switches are utilized to see the

results on FPGA i.e. one is Enable pin (right most switch), to
active the TLC and the other is Reset pin (left most switch).
Here Light Emitting Diodes (LEDs) and 7-segment
displays are used to represent the outputs. The number of
LEDs used is eight which represents four Green and Red
lights across four directions. Similarly, the displays are eight
in number and each direction corresponds to having two
displays. On FPGA the first pair of displays from left Fig. 6. Hardware connections to the FPGA from the PCB.
corresponds to North, West, South and East directions. This is
done by referring to UCF (user constraint file) file of
Nexys4™ FPGA board.
Once the results are satisfied on the FPGA we are
realizing the outputs onto TLC model by changing the UCF
file by utilizing additional ports of FPGA i.e. P-mod ports of
JA, JB and JC. Figure 6 shows the interconnection of FPGA
with external hardware. Figure 7 shows the working model of
TLC.

Fig. 7. Working model of TLC

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IV. RESULTS The following figure shows the logic that has been
realized in the RTL schematic. This is normally done by the
A. Simulation Results tool itself in order to show the input and output pin activity for
The below figure shows the Wave form of the Traffic each and every blocks of the Top Module of TLC.
Light Controller when the test bench is applied to the source
code.

Fig. 8. Simulation Results.

In this waveform the top part of the section consists of the

led control signals across all the four junctions. The middle
part of the waveform contains the control signals of the seven
segment display i.e., “a, b, c, d, e, f and g.” The bottom part
contains the enable and clock signals in order to control the
displays enable pin and the FSM.
B. Synthesis Results
The figure below shows the RTL Schematic diagram of the
Traffic Light Controller of Top Module. The schematic allows
one to view, a technology level representation of one’s HDL,
optimized for specific device architecture, which may be
aiding to discover the design issues early in the design
process. Fig. 10. Inter Logic Blocks of the Schematic.

C. Device utilization summary

This specifies the area that has been utilized, in order to
realize the logic in the Artix-7 Nexys4™ FPGA Board. The
following figure shows the corresponding results.

Fig. 9. Top Module Schematic.

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Fig. 11. Screenshot of device utilization summary. V. CONCLUSION

The implemented traffic light control system controls
D. Timing Report complex traffic in modern cities. This system uses FPGA
This specifies the timing information related to clock which can be configured by designer or user. The very useful
for the operation of the Traffic Light Controller [9]. The application of FPGA is that designer can change the program
following figure gives the timing that has been realized during at any instant which is easy to reprogram as per the
synthesis. requirement [7]. Verilog HDL is used for writing the code
which is dumped on to the FPGA board using Xilinx [9].
Nexys4™ FPGA Board is used as development kit.
In this paper a novel VLSI architecture for the traffic light
controller has been developed and implemented on the Artix7
Nexys4™ FPGA developmental kit which is working at a
maximum operating frequency of 290 MHz This work can be
further extended by reconfiguring the waiting time in all the
four directions at a junction based on the traffic density. The
Fig. 12. Screenshot of Timing summary. FPGA based on which the prototype is designed, has a space
utilization of about 1% approximately and on this basis a
E. Place & Route and Implementation Results single FPGA can be employed to integrate a large number of
The Figure 13 shows the place and route of the logic traffic light controllers at every junction which is efficient and
blocks of TLC inside the FPGA. cost effective.
Future Scope
For future use, the TLC design with FPGA can include
pedestrian crossing lights and also sensors for calculating the
density of the traffic thus allowing the free flow of vehicles.
The reliability of the design can be much enhanced.
Ultimately, a comprehensive and an exceptional TLC design
can be implemented into an embedded circuit board to control
the traffic flow in the city’s traffic intersections.
The future scope of this project is that it can be directly
used in real time applications by employing more number of
such circuits.
ACKNOWLEDGEMENT
We are thankful to our college management for
providing Xilinx tools under university program. This work is
Fig. 13. Screenshot of Place and Route in the FPGA. carried out at the Center for VLSI design at BVRIT.
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