MCP3201

2.7V 12-Bit A/D Converter with SPI Serial Interface

Features Description
• 12-bit resolution The Microchip Technology Inc. MCP3201 device is a
• ±1 LSB max DNL successive approximation 12-bit Analog-to-Digital
• ±1 LSB max INL (MCP3201-B) (A/D) Converter with on-board sample and hold
circuitry. The device provides a single pseudo-differen-
• ±2 LSB max INL (MCP3201-C)
tial input. Differential Nonlinearity (DNL) is specified at
• On-chip sample and hold ±1 LSB, and Integral Nonlinearity (INL) is offered in
• SPI serial interface (modes 0,0 and 1,1) ±1 LSB (MCP3201-B) and ±2 LSB (MCP3201-C)
• Single supply operation: 2.7V - 5.5V versions. Communication with the device is done using
• 100 ksps maximum sampling rate at VDD = 5V a simple serial interface compatible with the SPI
protocol. The device is capable of sample rates of up to
• 50 ksps maximum sampling rate at VDD = 2.7V
100 ksps at a clock rate of 1.6 MHz. The MCP3201
• Low power CMOS technology device operates over a broad voltage range (2.7V -
• 500 nA typical standby current, 2 µA maximum 5.5V). Low-current design permits operation with
• 400 µA maximum active current at 5V typical standby and active currents of only 500 nA and
• Industrial temp range: -40°C to +85°C 300 µA, respectively. The device is offered in 8-pin
• 8-pin MSOP, PDIP, SOIC and TSSOP packages MSOP, PDIP, TSSOP and 150 mil SOIC packages.

Applications Package Types

• Sensor Interface MSOP, PDIP, SOIC, TSSOP
• Process Control
• Data Acquisition
VREF 1 8 VDD
• Battery Operated Systems MCP3201
IN+ 2 7 CLK
Functional Block Diagram IN– 3 6 DOUT
VSS 4 5 CS/SHDN
VDD VSS
VREF

DAC

Comparator

IN+ Sample 12-Bit SAR

and
IN- Hold

Shift
Control Logic
Register

CS/SHDN CLK DOUT

© 2008 Microchip Technology Inc. DS21290E-page 1

MCP3201
NOTES:

DS21290E-page 2 © 2008 Microchip Technology Inc.

 MCP3201
1.0 ELECTRICAL †Notice: Stresses above those listed under “Maximum
ratings” may cause permanent damage to the device. This is
CHARACTERISTICS a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
1.1 Maximum Ratings† operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
VDD...................................................................................7.0V may affect device reliability.
All inputs and outputs w.r.t. VSS ................ -0.6V to VDD +0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
ESD protection on all pins (HBM) .................................> 4 kV

ELECTRICAL CHARACTERISTICS
Electrical Specifications: All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 100 ksps, and
fCLK = 16*fSAMPLE, unless otherwise noted.
Parameter Sym Min Typ Max Units Conditions
Conversion Rate:
Conversion Time tCONV — — 12 clock
cycles
Analog Input Sample Time tSAMPLE 1.5 clock
cycles
Throughput Rate fSAMPLE — — 100 ksps VDD = VREF = 5V
50 ksps VDD = VREF = 2.7V
DC Accuracy:
Resolution 12 bits
Integral Nonlinearity INL — ±0.75 ±1 LSB MCP3201-B
— ±1 ±2 LSB MCP3201-C
Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes over
temperature
Offset Error — ±1.25 ±3 LSB
Gain Error — ±1.25 ±5 LSB
Dynamic Performance:
Total Harmonic Distortion THD — -82 — dB VIN = 0.1V to 4.9V@1 kHz
Signal to Noise and Distortion SINAD — 72 — dB VIN = 0.1V to 4.9V@1 kHz
(SINAD)
Spurious Free Dynamic Range SFDR — 86 — dB VIN = 0.1V to 4.9V@1 kHz
Reference Input:
Voltage Range 0.25 — VDD V Note 2
Current Drain — 100 150 µA
— .001 3 µA CS = VDD = 5V
Analog Inputs:
Input Voltage Range (IN+) IN+ IN- — VREF+IN- V
Input Voltage Range (IN-) IN- VSS-100 VSS+100 mV
Leakage Current — 0.001 ±1 µA
Switch Resistance RSS — 1K — W See Figure 4-1
Sample Capacitor CSAMPLE — 20 — pF See Figure 4-1
Digital Input/Output:
Data Coding Format Straight Binary
High Level Input Voltage VIH 0.7 VDD — — V
Low Level Input Voltage VIL — — 0.3 VDD V
Note 1: This parameter is established by characterization and not 100% tested.
2: See graph that relates linearity performance to VREF level.
3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.

© 2008 Microchip Technology Inc. DS21290E-page 3

MCP3201
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 100 ksps, and
fCLK = 16*fSAMPLE, unless otherwise noted.
Parameter Sym Min Typ Max Units Conditions
High Level Output Voltage VOH 4.1 — — V IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage VOL — — 0.4 V IOL = 1 mA, VDD = 4.5V
Input Leakage Current ILI -10 — 10 µA VIN = VSS or VDD
Output Leakage Current ILO -10 — 10 µA VOUT = VSS or VDD
Pin Capacitance CIN, COUT — — 10 pF VDD = 5.0V (Note 1)
(all inputs/outputs) TA = +25°C, f = 1 MHz
Timing Parameters:
Clock Frequency fCLK — — 1.6 MHz VDD = 5V (Note 3)
— — 0.8 MHz VDD = 2.7V (Note 3)
Clock High Time tHI 312 — — ns
Clock Low Time tLO 312 — — ns
CS Fall To First Rising CLK Edge tSUCS 100 — — ns
CLK Fall To Output Data Valid tDO — — 200 ns See Test Circuits, Figure 1-2
CLK Fall To Output Enable tEN — — 200 ns See Test Circuits, Figure 1-2
CS Rise To Output Disable tDIS — — 100 ns See Test Circuits, Figure 1-2
(Note 1)
CS Disable Time tCSH 625 — — ns
DOUT Rise Time tR — — 100 ns See Test Circuits, Figure 1-2
(Note 1)
DOUT Fall Time tF — — 100 ns See Test Circuits, Figure 1-2
(Note 1)
Power Requirements:
Operating Voltage VDD 2.7 — 5.5 V
Operating Current IDD — 300 400 µA VDD = 5.0V, DOUT unloaded
— 210 — µA VDD = 2.7V, DOUT unloaded
Standby Current IDDS — 0.5 2 µA CS = VDD = 5.0V
Note 1: This parameter is established by characterization and not 100% tested.
2: See graph that relates linearity performance to VREF level.
3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.

TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA -40 — +85 °C
Operating Temperature Range TA -40 — +85 °C
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-MSOP θJA — 211 — °C/W
Thermal Resistance, 8L-PDIP θJA — 89.5 — °C/W
Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W
Thermal Resistance, 8L-TSSOP θJA — 139 — °C/W

DS21290E-page 4 © 2008 Microchip Technology Inc.

 MCP3201

tCSH

CS
tSUCS
tHI tLO

CLK
tEN tDO tDIS
tR tF

DOUT HI-Z HI-Z

NULL BIT MSB OUT LSB

FIGURE 1-1: Serial Timing.

Load circuit for tR, tF, tDO Load circuit for tDIS and tEN

1.4V Test Point

VDD
tDIS Waveform 2
3 kΩ Test Point 3 kΩ VDD/2
DOUT DOUT tEN Waveform

CL = 30 pF 30 pF tDIS Waveform 1
VSS

Voltage Waveforms for tR, tF Voltage Waveforms for tEN

VOH
DOUT VOL
CS
tR tF 1 2 3 4
CLK

DOUT B9

tEN

Voltage Waveforms for tDO Voltage Waveforms for tDIS

CS VIH
CLK
DOUT 90%
tDO Waveform 1*
tDIS
DOUT
DOUT 10%
Waveform 2†
* Waveform 1 is for an output with internal condi-
tions such that the output is high, unless disabled
by the output control.
† Waveform 2 is for an output with internal condi-
tions such that the output is low, unless disabled
by the output control.

FIGURE 1-2: Test Circuits.

© 2008 Microchip Technology Inc. DS21290E-page 5

MCP3201
NOTES:

DS21290E-page 6 © 2008 Microchip Technology Inc.

 MCP3201
2.0 TYPICAL PERFORMANCE CHARACTERISTICS
Note: The graphs provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only. The performance characteristics listed herein are not
tested or guaranteed. In some graphs, the data presented may be outside the specified operating range
(e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.

1.0 2.0
VDD = VREF = 2.7V
0.8 Positive INL
1.5
0.6
0.4 1.0
Positive INL
INL (LSB)

INL (LSB)
0.2 0.5
0.0 0.0
-0.2 Negative INL -0.5
-0.4 Negative INL
-0.6 -1.0
-0.8 -1.5
-1.0 -2.0
0 25 50 75 100 125 150 0 20 40 60 80 100
Sample Rate (ksps) Sample Rate (ksps)

FIGURE 2-1: Integral Nonlinearity (INL) FIGURE 2-4: Integral Nonlinearity (INL)
vs. Sample Rate. vs. Sample Rate (VDD = 2.7V).

2.0 2.0
VDD = 2.7V
1.5 1.5 FSAMPLE = 50 ksps
1.0 1.0 Positive INL
Positive INL
INL (LSB)
INL (LSB)

0.5 0.5
0.0 0.0
-0.5 Negative INL -0.5
-1.0 -1.0 Negative INL

-1.5 -1.5
-2.0 -2.0
0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
VREF (V) VREF (V)

FIGURE 2-2: Integral Nonlinearity (INL) FIGURE 2-5: Integral Nonlinearity (INL)
vs. VREF. vs. VREF (VDD = 2.7V).

1.0
1.0
0.8 VDD = VREF = 2.7V
0.8
0.6 FSAMPLE = 50 ksps
0.6
0.4
0.4
INL (LSB)

0.2
INL (LSB)

0.2
0.0 0.0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096
Digital Code
Digital Code
FIGURE 2-3: Integral Nonlinearity (INL) FIGURE 2-6: Integral Nonlinearity (INL)
vs. Code (Representative Part). vs. Code (Representative Part, VDD = 2.7V).

© 2008 Microchip Technology Inc. DS21290E-page 7

MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.

1.0 1.0
VDD = VREF = 2.7V
0.8 Positive INL 0.8
FSAMPLE = 50 ksps
0.6 0.6 Positive INL
0.4 0.4
INL (LSB)

INL (LSB)
0.2 0.2
0.0 0.0
-0.2 Negative INL -0.2
-0.4 -0.4
Negative INL
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100

Temperature (°C) Temperature (°C)

FIGURE 2-7: Integral Nonlinearity (INL) FIGURE 2-10: Integral Nonlinearity (INL)
vs. Temperature. vs. Temperature (VDD = 2.7V).

1.0 2.0
0.8 VDD = VREF = 2.7V
1.5
0.6
0.4 1.0
Positive DNL
DNL (LSB)

Positive DNL
0.2 DNL (LSB) 0.5
0.0 0.0
-0.2
-0.5 Negative DNL
-0.4 Negative DNL
-1.0
-0.6
-0.8 -1.5
-1.0 -2.0
0 25 50 75 100 125 150 0 20 40 60 80 100
Sample Rate (ksps) Sample Rate (ksps)

FIGURE 2-8: Differential Nonlinearity FIGURE 2-11: Differential Nonlinearity

(DNL) vs. Sample Rate. (DNL) vs. Sample Rate (VDD = 2.7V).

3.0 3.0
VDD = 2.7V
2.0 FSAMPLE = 50 ksps
2.0
Positive DNL
DNL (LSB)

1.0
DNL (LSB)

1.0 Positive DNL

0.0
0.0
-1.0 Negative DNL
Negative DNL
-1.0 -2.0

-2.0 -3.0
0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0

VREF (V) VREF(V)

FIGURE 2-9: Differential Nonlinearity FIGURE 2-12: Differential Nonlinearity

(DNL) vs. VREF. (DNL) vs. VREF (VDD = 2.7V).

DS21290E-page 8 © 2008 Microchip Technology Inc.

 MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.

1.0 1.0
VDD = VREF = 2.7V
0.8 0.8 F
SAMPLE = 50 ksps
0.6 0.6
0.4 0.4
DNL (LSB)

DNL (LSB)
0.2 0.2
0.0 0.0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096
Digital Code Digital Code

FIGURE 2-13: Differential Nonlinearity FIGURE 2-16: Differential Nonlinearity

(DNL) vs. Code (Representative Part). (DNL) vs. Code (Representative Part,
VDD = 2.7V).

1.0 1.0
0.8 0.8 VDD = 2.7V
FSAMPLE = 50ksps
0.6 0.6
0.4 Positive DNL 0.4 Positive DNL
DNL (LSB)

DNL (LSB)
0.2 0.2
0.0 0.0
-0.2 -0.2
Negative DNL -0.4 Negative DNL
-0.4
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)

FIGURE 2-14: Differential Nonlinearity FIGURE 2-17: Differential Nonlinearity

(DNL) vs. Temperature. (DNL) vs. Temperature (VDD = 2.7V).

5 20
18
4
16 V DD = 5V
Offset Error (LSB)

VDD = 2.7V
Gain Error (LSB)

3 14 FSAMPLE = 100 ksps

FSAMPLE = 50 ksps 12
2
10
1 8
V DD = 2.7V
0 6
VDD = 5V FSAMPLE = 50ksps
4
-1 FSAMPLE = 100 ksps 2
-2 0
0 1 2 3 4 5 0 1 2 3 4 5

VREF(V) VREF (V)

FIGURE 2-15: Gain Error vs. VREF. FIGURE 2-18: Offset Error vs. VREF.

© 2008 Microchip Technology Inc. DS21290E-page 9

MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.

1.0 2.0
0.8 1.8
0.6 1.6 VDD = VREF = 5V

Offset Error (LSB)

VDD = VREF = 2.7V
Gain Error (LSB)

FSAMPLE = 50 ksps 1.4 FSAMPLE = 100 ksps

0.4
0.2 1.2
0.0 1.0
-0.2 0.8 VDD = VREF = 2.7V
-0.4 0.6 FSAMPLE = 50 ksps
-0.6 0.4
VDD = VREF = 5V
-0.8 0.2
FSAMPLE = 100 ksps
-1.0 0.0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)

FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Offset Error vs.
Temperature.

100 100
VDD = VREF = 5V VDD = VREF = 5V
90 90 FSAMPLE = 100 ksps
FSAMPLE = 100 ksps
80 80
70 70
SINAD (dB)
SNR (dB)

60 60
50 50 VDD = VREF = 2.7V
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
40 FSAMPLE = 50 ksps 40
30 30
20 20
10 10
0 0
1 10 100 1 10 100
Input Frequency (kHz) Input Frequency (kHz)

FIGURE 2-20: Signal-to-Noise Ratio (SNR) FIGURE 2-23: Signal-to-Noise and

vs. Input Frequency. Distortion (SINAD) vs. Input Frequency.

0
80
-10 VDD = VREF = 5V
-20 70 FSAMPLE = 100 ksps
-30 60
SINAD (dB)
THD (dB)

-40 VDD = VREF = 2.7V 50 VDD = VREF = 2.7V

-50 FSAMPLE = 50 ksps
40 FSAMPLE = 50 ksps
-60
30
-70
20
-80
-90 VDD = VREF = 5V, FSAMPLE = 100 ksps 10
-100 0
1 10 100 -40 -35 -30 -25 -20 -15 -10 -5 0
Input Frequency (kHz) Input Signal Level (dB)

FIGURE 2-21: Total Harmonic Distortion FIGURE 2-24: Signal-to-Noise and

(THD) vs. Input Frequency. Distortion (SINAD) vs. Input Signal Level.

DS21290E-page 10 © 2008 Microchip Technology Inc.

 MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.

12.0
12.00 V DD = 5V
11.75 11.5
FSAMPLE = 100 ksps
11.50
11.0
11.25

ENOB (rms)
ENOB (rms)

11.00 VDD = VREF = 5V 10.5

10.75
FSAMPLE =100 ksps 10.0
10.50 VDD = VREF = 2.7V
10.25
FSAMPLE = 50 ksps 9.5
10.00
9.75 9.0 VDD = 2.7V
9.50
9.25 8.5 FSAMPLE = 50 ksps
9.00 8.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100

VREF (V) Input Frequency (kHz)

FIGURE 2-25: Effective Number of Bits FIGURE 2-28: Effective Number of Bits
(ENOB) vs. VREF. (ENOB) vs. Input Frequency.

100 0

Power Supply Rejection (dB)

90 VDD = VREF = 5V, FSAMPLE = 100 ksps -10
80 -20
70
SFDR (dB)

-30
60
50 -40
40 VDD = VREF = 2.7V -50
FSAMPLE = 50 ksps
30 -60
20
-70
10
0 -80
1 10 100 1 10 100 1000 10000
Input Frequency (kHz) Ripple Frequency (kHz)

FIGURE 2-26: Spurious Free Dynamic FIGURE 2-29: Power Supply Rejection
Range (SFDR) vs. Input Frequency. (PSR) vs. Ripple Frequency.

0 0
-10 VDD = VREF = 5V -10 VDD = VREF = 2.7V
-20 FSAMPLE = 100 ksps -20 FSAMPLE = 50 ksps
-30 FINPUT = 9.985kHz -30 FINPUT = 998.76 Hz
Amplitude (dB)

Amplitude (dB)

-40 4096 points -40 4096 points

-50 -50
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
0 10000 20000 30000 40000 50000 0 5000 10000 15000 20000 25000
Frequency (Hz) Frequency (Hz)

FIGURE 2-27: Frequency Spectrum of FIGURE 2-30: Frequency Spectrum of

10 kHz input (Representative Part). 1 kHz input (Representative Part, VDD = 2.7V).

© 2008 Microchip Technology Inc. DS21290E-page 11

MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.

500 100
VREF = VDD VREF = VDD
450 90
All points at FCLK = 1.6 MHz, except All points at FCLK = 1.6 MHz, except
400 at VREF = VDD = 2.5V, FCLK = 800 kHz 80 at VREF = VDD = 2.5V, FCLK = 800 kHz
350 70
IDD (µA)

IREF (µA)
300 60
250 50
200 40
150 30
100 20
50 10
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V) VDD (V)

FIGURE 2-31: IDD vs. VDD. FIGURE 2-34: IREF vs. VDD.

100
400
90 VDD = V REF = 5V
350 80
300 VDD = VREF = 5V
70

IREF (µA)
250 60
IDD (µA)

200 50

VDD = VREF = 2.7V 40

150
30 VDD = VREF = 2.7V
100
20
50 10
0 0
10 100 1000 10000 10 100 1000 10000
Clock Frequency (kHz)
Clock Frequency (kHz)
FIGURE 2-32: IDD vs. Clock Frequency. FIGURE 2-35: IREF vs. Clock Frequency.

400 100
VDD = VREF = 5V
350 VDD = VREF = 5V 90
FCLK = 1.6 MHz
FCLK = 1.6 MHz 80
300
70
250
IREF (µA)
IDD (µA)

60
200 50
150 VDD = VREF = 2.7V 40
FCLK = 800 kHz 30
100 VDD = VREF = 2.7V
20 FCLK = 800 kHz
50 10
0 0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)

FIGURE 2-33: IDD vs. Temperature. FIGURE 2-36: IREF vs. Temperature.

DS21290E-page 12 © 2008 Microchip Technology Inc.

 MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.

80 2.0

Analog Input Leakage (nA)

VREF = CS = VDD VDD = VREF = 5V
70 1.8
FCLK = 1.6 MHz
1.6
60
1.4
IDDS (pA)

50
1.2
40 1.0
30 0.8
20 0.6
0.4
10
0.2
0 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100
VDD (V) Temperature (°C)

FIGURE 2-37: IDDS vs. VDD. FIGURE 2-39: Analog Input Leakage
Current vs. Temperature.
100.00
VDD = VREF = CS = 5V

10.00
I DDS (nA)

1.00

0.10

0.01
-50 -25 0 25 50 75 100
Temperature (°C)

FIGURE 2-38: IDDS vs. Temperature.

© 2008 Microchip Technology Inc. DS21290E-page 13

MCP3201
NOTES:

DS21290E-page 14 © 2008 Microchip Technology Inc.

 MCP3201
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follows.

TABLE 3-1: PIN FUNCTION TABLE

MCP3201

MSOP, PDIP, SOIC, Symbol Description

TSSOP
1 VREF Reference Voltage Input
2 IN+ Positive Analog Input
3 IN- Negative Analog Input
4 VSS Ground
5 CS/SHDN Chip Select/Shutdown Input
6 DOUT Serial Data Out
7 CLK Serial Clock
8 VDD +2.7V to 5.5V Power Supply

3.1 Positive Analog Input (IN+) 3.4 Serial Clock (CLK)

Positive analog input. This input can vary from IN- to The SPI clock pin is used to initiate a conversion and to
VREF + IN-. clock out each bit of the conversion as it takes place.
See Section 6.2 “Maintaining Minimum Clock
3.2 Negative Analog Input (IN-) Speed” for constraints on clock speed.

Negative analog input. This input can vary ±100 mV 3.5 Serial Data Output (DOUT)
from VSS.
The SPI serial data output pin is used to shift out the
3.3 Chip Select/Shutdown (CS/SHDN) results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
The CS/SHDN pin is used to initiate communication takes place.
with the device when pulled low and will end a
conversion and put the device in low power standby
when pulled high. The CS/SHDN pin must be pulled
high between conversions.

© 2008 Microchip Technology Inc. DS21290E-page 15

MCP3201
NOTES:

DS21290E-page 16 © 2008 Microchip Technology Inc.

 MCP3201
4.0 DEVICE OPERATION 4.2 Reference Input
The MCP3201 A/D Converter employs a conventional The reference input (VREF) determines the analog input
SAR architecture. With this architecture, a sample is voltage range and the LSB size, as shown below.
acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the first rising edge of the EQUATION 4-1:
serial clock after CS has been pulled low. Following this
sample time, the input switch of the converter opens V REF
LSB Size = ------------
-
and the device uses the collected charge on the 4096
internal sample and hold capacitor to produce a serial
12-bit digital output code. Conversion rates of 100 ksps As the reference input is reduced, the LSB size is
are possible on the MCP3201 device. See Section 6.2 reduced accordingly. The theoretical digital output code
“Maintaining Minimum Clock Speed” for information produced by the A/D Converter is a function of the
on minimum clock rates. Communication with the analog input signal and the reference input as shown
device is done using a 3-wire SPI-compatible interface. below.

4.1 Analog Inputs EQUATION 4-2:

The MCP3201 device provides a single pseudo-differ- 4096*V IN
Digital Output Code = -----------------------
-
ential input. The IN+ input can range from IN- to VREF V REF
(VREF + IN-). The IN- input is limited to ±100 mV from
the VSS rail. The IN- input can be used to cancel small Where:
signal common-mode noise which is present on both
the IN+ and IN- inputs. VIN = Analog Input Voltage = V(IN+) - V(IN-)
VREF = Reference Voltage
For the A/D Converter to meet specification, the charge
holding capacitor (CSAMPLE) must be given enough
time to acquire a 12-bit accurate voltage level during When using an external voltage reference device, the
the 1.5 clock cycle sampling period. The analog input system designer should always refer to the
model is shown in Figure 4-1. manufacturer’s recommendations for circuit layout.
In this diagram, it is shown that the source impedance Any instability in the operation of the reference device
(RS) adds to the internal sampling switch (RSS) will have a direct effect on the operation of the
impedance, directly affecting the time that is required to A/D Converter.
charge the capacitor (CSAMPLE). Consequently, a
larger source impedance increases the offset, gain,
and integral linearity errors of the conversion.
Ideally, the impedance of the signal source should be
near zero. This is achievable with an operational
amplifier such as the MCP601, which has a closed loop
output impedance of tens of ohms. The adverse affects
of higher source impedances are shown in Figure 4-2.
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[VREF + (IN-)] - 1 LSB}, then the
output code will be FFFh. If the voltage level at IN- is
more than 1 LSB below VSS, then the voltage level at
the IN+ input will have to go below VSS to see the 000h
output code. Conversely, if IN- is more than 1 LSB
above VSS, then the FFFh code will not be seen unless
the IN+ input level goes above VREF level.

© 2008 Microchip Technology Inc. DS21290E-page 17

MCP3201

VDD
Sampling
Switch
VT = 0.6V
RSS CHx SS RS = 1 kΩ

CSAMPLE
VA CPIN ILEAKAGE = DAC capacitance
VT = 0.6V
7 pF ±1 nA = 20 pF

VSS

LEGEND
VA = Signal Source
RSS = Source Impedance
CHx = Input Channel Pad
CPIN = Input Pin Capacitance
VT = Threshold Voltage
ILEAKAGE = Leakage Current At The Pin
Due To Various Junctions
SS = Sampling Switch
RS = Sampling Switch Resistor
CSAMPLE = Sample/hold Capacitance

FIGURE 4-1: Analog Input Model.

1.8
1.6 VDD = VREF = 5V
Clock Frequency (MHz)

1.4
1.2
1.0
0.8
0.6 VDD = VREF = 2.7V

0.4
0.2
0.0
100 1000 10000

Input Resistance (Ohms)

FIGURE 4-2: Maximum Clock Frequency

vs. Input Resistance (RS) to maintain less than a
0.1 LSB deviation in INL from nominal
conditions.

DS21290E-page 18 © 2008 Microchip Technology Inc.

 MCP3201
5.0 SERIAL COMMUNICATIONS
Communication with the device is done using a
standard SPI-compatible serial interface. Initiating
communication with the MCP3201 device begins with
the CS going low. If the device was powered up with the
CS pin low, it must be brought high and back low to
initiate communication. The device will begin to sample
the analog input on the first rising edge after CS goes
low. The sample period will end in the falling edge of the
second clock, at which time the device will output a low
null bit. The next 12 clocks will output the result of the
conversion with MSB first, as shown in Figure 5-1. Data
is always output from the device on the falling edge of
the clock. If all 12 data bits have been transmitted and
the device continues to receive clocks while the CS is
held low, the device will output the conversion result
LSB first, as shown in Figure 5-2. If more clocks are
provided to the device while CS is still low (after the
LSB first data has been transmitted), the device will
clock out zeros indefinitely.

tCYC

TCSH
CS

TSUCS
POWER
DOWN
CLK
TSAMPLE
tCONV tDATA**
HI-Z NULL B11 B10 B9 HI-Z NULL B11 B10 B9
DOUT BIT B8 B7 B6 B5 B4 B3 B2 B1 B0* BIT B8

* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed
by zeros indefinitely. See Figure 5-2 below.
** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high-impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.

FIGURE 5-1: Communication with MCP3201 device using MSB first Format.

tCYC

tCSH
CS

tSUCS POWER DOWN

CLK
tSAMPLE
tCONV tDATA**
DOUT HI-Z NULL B11B10B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11* HI-Z
BIT

* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.
** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high-impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.

FIGURE 5-2: Communication with MCP3201 device using LSB first Format.

© 2008 Microchip Technology Inc. DS21290E-page 19

MCP3201
NOTES:

DS21290E-page 20 © 2008 Microchip Technology Inc.

 MCP3201
6.0 APPLICATIONS INFORMATION been sent to the device, the microcontroller’s receive
buffer will contain two unknown bits (the output is at
high-impedance for the first two clocks), the null bit and
6.1 Using the MCP3201 Device with
the highest order five bits of the conversion. After the
Microcontroller SPI Ports second eight clocks have been sent to the device, the
With most microcontroller SPI ports, it is required to MCU receive register will contain the lowest-order
clock out eight bits at a time. If this is the case, it will be seven bits and the B1 bit repeated as the A/D
necessary to provide more clocks than are required for Converter has begun to shift out LSB first data with the
the MCP3201. As an example, Figure 6-1 and extra clock. Typical procedure would then call for the
Figure 6-2 show how the MCP3201 device can be lower-order byte of data to be shifted right by one bit to
interfaced to a microcontroller with a standard SPI port. remove the extra B1 bit. The B7 bit is then transferred
Since the MCP3201 always clocks data out on the from the high-order byte to the lower-order byte, and
falling edge of clock, the MCU SPI port must be then the higher-order byte is shifted one bit to the right
configured to match this operation. SPI Mode 0,0 as well. Easier manipulation of the converted data can
(clock idles low) and SPI Mode 1,1 (clock idles high) be obtained by using this method.
are both compatible with the MCP3201. Figure 6-1 Figure 6-2 shows the same thing in SPI Mode 1,1
depicts the operation shown in SPI Mode 0,0, which which requires that the clock idles in the high state. As
requires that the CLK from the microcontroller idles in with mode 0,0, the A/D Converter outputs data on the
the ‘low’ state. As shown in the diagram, the MSB is falling edge of the clock and the MCU latches data from
clocked out of the A/D Converter on the falling edge of the A/D Converter in on the rising edge of the clock.
the third clock pulse. After the first eight clocks have

CS
MCU latches data from A/D
Converter on rising edges of SCLK

CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Data is clocked out of A/D

Converter on falling edges

HI-Z NULL B11 B10 HI-Z

DOUT BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2

LSB first data begins

to come out
? ? 0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1

Data stored into MCU receive register Data stored into MCU receive register
after transmission of first 8 bits after transmission of second 8 bits

FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).

CS
MCU latches data from A/D
Converter on rising edges of SCLK
CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Data is clocked out of A/D

Converter on falling edges

HI-Z NULL B11 B10 B9 HI-Z

DOUT B8 B7 B6 B5 B4 B3 B2 B1 B0 B1
BIT
LSB first data begins
to come out
? ? 0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1

Data stored into MCU receive register Data stored into MCU receive register
after transmission of first 8 bits after transmission of second 8 bits

FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).

© 2008 Microchip Technology Inc. DS21290E-page 21

MCP3201
6.2 Maintaining Minimum Clock Speed
VDD
When the MCP3201 initiates the sample period, charge 10 µF
4.096V
is stored on the sample capacitor. When the sample Reference
period is complete, the device converts one bit for each
0.1 µF 10 µF
clock that is received. It is important for the user to note MCP1541
that a slow clock rate will allow charge to bleed off the CL
1 µF
sample cap while the conversion is taking place. At VREF
85°C (worst case condition), the part will maintain IN+

proper charge on the sample capacitor for at least MCP3201

1.2 ms after the sample period has ended. This means C1 MCP601 IN-
R1
that the time between the end of the sample period and VIN +
the time that all 12 data bits have been clocked out R2
-
must not exceed 1.2 ms (effective clock frequency of C2
10 kHz). Failure to meet this criteria may induce R4
R3
linearity errors into the conversion outside the rated
specifications. It should be noted that during the entire
conversion cycle, the A/D Converter does not require a
constant clock speed or duty cycle, as long as all timing FIGURE 6-3: The MCP601 Operational
specifications are met. Amplifier is used to implement a 2nd order anti-
aliasing filter for the signal being converted by
6.3 Buffering/Filtering the Analog the MCP3201 device.
Inputs
If the signal source for the A/D Converter is not a low
impedance source, it will have to be buffered
or inaccurate conversion results may occur.
See Figure 4-2. It is also recommended that a filter be
used to eliminate any signals that may be aliased back
into the conversion results. This is illustrated in
Figure 6-3 where an op amp is used to drive the analog
input of the MCP3201 device. This amplifier provides a
low impedance source for the converter input and a
low-pass filter, which eliminates unwanted high-
frequency noise.
Low-pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab® software. FilterLab
will calculate capacitor and resistor values, as well as
determine the number of poles that are required for the
application. For more information on filtering signals,
see the application note AN699 “Anti-Aliasing Analog
Filters for Data Acquisition Systems.”

DS21290E-page 22 © 2008 Microchip Technology Inc.

 MCP3201
6.4 Layout Considerations
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor should
always be used with this device and should be placed
as close as possible to the device pin. A bypass
capacitor value of 1 µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high-
frequency signals (such as clock lines) as far as
possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using A/D Converter, refer to AN688 “Layout
Tips for 12-Bit A/D Converter Applications”.

VDD
Connection

Device 4

Device 1

Device 3

Device 2

FIGURE 6-4: VDD traces arranged in a

‘Star’ configuration in order to reduce errors
caused by current return paths.

© 2008 Microchip Technology Inc. DS21290E-page 23

MCP3201
NOTES:

DS21290E-page 24 © 2008 Microchip Technology Inc.

 MCP3201
7.0 PACKAGING INFORMATION

7.1 Package Marking Information

8-Lead MSOP Example:

XXXXXX 3201CI
YWWNNN 820256

8-Lead PDIP (300 mil) Example:

XXXXXXXX 3201-B
XXXXXNNN I/P e^^256
3
YYWW 0820

8-Lead SOIC (150 mil) Example:

XXXXXXXX 3201-BI
XXXXYYWW SN e3 0820
NNN 256

8-Lead TSSOP Example:

XXXX 201C
YYWW I820
NNN 256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

© 2008 Microchip Technology Inc. DS21290E-page 25

MCP3201

       

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DS21290E-page 26 © 2008 Microchip Technology Inc.

 MCP3201

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© 2008 Microchip Technology Inc. DS21290E-page 27

MCP3201

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DS21290E-page 28 © 2008 Microchip Technology Inc.

 MCP3201

    !&'"()#$% *

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© 2008 Microchip Technology Inc. DS21290E-page 29

MCP3201

  +, ,   +!-(-$%+ 

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%% 033)))&    &3 2

E1

NOTE 1

1 2
b
e

c
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        ) /9:.

DS21290E-page 30 © 2008 Microchip Technology Inc.

 MCP3201
APPENDIX A: REVISION HISTORY

Revision E (November 2008)

The following is the list of modifications:
1. Updated Section 7.0 “Packaging Informa-
tion”
2. Updated Section “Product Identification
System”.

Revision D (January 2007)

The following is the list of modifications:
1. This revision includes updates to the packaging
diagrams.

diagrams.Revision C (August 2001)

The following is the list of modifications:
1. This revision includes undocumented changes.

Revision B (August 1999)

The following is the list of modifications:
1. This revision includes undocumented changes.

Revision A (September 1998)

• Original Release of this Document.

© 2008 Microchip Technology Inc. DS21290E-page 31

MCP3201
NOTES:

DS21290E-page 32 © 2008 Microchip Technology Inc.

 MCP3201
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO. X X /XX
a) MCP3201-BI/P: B Grade,
Device Grade Temperature Package Industrial Temperature,
Range 8LD PDIP package.
b) MCP3201-BI/SN: B Grade,
Industrial Temperature,
Device MCP3201: 12-Bit A/D Converter w/SPI Interface
MCP3201T: 12-Bit A/D Converter w/SPI Interface
8LD SOIC package.
(Tape and Reel) c) MCP3201-CI/P: C Grade,
Industrial Temperature,
8LD PDIP package.
Grade B: = ± LSB max INL (MSOP and TSSOP not available)
C: = ± LSB max INL d) MCP3201-CI/MS: C Grade,
Industrial Temperature,
8LD MSOP package.
Temperature Range I = -40°C to+85°C(Industrial)
e) MCP3201-CI/SN: C Grade,
Industrial Temperature,
Package MS = Plastic Micro Small Outline (MSOP), 8-lead 8LD SOIC package.
P = Plastic DIP (300 mil Body), 8-lead
f) MCP3201-CI/ST: C Grade,
SN = Plastic SOIC (150 mil Body), 8-lead
ST = Plastic TSSOP (4.4 mm), 8-lead Industrial Temperature,
8LD TSSOP package.
g) MCP3201T-BI/SN: Tape and Reel,B Grade,
Industrial Temperature,
8LD SOIC package.
h) MCP3201T-CI/MS: Tape and Reel, C Grade,
Industrial Temperature,
8LD MSOP package.
i) MCP3201T-CI/SN: Tape and Reel, C Grade,
Industrial Temperature,
8LD SOIC package.
j) MCP3201T-CI/ST: Tape and Reel, C Grade,
Industrial Temperature,
8LD TSSOP package.

© 2008 Microchip Technology Inc. DS21290E-page 33

MCP3201
NOTES:

DS21290E-page 34 © 2008 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, rfPIC, SmartShunt and UNI/O are registered
MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

© 2008 Microchip Technology Inc. DS21290E-page 35

 WORLDWIDE SALES AND SERVICE
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Addison, TX Fax: 86-25-8473-2470 Fax: 60-3-6201-9859 UK - Wokingham
Tel: 972-818-7423 China - Qingdao Tel: 44-118-921-5869
Malaysia - Penang
Fax: 972-818-2924 Tel: 86-532-8502-7355 Fax: 44-118-921-5820
Tel: 60-4-227-8870
Detroit Fax: 86-532-8502-7205 Fax: 60-4-227-4068
Farmington Hills, MI China - Shanghai Philippines - Manila
Tel: 248-538-2250 Tel: 86-21-5407-5533 Tel: 63-2-634-9065
Fax: 248-538-2260 Fax: 86-21-5407-5066 Fax: 63-2-634-9069
Kokomo China - Shenyang Singapore
Kokomo, IN Tel: 86-24-2334-2829 Tel: 65-6334-8870
Tel: 765-864-8360 Fax: 86-24-2334-2393 Fax: 65-6334-8850
Fax: 765-864-8387
China - Shenzhen Taiwan - Hsin Chu
Los Angeles Tel: 86-755-8203-2660 Tel: 886-3-572-9526
Mission Viejo, CA Fax: 86-755-8203-1760 Fax: 886-3-572-6459
Tel: 949-462-9523
China - Wuhan Taiwan - Kaohsiung
Fax: 949-462-9608
Tel: 86-27-5980-5300 Tel: 886-7-536-4818
Santa Clara Fax: 86-27-5980-5118 Fax: 886-7-536-4803
Santa Clara, CA
China - Xiamen Taiwan - Taipei
Tel: 408-961-6444
Tel: 86-592-2388138 Tel: 886-2-2500-6610
Fax: 408-961-6445
Fax: 86-592-2388130 Fax: 886-2-2508-0102
Toronto
China - Xian Thailand - Bangkok
Mississauga, Ontario,
Tel: 86-29-8833-7252 Tel: 66-2-694-1351
Canada
Tel: 905-673-0699 Fax: 86-29-8833-7256 Fax: 66-2-694-1350
Fax: 905-673-6509 China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049

01/02/08

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