D Integrated Asynchronous-Communications D Fully Programmable Serial Interface

Element Characteristics:
D Consists of Four Improved TL16C550C – 5-, 6-, 7-, or 8-Bit Characters
ACEs Plus Steering Logic – Even-, Odd-, or No-Parity Bit
D In FIFO Mode, Each ACE Transmitter and
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 1-Mbit Per
Receiver Is Buffered With 16-Byte FIFO to
Second)
Reduce the Number of Interrupts to CPU
D In TL16C450 Mode, Hold and Shift
D False Start Bit Detection
Registers Eliminate Need for Precise D Complete Status Reporting Capabilities
Synchronization Between the CPU and D Line Break Generation and Detection
Serial Data D Internal Diagnostic Capabilities:
D Up to 16-MHz Clock Rate for up to 1-Mbaud – Loopback Controls for Communications
Operation Link Fault Isolation
D Programmable Baud-Rate Generators – Break, Parity, Overrun, Framing Error
Which Allow Division of Any Input Simulation
Reference Clock by 1 to (216 – 1) and D Fully Prioritized Interrupt System Controls
Generate an Internal 16 × Clock D Modem Control Functions (CTS, RTS, DSR,
D Adds or Deletes Standard Asynchronous DTR, RI, and DCD)
Communication Bits (Start, Stop, and D 3-State Outputs Provide TTL Drive
Parity) to or From the Serial-Data Stream Capabilities for Bidirectional Data Bus and
D Independently Controlled Transmit, Control Bus
Receive, Line Status, and Data Set D Programmable Auto-RTS and Auto-CTS
Interrupts
D CTS Controls Transmitter in Auto-CTS
D 5-V and 3.3-V Operation Mode,
D RCV FIFO Contents and Threshold Control
RTS in Auto-RTS Mode,

description
The TL16C554A is an enhanced quadruple version of the TL16C550C asynchronous-communications element
(ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral
devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete
status of each channel of the quadruple ACE can be read by the CPU at any time during operation. The
information obtained includes the type and condition of the operation performed and any error conditions
encountered.
The TL16C554A quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs
to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and
transmit modes. In the FIFO mode of operation, there is a selectable autoflow control feature that can
significantly reduce software overhead and increase system efficiency by automatically controlling serial-data
flow using RTS output and CTS input signals. All logic is on the chip to minimize system overhead and maximize
system efficiency. Two terminal functions allow signaling of direct-memory access (DMA) transfers. Each ACE
includes a programmable baud-rate generator that can divide the timing reference clock input by a divisor
between 1 and 216 – 1.
The TL16C554A is available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and in an 80-pin (TQFP)
PN package.

1
 FN PACKAGE
(TOP VIEW)

DCDD
DCDA

INTN
GND

RXD
VCC
RXA

RID
RIA

D7
D6
D5
D4
D3
D2
D1
D0
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
DSRA 10 60 DSRD
CTSA 11 59 CTSD
DTRA 12 58 DTRD
VCC 13 57 GND
RTSA 14 56 RTSD
INTA 15 55 INTD
CSA 16 54 CSD
TXA 17 53 TXD
IOW 18 52 IOR
TXB 19 51 TXC
CSB 20 50 CSC
INTB 21 49 INTC
RTSB 22 48 RTSC
GND 23 47 VCC
DTRB 24 46 DTRC
CTSB 25 45 CTSC
DSRB 26 44 DSRC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
XTAL1
XTAL2
A2
A1
A0
RXB

NC

RESET

RIC
TXRDY

RXC
DCDB

RXRDY

GND

DCDC
RIB

VCC

NC – No internal connection

2
 PN PACKAGE
(TOP VIEW)

RXRDY
TXRDY

RESET

XTAL2
XTAL1
DCDC

DCDB
GND
RXC

RXB
VCC
RIC

RIB

NC
NC

NC

NC
A0
A1
A2
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
NC 61 40 NC
DSRC 62 39 DSRB
CTSC 63 38 CTSB
DTRC 64 37 DTRB
VCC 65 36 GND
RTSC 66 35 RTSB
INTC 67 34 INTB
CSC 68 33 CSB
TXC 69 32 TXB
IOR 70 31 IOW
NC 71 30 NC
TXD 72 29 TXA
CSD 73 28 CSA
INTD 74 27 INTA
RTSD 75 26 RTSA
GND 76 25 VCC
DTRD 77 24 DTRA
CTSD 78 23 CTSA
DSRD 79 22 DSRA
NC 80 21 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VCC

D0
D1
D2

D3
D4
D5
D6
D7

RIA
NC

RID

INTN

RXA
RXD

NC

GND

DCDA
DCDD

NC

NC – No internal connection

3
functional block diagram (per channel)
Internal
Data S
e
Bus
5 – 66 Data 8 l Receiver
D(7 – 0) Bus e FIFO
Buffer c 8
t

Receiver 7
Receiver Shift RXA
Buffer Register
Register

Receiver
Line Timing and
Control Control
Register 14
RTSA

34
A0 Divisor
33 Latch (LS)
A1 Baud
32 Generator
A2 Divisor
Latch (MS)
16 Autoflow
CSA Control
20 Line Transmitter (AFE)
CSB Timing and
Status
50 Control
CSC Register
54 Select
CSD and Transmitter S
37 Control FIFO e
RESET
Logic l
52
IOR Transmitter 8 e 8 Transmitter 17
18 Holding c Shift TXA
IOW t Register
Register
39
TXRDY
35
XTAL1 Modem
36 8
XTAL2 Control
Register 11
38 CTSA
RXRDY
12
65 DTRA
INTN Modem 8 Modem
10
Status Control DSRA
Register Logic 9
DCDA
8
RIA

13, 30, 47, 64

VCC
Power
6, 23, 40, 57 Supply Interrupt 8 Interrupt 15 INTA
GND Enable Control
Register Logic

Interrupt 8
Identification
Register

FIFO
Control
Register

NOTE A: Terminal numbers shown are for the FN package and channel A.

4
 Terminal Functions
TERMINAL
FN PN I/O DESCRIPTION
NAME
NO. NO.
A0 34 48 I Register select terminals. A0, A1, and A2 are three inputs used during read and write operations to
A1 33 47 select the ACE register to read or write.
A2 32 46
CSA, CSB, 16, 20, 28, 33, I Chip select. Each chip select (CSx) enables read and write operations to its respective channel.
CSC, CSD 50, 54 68, 73
CTSA, CTSB, 11, 25, 23, 38, I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS)
CTSC, CTSD 45, 59 63, 78 of the modem-status register. Bit 0 (ΔCTS) of the modem-status register indicates that CTS has
changed state since the last read from the modem-status register. If the modem-status interrupt is
enabled when CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated.
CTS is also used in the auto-CTS mode to control the transmitter.
D7 – D0 66 – 68 15–11, I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
1–5 9–7 information between the TL16C554A and the CPU. D0 is the least-significant bit (LSB).
DCDA, DCDB, 9, 27, 19,42, I Data carrier detect. A low on DCDx indicates the carrier has been detected by the modem. The
DCDC, DCDD 43, 61 59, 2 condition of this signal is checked by reading bit 7 of the modem-status register.
DSRA, DSRB, 10, 26, 22, 39, Data set ready. DSRx is a modem-status signal. Its condition can be checked by reading bit 5 (DSR)
I
DSRC, DSRD 44, 60 62, 79 of the modem-status register. DSR has no effect on the transmit or receive operation.
DTRA, DTRB, 12, 24, 24, 37, O Data terminal ready. DTRx is an output that indicates to a modem or data set that the ACE is ready
DTRC, DTRD 46, 58 64, 77 to establish communications. It is placed in the active state by setting the DTR bit of the modem-
control register. DTRx is placed in the inactive state (high) either as a result of the master reset during
loop-mode operation, or when clearing bit 0 (DTR) of the modem-control register.
GND 6, 23, 16, 36, Signal and power ground
40, 57 56, 76
INTN 65 6 I Interrupt normal. INTN operates in conjunction with bit 3 of the modem-status register and affects
operation of the interrupts (INTA, INTB, INTC, and INTD) for the four universal asynchronous
receiver/transceivers (UARTs) per the following table.
INTN OPERATION OF INTERRUPTS
Brought low or Interrupts are enabled according to the state of OUT2 (MCR bit 3). When the MCR
allowed to float bit 3 is cleared, the 3-state interrupt output of that UART is in the high-impedance
state. When the MCR bit 3 is set, the interrupt output of the UART is enabled.
Brought high Interrupts are always enabled, overriding the OUT2 enables.
INTA, INTB, 15, 21, 27, 34, O External interrupt output. The INTx outputs go high (when enabled by the interrupt register) and
INTC, INTD 49, 55 67, 74 inform the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt
to be issued are: receiver error, receiver data available or timeout (FIFO mode only), transmitter
holding register empty, and an enabled modem-status interrupt. The interrupt is disabled when it is
serviced or as the result of a master reset.
IOR 52 70 I Read strobe. A low level on IOR transfers the contents of the selected register to the external CPU
bus.
IOW 18 31 I Write strobe. IOW allows the the CPU to write to the register selected by the address.
RESET 37 53 I Master reset. When active, RESET clears most ACE registers and sets the state of various signals.
The transmitter output and the receiver input are disabled during reset time.
RIA, RIB, 8, 28, 18, 43, I Ring detect indicator. A low on RIx indicates the modem has received a ring signal from the telephone
RIC, RID 42, 62 58, 3 line. The condition of this signal can be checked by reading bit 6 of the modem-status register.
RTSA, RTSB, 14, 22, 26, 35, O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive
RTSC, RTSD 48, 56 66, 75 data. RTS is set to the active level by setting the RTS modem-control register bit, and is set to the
inactive (high) level either as a result of a master reset, or during loop-mode operations, or by clearing
bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to the inactive level by the receiver
threshold-control logic.

5
 Terminal Functions (Continued)
TERMINAL
FN PN I/O DESCRIPTION
NAME
NO. NO.
RXA, RXB 7, 29, 17, 44, I Serial input. RXx is a serial-data input from a connected communications device. During loopback
RXC, RXD 41, 63 57, 4 mode, the RXx input is disabled from external connection and connected to the TXx output internally.
RXRDY 38 54 O Receive ready. RXRDY goes low when the receive FIFO is full. It can be used as a single transfer
or multitransfer.
TXA, TXB 17, 19, 29, 32, O Transmit outputs. TXx is a composite serial-data output connected to a communications device.
TXC, TXD 51, 53 69, 72 TXA, TXB, TXC, and TXD are set to the marking (high) state as a result of reset.
TXRDY 39 55 O Transmit ready. TXRDY goes low when the transmit FIFO is full. It can be used as a single transfer
or multitransfer function.
VCC 13, 30, 5, 25, Power supply
47, 64 45, 65
XTAL1 35 50 I Crystal input 1 or external clock input. A crystal can be connected to XTAL1 and XTAL2 to utilize the
internal oscillator circuit. An external clock can be connected to drive the internal-clock circuits.
XTAL2 36 51 O Crystal output 2 or buffered clock output (see XTAL1).

absolute maximum ratings over free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range at any input, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 3 V
Continuous total-power dissipation at (or below) 70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Operating free-air temperature range, TA: TL16C554A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to GND.

6
recommended operating conditions, standard voltage (5 V-nominal)
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Clock high-level input voltage at XTAL1, VIH(CLK) 2 VCC V
Clock low-level input voltage at XTAL1, VIL(CLK) – 0.5 0.8 V
High-level input voltage, VIH 2 VCC V
Low-level input voltage, VIL – 0.5 0.8 V
Clock frequency, fclock 16 MHz
Operating free-air temperature, TA 0 70 °C

electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage, standard voltage (5-V nominal) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VOH‡ High-level output voltage IOH = – 1 mA 2.4 V
VOL‡ Low-level output voltage IOL = 1.6 mA 0.4 V
VCC = 5.25 V, GND = 0,
IIkg Input leakage current ± 10
VI = 0 to 5.25 V, All other terminals floating

g
recommended operating conditions, low voltage (3.3-V nominal)
MIN NOM MAX UNIT
Supply voltage, VCC 3 3.3 3.6 V
Clock high-level input voltage at XTAL1, VIH(CLK) 2 VCC V
Clock low-level input voltage at XTAL1, VIL(CLK) – 0.5 0.8 V
High-level input voltage, VIH 2 VCC V
Low-level input voltage, VIL – 0.5 0.8 V
Clock frequency, fclock 16 MHz
Operating free-air temperature, TA 0 70 °C

electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage, low voltage (3.3-V nominal) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VOH‡ High-level output voltage IOH = – 1 mA 2.4 V
VOL‡ Low-level output voltage IOL = 1.6 mA 0.4 V
VCC = 3.6 V, GND = 0,
IIkg Input leakage current ± 10
VI = 0 to 3.6 V, All other terminals floating

g
read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)
MIN MAX UNIT
tw4 Pulse duration, IOR low 75 ns
tsu1 Setup time, CSx valid before IOR low (see Note 2) 10 ns
tsu2 Setup time, A2 – A0 valid before IOR low (see Note 2) 15 ns
th1 Hold time, A2 – A0 valid after IOR high (see Note 2) 0 ns
th2 Hold time, CSx valid after IOR high (see Note 2) 0 ns
td1 Delay time, tsu2 + tw4 + td2 (see Note 3) 140 ns
td2 Delay time, IOR high to IOR or IOW low 50 ns
NOTES: 2. The internal address strobe is always active.
3. In the FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt-identification register
and line-status register).

write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 5)
MIN MAX UNIT
tw5 Pulse duration, IOW↓ 50 ns
tsu3 Setup time, CSx valid before IOW↓ (see Note 2) 10 ns
tsu4 Setup time, A2 – A0 valid before IOW↓ (see Note 2) 15 ns
tsu5 Setup time, D7 – D0 valid before IOW↑ 10 ns
th3 Hold time, A2 – A0 valid after IOW↑ (see Note 2) 5 ns
th4 Hold time, CSx valid after IOW↑ (see Note 2) 5 ns
th5 Hold time, D7 – D0 valid after IOW↑ 25 ns
td3 Delay time, tsu4 + tw5 + td4 120 ns
td4 Delay time, IOW↑ to IOW or IOR↓ 55 ns
NOTE 2: The internal address strobe is always active.

read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage, CL = 100 pF (see Note 4 and Figure 4)
PARAMETER MIN MAX UNIT
ten Enable time, IOR↓ to D7 – D0 valid 30 ns
tdis Disable time, IOR↑ to D7 – D0 released 0 20 ns
NOTE 4: VOL and VOH (and the external loading) determine the charge and discharge time.

9
transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 6, 7, and 8)
PARAMETER TEST CONDITIONS MIN MAX UNIT
RCLK
td5 Delay time, INTx↓ to TXx↓ at start See Note 7 8 24 cycles
RCLK
td6 Delay time, TXx↓ at start to INTx↑ See Note 5 8 8 cycles
RCLK
td7 Delay time, IOW high or low (WR THR) to INTx↑ See Note 5 16 32 cycles
RCLK
td8 Delay time, TXx↓ at start to TXRDY↓ CL = 100 pF 8 cycles
tpd1 Propagation delay time, IOW (WR THR)↓ to INTx↓ CL = 100 pF 35 ns
tpd2 Propagation delay time, IOR (RD IIR)↑ to INTx↓ CL = 100 pF 30 ns
tpd3 Propagation delay time, IOW (WR THR)↑ to TXRDY↑ CL = 100 pF 50 ns
NOTE 5: If the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop-bit time.

receiver switching characteristics over recommended ranges of operating free-air temperature

and supply voltage (see Figures 9 through 13)
PARAMETER TEST CONDITIONS MIN MAX UNIT
RCLK
td9 Delay time, stop bit to INTx↑ or stop bit to RXRDY↓ or read RBR to set interrupt See Note 6 1 cycle
CL = 100 pF,
tpd4 Propagation delay time, Read RBR/LSR to INTx↓/LSR interrupt↓ See Note 7 40 ns

tpd5 Propagation delay time, IOR RCLK↓ to RXRDY↑ See Note 7 30 ns

NOTES: 6. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are
delayed three RCLK (internal receiver timing clock) cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status
indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after
IOR goes active for a read from the RBR register. There are eight RCLK cycle delays for trigger change level interrupts.
7. RCLK and baudout are internal signals derived from divisor latches LSB (DLL) and MSB (DLM) and input clock.

modem control switching characteristics over recommended ranges of operating free-air

temperature and supply voltage, CL = 100 pF (see Figures 14, 15, 16, and 17)
PARAMETER MIN MAX UNIT
tpd6 Propagation delay time, IOW (WR MCR)↑ to RTSx, DTRx↑ 50 ns
tpd7 Propagation delay time, modem input CTSx, DSRx, and DCDx ↓↑ to INTx↑ 30 ns
tpd8 Propagation delay time, IOR (RD MSR)↑ to interrupt↓ 35 ns
tpd9 Propagation delay time, RIx↑ to INTx↑ 30 ns
baudout
tpd10 Propagation delay time, CTS low to SOUT↓ (See Note 7) 24
cycles
baudout
tsu6 Setup time CTS high to midpoint of Tx stop bit 2
cycles
baudout
tpd11 Propagation delay time, RCV threshold byte to RTS↑ 2
cycles
baudout
tpd12 Propagation delay time, IOR (RD RBR) low (read of last byte in receive FIFO) to RTS↓ 2
cycles
baudout
tpd13 Propagation delay time, first data bit of 16th character to RTS↑ 2
cycles
baudout
tpd14 Propagation delay time, IOR (RD RBR) low to RTS↓ 2
cycles
7. RCLK and baudout are internal signals derived from divisor latches LSB (DLL) and MSB (DLM) and input clock.

10
 PARAMETER MEASUREMENT INFORMATION

tw1

Clock 2V 2V 2V
(XTAL1) 0.8 V
0.8 V 0.8 V

tw2

fclock = 16 MHz MAX

(a) CLOCK INPUT VOLTAGE WAVEFORM

RESET

tw3

(b) RESET VOLTAGE WAVEFORM

Figure 1. Clock Input and RESET Voltage Waveforms

2.54 V

Device Under Test

680

TL16C554