ESc201 : Introduction to Electronics

Excitation Table and

Circuit States

Vipul Arora
Dept. of Electrical Engineering
IIT Kanpur
April 17, 2023
1
Toggle or T Flip-flop Characteristic table:
Inputs (T) Q(t+1)
T Q 0 Q(t)
clk 1 Q(t)

Characteristic equation: Q(t + 1) = T  Q(t )

Excitation Table:
What inputs are required to affect a particular state change
Inputs
Q T Q(t+1) Q(t) Q(t+1) T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0
1 1 0 2
JK Flip-flop excitation table (recap)
Inputs
J K Q(t+1) Q(t) Q(t+1) J K
J Q 0 0 Q(t) 0 0 0 X
clk 0 1 0
0 1 1 X
1 0 1
K 1 1 Q(t) 1 0 X 1
Characteristic Table 1 1 X 0

Excitation Table
Q J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0 3
D Flip flop excitation table (recap)

D Q D Q(t+1)
0 0
clk 1 1

Characteristic Table

Q D Q(t+1)
0 0 0 Inputs

0 1 1 Q(t) Q(t+1) D
0 0 0
1 0 0
0 1 1
1 1 1
1 0 0
1 1 1

Excitation Table
4
Convert a D FF to JK FF
or use D FF to implement JK FF J K Q Q(t+1) D
0 X 0 0 0
D Q
J 1 X 0 1 1
CC clk
X 1 1 0 0
K
X 0 1 1 1

Inputs Inputs
Q(t) Q(t+1) J K Q(t) Q(t+1) D
0 0 0 X 0 0 0
0 1 1 X 0 1 1
1 0 X 1 1 0 0
1 1 X 0 1 1 1

Excitation Table Excitation Table

5
Convert a D FF to JK FF
or use D FF to implement JK FF J K Q Q(t+1) D
0 X 0 0 0
D Q
J 1 X 0 1 1
CC clk
X 1 1 0 0
K
X 0 1 1 1

To determine CC, find D in terms of J,

K, Q(t), so as to induce the same
1 1 excitation Q(t+1)

1 1

D = Q.J + Q.K
6
Convert a D FF to JK FF
Confirm
D = Q.J + Q.K Q J K D Q(t+1)
0 0 0 0 0

0 0 1 0 0

0 1 0 1 1

0 1 1 1 1
1 0 0 1 1
1 0 1 0 0

Inputs J K Q(t+1) 1 1 0 1 1

0 0 Q(t) 1 1 1 0 0

0 1 0
1 0 1
1 1 Q(t)

7
 State of Sequential Circuits
The binary information stored in
X Z
CC the storage elements at any given
time defines the state of the
sequential circuit at that time
Storage
elements

Output is a function of inputs and current state.

Next state is also a function of inputs and current state.
 Synchronous Sequential Circuits
Input Combinational Output
Circuit
Flip-flops
Clock

Employs signals that affect the storage elements only at

discrete instants of time.

Synchronization is achieved via the clock pulses.

Synchronous Clocked Sequential Circuits
Analysis
Next state Logic Output Logic

A
x A
D

B
A B z
D
x x

clk
memory
Output z depends on the input x and on the state of the memory (A,B)
The memory has 2 FFs and each FF can be in state 0 or 1. Thus there
are four possible states: AB: 00,01,10,11.

To describe the behavior of a sequential circuit, we need to show

1. How the system goes from one memory state to the next as the input
changes
2. How the output responds to input in each state
Analysis of Sequential Circuits
A
memory Output Logic
x A
D

B
A B z
D
x x

Next state Logic clk

DA = A.x + B.x ; DB = A.x ; z = ( A + B ). x

A(t + 1) = A(t ).x + B (t ).x

B(t + 1) = A(t ).x
z = ( A + B). x
 State Transition Table
• Next state as a function of inputs and current
state
• Current output as a function of inputs and
current state

12
Analysis of Sequential Circuits
A
memory Output Logic
x A
D

B
A B z
D
x x

Next state Logic clk

DA = A.x + B.x ; DB = A.x ; z = ( A + B ). x State Transition Table

Present State Input Next State Output

A B x A B z
0 0 0 0 0 0
0 0 1 0 1 0
A(t + 1) = A(t ).x + B (t ).x
0 1 0 0 0 1
B(t + 1) = A(t ).x 0 1 1 1 1 0
1 0 0 0 0 1
z = ( A + B). x 1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
 State Transition Graph
• Helps in visualizing and designing
• Plots State, inputs and outputs

x/z
AB A’B’

x’/z’
x’’/z’’

A’’B’’

14
 State Transition Table

A
Present State Input Next State Output
memory Output Logic
x A A B x A B z
D
0 0 0 0 0 0
B
0 0 1 0 1 0
A B z 0 1 0 0 0 1
D
x x 0 1 1 1 1 0
Next state Logic clk 1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1
1 0 0

00 Memory state in which FF A& B have output values 00

If x = 0 then z = 0, When the clock edge comes the
x=0/z system would stay in 00 state.
?
00 If x = 1 then z = 0. When the clock edge comes the
system would go to 01 state.
x=1/z
0/0
?

00 01
1/0
Analysis of Sequential Circuits

A
x
memory
D
A Output Logic A(t + 1) = A(t ).x + B (t ).x

B
B(t + 1) = A(t ).x
A B z
x
D
x z = ( A + B). x
Next state Logic clk

State Transition Table

1/0 Present State Input Next State Output

10
A B x A B z
0/0 0/1 0 0 0
1/0 0 0 0
0 0 1 0 1 0
00 01 11
1/0 1/0 0 1 0 0 0 1
0 1 1 1 1 0
0/1
0 0 1
1 0 0
0/1 1 0 1 1 0 0

1 1 0 0 0 1
State transition Graph
1 1 1 1 0 0
 1/0
10
0/0 0/1
1/0

00 01 11
1/0 1/0

0/1
0/1

State transition Graph

'10', '110', '1110'

x z
Sequence detector
(0101101110111100......)
0010010001000010….
CIRCUIT DESIGN

18
Design of Sequential Circuits
1/0
10
0/0 0/1
1/0

Specifications 00
1/0
01
1/0
11

0/1
0/1

State Diagram
State Transition Table

Present State Input Next State Output

A B x A B z
0 0 0 0 0 0
Choose FF 0 0 1
0 1 0

State Encoding 0
0
1
1
0
1
0 0 1
0
1 1
1 0 0 1
1 0 1 0 0
1 0 0
1 1 0
1 1 1 0 0 1
State Table 1 0 0

A
x A
D
Synthsize Combinational
B
Circuit A B z
D
x x

clk
System specification to State diagram

x Sequence detector Y

(0101101110111100......)

Detect 3 or more consecutive 1’s in the input stream

0/0
0/0

S0 S1
1/0
1/0
0/0 0/0

S3 S2
1/1 1/1
Conversion of State transition graph to a circuit
Example-1

x
0/0 0/0
CC-2
Next State logic

S0 S1
1/0 y CC-1
z
Y Memory
Output logic
clk
(FFs)

1/1
3 blocks need to be designed

1. How many FFs do we need? N FFS can represent 2N states so

Minimum is 1
2. Which FF do we choose? Say D FF

3. How are the states encoded? Say FF output Q=0 represents S0 and
Q=1 represents S1 state
 0/0 CC-2
0/0 x
Next State logic

S0 S1 CC-1
1/0 z
D Q Output logic

clk
1/1

State Transition Table

Present State Input Next State D Output

Q(t) x Q(t+1) z We need the
0 0 0 0 excitation table of
0 1 1 0 D FF
1 0 1 0
1 1 0 1
Excitation Table

Inputs
D Q Q(t) Q(t+1) D
clk 0 0 0
0 1 1
1 0 0
1 1 1
 0/0 CC-2
0/0 x
Next State logic

S0 S1 CC-1
1/0 z
D Q Output logic

clk
1/1

State Transition Table

Now write
Present State Input Next State D Output 𝐷 = 𝑓 𝑥, 𝑄 𝑡
Q(t) x Q(t+1) z 𝑧 = 𝑓 ′ 𝑥, 𝑄 𝑡
0 0 0 0 0
0 1 1 1 0 D = Q.x + Q.x ; z = Q. x
1 0 1 1 0
1 1 0 0 1
x D Q
z
clk
Example-2

CC-2 x
0/0 0/0 Next State logic

S0 S1
1/0 CC-1
Y y z
Memory
Output logic
clk
(FFs)
1/1

1. How many FFs do we need? 1

2. Which FF do we choose? Say JK FF

3. How are the states encoded?Say FF output Q=0 represents S0 and

Q=1 represents S1 state
 CC-2
x
Next State logic
0/0 0/0
CC-1
z
S0 S1 J Q Output logic
1/0 clk
K Q

1/1
Q(t) Q(t+1) J K
0 0 0 X
State Transition Table
0 1 1 X
Present State Input Next State J K Output 1 0 X 1
Q(t) x Q(t+1) z
1 1 X 0
0 0 0 0 X 0
0 1 1 1 X 0

1 0 1 X 0 0 x J Q
1 1 0 1 z
X 1 clk
K

J = x ; K = x ; z = Q. x
Example-3 For 4 states a minimum of two FFs will be
required. Let us choose 2 D FFs A &B

1
0 1
x
S0 S3 NS logic
0
0
0 1
DA QA DB QB
S1 S2
1 clk clk

FF O/P
Present State Input Next State
State A B
A B x A B DA DB
S0 0 0 0 0 0 0 1 00 11
0 0 1 0 0 0
0 00
S1 0 1 0 1 0 1 1 11 11
0 1 1 1 0 11 00
S2 1 0 1 0 0 1 1 11 11
1 0 1 1 0 11 00
S3 1 1 1 1 0 0 0 00 00
1 1 1 1 1 11 11
Present State Input Next State
A B x A B DA DB DA
AB
0 0 0 0 1 0 1 x 00 01 11 10
0 0 1 0 0 0 0

0 1 0 1 1 1 1 0 0 1 0 1
0 1 1 1 0 1 0

1 0 0 1 1 1 1 1 0 1 1 1
1 0 1 1 0 1 0

1 1 0 0 0 0 0
1 1 1 1 1 1 1
DA = AB + xB + AB
= A  B + x.B

DB
AB
x 00 01 11 10 DB = x. A + x.B + x. A.B
1 1 0 1
0 = x.( A + B) + x. A.B
1 0 0 1 0 = x. AB + x. AB = x  AB
 DA = A  B + x.B DB = x  AB

1
0 1

S0 S3 x
0
0
0 1

S1 S2
1

DA QA

clk DB QB

clk