UNIVERSITY OF EDINBURGH

COLLEGE OF SCIENCE AND ENGINEERING

SCHOOL OF INFORMATICS

INFR08018 INFORMATICS 2C - INTRODUCTION TO

COMPUTER SYSTEMS

Thursday 20 th December 2012

14:30 to 15:30

INSTRUCTIONS TO CANDIDATES

1. Answer Parts A and B. The multiple choice questions in Part A are

worth 50% in total and are each worth the same amount. Mark one
answer only for each question — multiple answers will score 0. Marks
will not be deducted for incorrect answers. Part B is worth 50% and
contains TWO questions. Answer ONE of them.

2. Use the special mark sheet for Part A. Use a script book for the ques-
tion from Part B that you answer.

3. Calculators may not be used in this examination.

Convener: J Bradfield
External Examiner: A Preece

THIS EXAMINATION WILL BE MARKED ANONYMOUSLY

 Part A
ANSWER ALL QUESTIONS IN PART A. Use the special mark sheet.

1. According to the IEEE 754 floating-point standard, what decimal number is

represented by the 32-bit word 0x c16c 0000?
Remember that, for 32-bit numbers, the exponent bias is 127.

(a) −6.75
(b) −7.375
(c) −13.5
(d) −13.75
(e) −14.75

2. What is the value in register $t2 after executing the following piece of MIPS
assembly code

li $t0, 2
li $t1, 1
li $t2, 2
li $t3, 4
loop: beq $t0, $zero, end
add $t3,$t1,$t2
add $t2,$zero,$t3
srl $t0,$t0,2 # shift right logical
j loop
end:

(a) 2
(b) 3
(c) 4
(d) 5
(e) 6

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3. Consider running the C program fragment:

int x[4] = {1,2,4,8};

int *y;
int *z;
y = &x[1];
z = y + 1;
x[0] = *z;

What is the value of the expression x[0] afterwards?

(a) 1
(b) 2
(c) 3
(d) 4
(e) 5

4. Consider the logic circuit:

What is c as a function of a and b?

(a) a.b + a.b

(b) a.b
(c) a + b
(d) a.b + a.b
(e) a + b

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5. Consider the MIPS multi-cycle implementation discussed in class. Suppose we
want to modify the architecture to support a new instruction, similar to the store
word instruction

sw r, n(s) ,

that does the store as usual, but also updates the value in register s to s + n.
The modification might involve adding one or more multiplexers and changing
the control logic, but would not involve adding any further registers.
What is the minimum number of cycles this new instruction would need?

(a) 1
(b) 2
(c) 3
(d) 4
(e) 5

6. Which hazards are present in the following piece of code, on the familiar 5-stage
pipelined MIPS processor discussed in the course?

slt $s1, $s2, $s3

beq $s1, $zero, label
add $s4, $s2, $s3
label: sub $s5, $s2, $s3

(a) Structural hazard only

(b) Data hazard and control hazard
(c) Control hazard only
(d) Data hazard only
(e) Data hazard and structural hazard

7. Which of the following is not a function of an operating system’s kernel?

(a) I/O support

(b) Program compilation
(c) Interrupt handling
(d) Memory management
(e) Process creation and destruction

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 8. Consider a direct-mapped cache with 1024 blocks/lines in which each block has
four 32-bit words. How many bits are needed for the tag and index fields, assum-
ing a 32-bit address?

(a) 18 bits tag, 10 bits index.

(b) 18 bits tag, 12 bits index.
(c) 10 bits tag, 18 bits index.
(d) 20 bits tag, 10 bits index.
(e) 10 bits tag, 20 bits index.

9. Which of the following is not an advantage of virtual memory?

(a) Some data transfers between physical memory and disk are automatic – they
do not have to be explicitly coded for in user programs
(b) Memory accesses are faster than if the processor directly addresses physical
memory
(c) Programs in distinct processes can have overlapping addresses for their code
blocks
(d) A process cannot corrupt data that does not belong to it
(e) The computer can appear to have a larger main memory than it actually
has

10. Which of the following can be described as polling a peripheral?

(a) The processor asks the peripheral to interrupt it when the peripheral is
ready to transfer data.
(b) The processor requests the peripheral to begin a data transfer
(c) The processor asks the peripheral about the priority of a data transfer it
wishes to do, in order to help the processor decide whether to serve that
peripheral or some other peripheral first.
(d) The processor instructs the DMA controller to transfer data from a block
of memory to the peripheral or from the peripheral to a block of memory.
(e) The processor continuously checks the status of the peripheral and transfers
data when the peripheral is ready.

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 Part B
ANSWER ONE QUESTION FROM PART B.

1. (a) Convert the following C code into equivalent MIPS assembly code.
int a[50];
int i;
...
a[0] = 1;
a[1] = 1;
i = 2;
while (i < 48) {
a[i+2] = a[i] + a[i+1];
i++;
}
When your code starts, assume that the base address of array a is held
in register $s0 and that i is held in register $s1. Integers are 32-bit and
memory is byte addressable. You are free to use any other registers as you
wish. Please comment your code well to ease understanding. [18 marks ]
(b) Create a logic design from and, or and not gates which implements a 2 to
4 line decoder with an enable input. This circuit has 2 address inputs a0
and a1, an enable input en and 4 outputs x0, x1, x2 and x3. When a 2-bit
number i is presented on address inputs a1,a0 (a1 the most significant bit),
and en is high, then output xi is high and the other outputs are low. When
en is low, all outputs are low. [8 marks ]
QUESTION CONTINUES ON NEXT PAGE

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 QUESTION CONTINUED FROM PREVIOUS PAGE

(c) Consider a simple fully-associative cache with 4 lines, each containing 8

bytes of data and a tag field of appropriate size for 6-bit addresses.
Assume that the cache is initially empty, that empty lines are filled in order,
and that a least-recently-used replacement policy is used for cache lines.
For the following pattern of cache accesses,
Access Number Address
1. 01 0011
2. 01 1101
3. 01 0101
4. 11 0001
5. 10 1001
6. 00 0101
7. 00 1011
draw up a table as shown below.

Access Number Line 0 Line 1 Line 2 Line 3 Hit/Miss

1
2
3
4
5
6
7
Fill in the table so as to show the valid tags in the cache after each access
and to show whether each access is a hit or a miss: In each row, if Line i is
occupied with the memory block with tag t, write the decimal value of t in
the column for Line i, and record in the Hit/Miss column an H or an M to
indicate whether the access is a hit or a miss. In each row, also circle the
tag derived from the access address. [16 marks ]
(d) How does a pipelined processor differ from a multi-cycle processor such as
discussed in class? Why can pipelining improve processor performance? [8 marks ]

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2. (a) Write C code for a function
int insertchar(char c, int pos, char* s)
which inserts the character c at position pos (0-based) in string s, moving
all the characters in s at pos and beyond one place to the right. Assume
that the string is null terminated, that the storage for the string has space to
accommodate the shift right of some of the characters, and that position pos
is within the string (possibly at the null character terminating the string, in
which case the new character is inserted at the end of the string).
Please add comments to your code explaining the main components. [16 marks ]
(b) i. Consider the single cycle processor discussed in class:

Explain the flow of data, starting with the instruction address from the
PC, for execution of the sw store-word instructions. Remark on needed
values for control signals and which signals are don’t cares.
ii. What minimal changes could you make to the data-path so the archi-
tecture supports a new instruction, similar to the store-word instruction
sw r, n(s) ,
that not only stores register r at location n+s, but also writes n+s back
to register s. Remark on how the control signals must be different for
this new instruction. [16 marks ]
QUESTION CONTINUES ON NEXT PAGE

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 QUESTION CONTINUED FROM PREVIOUS PAGE

(c) Explain what the Translation Lookaside Buffer is and how it operates. [12 marks ]
(d) Both a CPU and DMA (Direct Memory Access) controller need to address
memory. How is their access managed so that attempts at simultaneous
accesses are avoided? Explain the signals involved in this management. [6 marks ]

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