Verilog Challange

DELTA IC LAB

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1 Introductıon
a) Write a Verilog code to swap contents of two registers without temporary
register using asynchronous reset.

b) The 7458 is a chip with four AND gates and two OR gates. Create a module
with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs.
Note: You may choose to use an assign statement to drive each of the output
wires, or you may choose to declare (four) wires for use as intermediate signals,
where each internal wire is driven by the output of one of the AND gates.

Figure 1: top module

c) Observe the difference between logical AND (&&) and bitwise AND (&).

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2 Introduction 2 - Vector Operations
a) Vectors are used to group related signals using one name to make it more
convenient to manipulate. For example, wire [7:0] w; declares an 8-bit vector
named w that is functionally equivalent to having 8 separate wires. Build a

Figure 2: Vector Decleration

circuit that has one 3-bit input, then outputs the same vector, and also splits
it into three separate 1-bit outputs. Connect output o0 to the input vector’s
position 0, o1 to position 1, etc.
In a diagram, a tick mark with a number next to it indicates the width of
the vector (or ”bus”), rather than drawing a separate line for each bit in the
vector.

Figure 3: top module for a vector

b) A 32-bit vector can be viewed as containing 4 bytes (bits [31:24], [23:16],

etc.). Build a circuit that will reverse the byte ordering of the 4-byte word.

AaaaaaaaBbbbbbbbCcccccccDddddddd A → BDdddddddCcccccccBbbbbbbbAaaaaaaa

c) Given a 100-bit input vector [99:0], reverse its bit ordering.

Hint: A for loop (in a combinational always block or generate block) would
be useful here. I would prefer a combinational always block in this case because
module instantiations (which require generate blocks) aren’t needed.

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3 Hamming Distance
İki sayının birbirine ne kadar yakın olduğunu ölçmek için ”hamming uzaklığı”
adı verilen bir karakteristik kullanılmaktadır. Bu uzaklık iki sayının kaç farklı
bit için farklılık gösterdiğini göstermektedir. Örneğin, 001011 sayısı ile 111000
sayısının hamming uzaklığı 4tür.

Bu tanıma göre sizden iki adet on altılık tabanda (hexadecimal) olarak ver-
ilmiş iki sayının birbirlerine olan hamming uzaklığını bulan bir modülü Verilog
kapı seviyesinde modelleme kullanarak gerçeklemeniz beklenmektedir. Modül
içinde toplayıcı kullanmayın.

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4 N-bit Adder
4.1 Half and Full Adder

Figure 4: Truth Table for Half Adder

a) Please try to draw logical circuit of Half Adder according to the truth
table given above. Then, write a Verilog code for Half Adder.

Figure 5: Truth Table for Full Adder

b) Please try to draw logical circuit of Full Adder according to the truth table
given above. Then, write a Verilog code for Full Adder.

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4.2 N-bit Adder
c) Design a N-bit Adder using half adder and full adder on the previous assign-
ment.
Note: For more practice, you can get schematic on Vivado.

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5 Johnson and Ring Counter
a) Please design 4-bit Ring Counter using Verilog HDL. Don’t forget to adjust
preset to logic 1.

Figure 6: 4-bit Ring Counter

b) Please design 4-bit Johnson Counter using Verilog HDL. Don’t forget to
use reverse of the output feedback.

Figure 7: 4-bit Johnson Counter

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6 D Flip Flop vs D Latch
a) Create 16 D flip-flops. It’s sometimes useful to only modify parts of a group of
flip-flops. The byte-enable inputs control whether each byte of the 16 registers
should be written to on that cycle. byteena[1] controls the upper byte d[15:8],
while byteena[0] controls the lower byte d[7:0].
1. resetn is a synchronous, active-low reset.

2. All DFFs should be triggered by the positive edge of clk.

3. The module should have the following interface:

Figure 8: top module for DFF with enable

b) Write a Verilog code to implement basic D Latch with D,Q and enable
signal. Observe the differences between D Latch and D Flip Flop.

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7 Up/down Counter using debouncing button
1) Design 3-bit up/down counter with a reset feature.
After count direction = 1, it should perform to count upwards.

2) Design a clock divider with multiple frequency dividing options based on

input freq.

3) Design a 8-bit counter with two different speeds, one that counts 1bit at
1s and the other one counts 4bit at 1s.

4) Design a 4-bit up/down counter that increments and decrements automat-

ically when reaching its maximum(4’b1111) and minimum(4’b0001). Use a
slowed clock that changes between 1Hz and 100Hz according to sel freq bit.

1. Add a switch to control counter that incerements and decrements.

2. Also design a button debouncer using shift registers to avoid bouncing of
the button.
3. Add a db button used for starting or stopping the counting process.
Debouncing should be applied to that button.

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8 Clock Divider to make LED blink
Design a clock divider to make LED blink.
1. Implement a DFF with asynchronous reset. DFF have three inputs: D,
clk, rst(active high) and one output Q
2. Design a clock divider using propagation delay of the inverter.

Figure 9: The circuit that can divide the clok freq by half

Assume clkdiv is high initially. Thus, din is initially low since it inverts
the signal.
3. Determine how many DFF is needed to decrease 100 MHz to 0.745 Hz.
Don’t adjust initial value of clk to 100 MHz. Dividing by half is enough.

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4. We can actually divide the clock by cascading the previous circuit, as
displayed in Figure below. Besides, we need another output called led.
You can adjust the delay connecting led to output of a DFF.

5. Can you add two switches to control how fast the LED blinks: Say, if
switch[1:0] is 0, LED blink frequency is 0.745 Hz; if switch[1:0] is 1, LED
blink frequency is 1.49 Hz; if switch[1:0] is 2, LED blink frequency is 2.98
Hz; if switch[1:0] is 3, LED blink frequency is 5.96 Hz.

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9 MUX and D Flip Flop
a) Consider the sequential circuit below:
Assume that you want to implement hierarchical Verilog code for this circuit,

using three instantiations of a submodule that has a flip-flop and multiplexer

in it. Write a Verilog module (containing one flip-flop and multiplexer) named
top module for this submodule.

b) Consider the n-bit shift register circuit shown below:

Write a Verilog module named top module for one stage of this circuit, in-
cluding both the flip-flop and multiplexers.

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10 Sequence Generator
Design the following sequence generator module:

0 → 1 → 1 → 1 → 2 → 2 → 3 → 4 → 5 → 7 → 9 → 12 → 16 → 21 ...

Assume the sequence goes on forever until the circuit is reset. All the flops
should be positive edge triggered with asynchronous resets (if any).

10.1 Interface Definition

seq o : sequence output on every cycle

10.2 Interface Requirements

1. The generator should produce output every cycle.
2. You can assume that the sequence generator would never overflow.

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11 Sequence Detector with Finite State Machines
A Mealy Machine changes its output on the basis of its present state and cur-
rent input. A Moore Machine’s output depends only on the current state. It
does not depend on the current input. We will observe this designing sequence
detector with Moore and Mealy FSM.

Inputs are d in, clk and rst signals.

Output is d out.

11.1 Mealy FSM

According to the figure shown below, if the input value equals 1, the state should
be changed to S1, and the output value will be equal to 0. Otherwise, we don’t
need to change the state. As a result, the output value changes based on the
state and input. Remember that the output value will be equal to 1 when the
sequence 1011 is detected.

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11.2 Moore FSM
As shown below, output signal does not depend on current input. Output value
should be equal to 0 except S4 state and it should not be changed on the basis
of input value.

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12 Cypher Detector
In this assignment, you will design cypher detector to be used for security. It
will detect a particular number sequence incoming from an input.

Implement Control Unit and Datapath. Control Unit will be designed as 3

always blocks.

Your design will get a 16-bit number showing the cypher. For instance, if the
cypher is 1-2-3-4 then the 16-bit input will be 0100 0011 0010 0001

The second input is 4-bit from where you will read numbers sequentially.

Third input will be the read input, which will be made 1 when the 4-bit in-
put is ready. If read input is 0 you will not read the 4-bit as it is not ready.
Read each 4-bit number only at the positive edge of the read input.

The last inputs are reset and clock signals.

The first output of your design will be 1-bit signal, which becomes 1 only after
the right cypher numbers are collected.

The second output will be 8-bits and will show the sum of all numbers un-
til the right cypher is detected.

An Example Case:

Cypher: 0010 0110 0000 0001 (Cypher is 2-6-0-1)

4-bit inputs: 0000-0001-0011-0000-0011-0100-0001-0000-0010-0001-0001-0000-

0110-0010

The fist output will become 1 after the last four numbers are observed.

The second output will be 24, i.e. 0001 1000.

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13 Block RAM (BRAM)
FPGAs contain some fixed and specialized Hard IP resources, and one of these
resources is BRAM (Block RAM). BRAM is designed for data storage purposes
and can be used in different modes (Single Port, Dual Port, True Dual Port).

parameter RAM WIDTH = 16,

parameter RAM DEPTH = 1024

13.1 Single Port Block RAM

Single-port Block RAM (BRAM) is a type of memory block available in FPGAs
(Field-Programmable Gate Arrays) that has a single data input and output
port. It is used for storing data and provides access to that data through a
single interface. Both writing and reading operations occur through a single
port.

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13.2 Simple Dual Port Block RAM
When the block RAM is used as Simple Dual Port memory, independent read
and write operations can occur simultaneously, where port A is designated as
the read port and port B as the write port. When the read and write port access
the same data location at the same time, it is treated as a collision, identical to
the port collision in true dual-port mode. Versal devices support these modes
when the block RAM is used as SDP memory (READ FIRST, WRITE FIRST,
NO CHANGE). The default mode is NO CHANGE. WRITE FIRST outputs
the newly written data onto the output bus. READ FIRST outputs the pre-
viously stored data while new data is being written. NO CHANGE maintains
the output previously generated by a read operation.

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13.3 True Dual Port Block RAM
Unlike Simple Port BRAM, both ports of True Dual Port BRAM can perform
both read and write operations.

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13.4 Write Modes
WRITE FIRST

READ FIRST

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NO CHANGE

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14 Function, Event and Task
14.1 Function
First, Why need function ?

1. It makes code more readable.

2. We can reuse the code by function.
Second, the difference between function and task.

1. A function must execute in one simulation time unit.

A task can contain time-controlling statements.
2. A function cannot enable a task, it can call another function
A task can enable other tasks and functions
3. A function must have at least one input argument
A task can have zero or more arguments of any type.
4. A function returns a single value.
A task does not return a value.
Write a function is used to count how many zero in one byte data.
Then, write a top module and include the function file inside the
module.

14.2 Task
Why need Task ?
1. We can reuse the code using task
2. Task makes the code more readable.
You should create two files;

1. task max.v : it includes one task named task max

2. task max top : it is the top file which call the task max
You should compare two one byte input data, then output will be
greater data. Insıde the top module, include the task max.v file.

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14.3 Event
What is Event ?
Event is like an interrupt which can trigger some code to run. It is very useful
in an testbench.
How to capture event ? @(event name);
Create a testbench, use an event to trigger a reset wire. Use two
event; reset trigger and reset done trigger. First, wait for reset trigger
event, then change the reset level. After it is triggered, observe the
trigger time and wait 20ns. At the end of the event, reset should be
zero again and trigger the reset done event.

You can set input arguments manually using Force Constant to perform first
two task.

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15 Serial Adder
Design a serial adder. It takes 8-bit inputs A and B and adds them in a serial
fashion when the go(start) input is set to 1. The result of the operation is
stored in a 9-bit sum register.

A block diagram of the circuit is shown in Figure below. It consists of three

shift registers, a full-adder, a flip-flop to store carry-out signal from the full
adder and a finite state machine. The shift registers A and B are loaded with
the values of A and B. After the start signal is set to high, these registers are
shifted right one bit at a time. At the same time the least-significant bits of A
and B are addded and the result is stored into the shift register sum. Once all
bits of A and B have been added, the circuit stops and displays the sum until
a new addition is requested.

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16 Synchronous FIFO
16.1 FIFO Basics
1. Can be made of registers or BRAM
Register based = small
BRAM based = big
2. Can use unique or shared clock
3. Never write to Full FIFO (overflow)

4. Never read from Empty FIFO (underflow)

5. Figure out how to write code using Empty/Full flags

16.2 Synchronous FIFO

In a synchronous FIFO, data is written into and read from the FIFO using clock
signals that are synchronized between the input and output sides.

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 Do not use Xilinx IP. Some conditions is describes as follows;

But if you want to create FIFO using Xilinx IP. Here is some informations about
implementation.

Common clok = Synchronous

Independent = Asynchronous
Buitin FIFO = It consumes less FPGA resources than Block RAM because there
is already exist a FIFO so you don’t have to handle some stuff such as address
and I assume Builtin FIFO also uses the Block RAM as memory storage. You
cannot choose Data Count in Builtin FIFO.
You can also add Almost Empty and Almost Full Flags in your design.

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17 Asynchronous FIFO
Asynchronous FIFO is crucial for Clock Domain Crossing. Ports operate at
different clock frequency.

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 Block Diagram of Asynchronous FIFO is described as follows. Please read
provided documents on Trello for better understanding.

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18 AMBA APB Protocol
Sam is a fan of the AMBA APB protocol and has taken up the challenge to
design a block which converts certain input events to APB transactions. The
design takes three different inputs and generates an APB transaction to a single
slave. Whenever any input is asserted, Sam wants to send out an APB trans-
action to an address reserved for the particular event. Sam needs your help to
design the events to APB converter.

All the flops (if any) should be positive edge triggered with asynchronous
resets.

18.1 Interface Definition

The block takes three single bit inputs:

event a i
event b i
event c i

The output APB transaction uses the following signals:

apb psel o
apb penable o
apb paddr o[31:0]
apb pwrite o
apb pwdata o[31:0]
apb pready

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 The APB transaction should be generated whenever any of the input event
is asserted. The generated APB transactions should always be an APB write
transaction. Hence the interface doesn’t contain the apb prdata i input.

18.2 Interface Requirements

1. The APB transaction must comply with the AMBA APB protocol speci-
fications.
2. The three event inputs are mutually exclusive i.e. there can be atmost
one event asserted on a cycle.
3. The APB transaction generated due to Event A should be sent to address
0xABBA0000
4. The APB transaction generated due to Event B should be sent to address
0xBAFF0000

5. The APB transaction generated due to Event C should be sent to address

0xCAFE0000
6. The write data should give the count of the number of events seen since
the last write for that particular event.

7. The APB interface guarantees that the pready signal would be asserted
within 10 cycles for a particular transaction without any pslverr. Hence
the interface doesn’t contain the pslverr input.
8. Back to back APB transactions aren’t supported by interface hence there
should a cycle gap before the next APB transaction is generated.

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 9. The event input interface guarantees fairness amongst the three events
such that there cannot be more than 10 pending events for any input
event.

Note that: The above fairness scheme allows you to implement the address
selection logic for the APB request in any given order of priority for the inputs.

18.3 Sample Simulation

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19 Parametric UART Module
In this experiment, you will design a parametric UART Module. This Module
used as a computer hardware device for asynchronous serial communication in
which the data format and transmission speeds are configurable. It sends data
bits one by one, from the least significant to the most significant, framed by start
and stop bits so that precise timing is handled by the communication channel.
The band rate will be parametric in our design. This module will be connected
to FIFO. Final design will look like as follows.

Connect your UART modules to the previously designed FIFO module. UART
Module will receive input from FPGA GPIO pin and received message should
be saved to FIFO. IF the FIFO is empty, ”e” letter should be send to UART
Tx module in ASCII encoding. When button on the FPGA is pressed, first
data should be displayed at the FPGA LEDs. Plan your constraints from pin
planner. (data inputs from switches, data output to LEDs, enable and reset
inputs from buttons.)

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20 FIFO Flush
You are asked to a design a FIFO which has different data widths on the read
and the write interface. The write interface can send 4-bits per cycle whereas
the read interface expects 32-bits per cycle. Along with the asymmetrical data
widths the FIFO should also support the ability for the read interface to issue
a flush request. This is needed whenever the write interface doesn’t have the
complete 32-bits of data but the read interface wants to read from FIFO and
thus can issue a flush. During a flush request the FIFO should send all of the
data written prior and on the cycle the flush request was seen. Once all of the
data is read the flush can be marked as completed. FIFO should support the
ability to write new data while the flush request is being serviced. The FIFO
must be sized such that it is able to store 128-bits of data exactly.

20.1 Interface Definitions

The interface to the fifo consists of the following ports:

fifo wr valid i → Input to the module which signals that write data is valid
fifo wr data i → The 4-bit write data input
fifo data avail o → Output flag which tells that a read can be issued
fifo rd valid i → Input to the module which signals 32-bit data is read
fifo rd data o → 32-bit read data associated given as output
fifo flush i → Fifo flush input to the module
fifo flush done o → Output signal which marks the flush as complete

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20.2 Interface Requirements
1. The interface guarantees that the write request will never be seen whenever
fifo has 128-bits of data
2. The interface guarantees that the fifo rd valid i will only be asserted if the
fifo data avail o signal is high. The fifo rd data o should be sent on the
same cycle as when the fifo rd valid i is seen
3. The interface guarantees that the flush request would only be asserted if
the fifo isn’t empty
4. The fifo flush i signal would remain asserted until the fifo flush done o
output is seen
5. In case fifo has partial data (data less than 32-bits) during a flush request,
the specifications allow the fifo data to be padded with 0xC to form the
complete 32-bits worth of data
6. The data written on the same cycle as when the flush request was asserted
should also be flushed before the fifo flush done o signal is asserted. This
implies that the flush data should only consist of the data already stored
in the fifo and the data written (if any) on the same cycle as the flush
request was asserted.

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 7. The fifo should allow any new data to be written into the fifo while the
flush is being serviced. The new data written one cycle after the flush
request should not be given out as part of the flush request
8. All the flops (if any) should be positive edge triggered with asynchronous
resets

20.3 Sample Simulation

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