ShanghaiTech University

School of Information Science and Technology

EE115A Analog Circuits I

Homework 4
Due:11/11 11:59 p.m.
Read the chapter 7.

1. Consider the amplifier of Fig. 1(a) for the case 𝑉𝐷𝐷 = 5 V, 𝑅𝐷 = 24 kΩ, 𝑘𝑛′ (W/L)
= 1 mA/𝑉 2 , and Vt= 1 V.
a) Find the coordinates of the two end points of the saturation-region segment of
the amplifier transfer characteristic, that is, points A and B in Fig. 1(b).
b) If the amplifier is biased to operate with an overdrive voltage 𝑉𝑂𝑉 of 0.5 V,
find the coordinates of the bias point Q on the transfer characteristic. Also, find
the value of 𝐼𝐷 and of the incremental gain Av at the bias point.
c) For the situation in (b), and disregarding the distortion caused by the
MOSFET’s square-law characteristic, what is the largest amplitude of a sine-
wave voltage signal that can be applied at the input while the transistor remains
in saturation? What is the amplitude of the output voltage signal that results?
What gain value does the combination of these amplitudes imply? By what
percentage is this gain value different from the incremental gain value
calculated above? Why is there a difference?

Figure. 1(a) Figure. 1(b)

2. For the amplifier in the figure below, let 𝑉𝐷𝐷 = 2 V, 𝑅𝐷 = 15 kΩ, Vt= 0.5 V, 𝐾𝑛′ =
0.4 mA/𝑉 2 , W/L = 12.5, 𝑉𝐺𝑆 =0.7 V, and λ = 0.
a) Find the dc current 𝐼𝐷 and the dc voltage 𝑉𝐷𝑆 .
b) Find gm.
c) Find the voltage gain.
 d) If 𝑣𝑔𝑠 = 0.015 sin ωt volts, find 𝑣𝑑𝑠 assuming that the small-signal
approximation holds. What are the minimum and maximum values of 𝑣𝐷𝑆 ?
1 1
e) Use 𝑖𝐷 = 2 k n (VGS + vgs − Vt )2 = 2 k n (VGS − Vt )2 + k n (VGS − Vt )vgs +

1
k n vgs 2 to determine the various components of 𝑖𝐷 . Using the identity
2

1 1
𝑠𝑖𝑛2 𝑤𝑡 = 2 − 2 𝑐𝑜𝑠2𝑤𝑡, determine the second-harmonic distortion defined as
the ratio of the component of 𝑖𝐷 of frequency 2ω to the component of 𝑖𝐷 of
frequency ω, multiplied by 100.

3. Figure below shows a discrete-circuit amplifier. The input signal 𝑣𝑠𝑖𝑔 is coupled
to the gate through a very large capacitor (shown as infinite). The transistor source
is connected to ground at signal frequencies via a very large capacitor (shown as
infinite). The output voltage signal that develops at the drain is coupled to a load
via a very large capacitor (shown as infinite). All capacitors behave as short circuits
for signals and as open circuits for dc.
a) If the transistor has Vt= 1 V, and kn = 4 mA/𝑉 2 , verify that the bias circuit
establishes 𝑉𝐺𝑆 = 1.5 V, 𝐼𝐷 = 0.5mA, and 𝑉𝐷 = +7.0 V. That is, assume
these values, and verify that they are consistent with the values of the circuit
components and the device parameters.
b) Find gm and ro if 𝑉𝐴 = 100 V.
c) Draw a complete small-signal equivalent circuit for the amplifier, assuming all
capacitors behave as short circuits at signal frequencies.
d) Find Rin, 𝑣𝑔𝑠 /𝑣𝑠𝑖𝑔 , 𝑣𝑜 /𝑣𝑔𝑠 , and 𝑣𝑜 /𝑣𝑠𝑖𝑔 .
4. Two identical CS amplifiers are connected in cascade. The first stage is fed with a
source 𝑣𝑠𝑖𝑔 having a resistance 𝑅𝑠𝑖𝑔 = 100 kΩ. A load resistance 𝑅𝐿 = 10 kΩ is
connected to the drain of the second stage. Each MOSFET is biased at 𝐼𝐷 = 0.4
mA and operates with 𝑉𝑂𝑉 = 0.4 V. Each stage utilizes a drain resistance 𝑅𝐷 =
10kΩ.
a) Sketch the equivalent circuit of the two-stage amplifier.
b) Calculate the overall voltage gain Gv

5. (need simulation remember to change the transistor parameters as you did in HW3)
Design the circuit in figure below so that the transistor operates in saturation with
𝑉𝐷 biased 1 V from the edge of the triode region, with 𝐼𝐷 = 1 mA and 𝑉𝐷 = 3 V,
for each of the following two devices (use a 10-µA current in the voltage divider):
a) |Vt| = 1 V and 𝑘𝑝′ W/L = 0.5 mA/𝑉 2
b) |Vt| = 2 V and 𝑘𝑝′ W/L = 1 mA/𝑉 2
For each case, specify the values of 𝑉𝐺 , 𝑉𝐷 , 𝑉𝑆 , R1, R2, 𝑅𝑆 , and 𝑅𝐷

6. The NMOS transistor in the CS amplifier shown in figure below has 𝑉𝑡 = 0.75 V
and 𝑉𝐴 = 50 V. Also, 𝑉𝐷𝐷 = 5 V, 𝑅𝐺1 = 750 kΩ, 𝑅𝐺2 = 500 kΩ, 𝑅𝐷 = 10 kΩ,
𝑅𝑆 = 4 kΩ, 𝑅𝑠𝑖𝑔 = 100 kΩ, and 𝑅𝐿 = 10 kΩ.
a) Neglecting the Early effect, verify that the MOSFET is operating in saturation
with 𝐼𝐷 = 0.25 mA and 𝑉𝑂𝑉 =0.25 V. What must the MOSFET’s 𝑘𝑛 be?
What is the dc voltage at the drain?
b) Find Rin and Gv
c) If 𝑣𝑠𝑖𝑔 is a sinusoid with a peak amplitude 𝑣̂𝑠𝑖𝑔 , find the maximum allowable
value of 𝑣̂𝑠𝑖𝑔 for which the transistor remains in saturation. What is the
corresponding amplitude of the output voltage?
d) What is the value of resistance R that needs to be inserted in series with
capacitor 𝐶𝑆 in order to allow us to double the input signal 𝑣̂𝑠𝑖𝑔 ? What output
voltage now results?