國立清華大學

電機工程學系
102 學年度第一學期

EE-6250
超大型積體電路測試
VLSI Testing

授課教師：黃錫瑜

2013 年 Fall Semester

清
華
大
學
電
機
系

超
大
型
積
體
電
路
測
試

講
義
 國立清華大學電機系

EE-6250
超大型積體電路測試
VLSI Testing

Chapter 1
Introduction

Course Flow

Introduction

Fault Modeling

Fault Simulation

Automatic Test Pattern Generation ATPG

IC test
Design-for-Testability and Scan Test DfT

Delay Test

Built-In Self-Test BISG

Test Compression

Board-level test Boundary-Scan Test

Die-to-Die test Parametric Interconnect Testing

Diagnosis Logic Diagnosis

Ch1-2

1
 What You can Benefit from this
Course?
 Values of Acquired Knowledge
- Making ICs more testable
- Makingg ICs/Boards/Systems
y more debuggable
gg
- Making ICs Faster Time-to-Market
- Making ICs Faster Time-to-Volume

 Academic Training
- Testing is a rich field as you will know.
- Testing is a good topic for MS/Ph.D. theses.

 Career Development
- IC 設計公司 (讓晶片的可測試性更高)
- 半導體廠 (故障診斷，良率追蹤與分析與改善)
- 測試產業 (量產測試之規劃與執行)
- 電子系統廠 (系統故障診斷，可靠度分析與改善)
Ch1-3

Chip Design & Manufacturing Flow

IC Fabrication
Idea
Wafer
(hundreds
(h d d off di
dies))
Architecture Design
Sawing & Packaging

Block
diagram Final chips

Circuit & Layout Design Testing

Layout
customers
Bad chips Good chips
Ch1-4

2
 Design Verification, Testing
and Diagnosis

• Design Verification:
– Ascertain the design perform its specified
behavior

• Testing:
– Exercise the system and analyze the response to
ascertain whether it behaves correctly after
manufacturing

• Diagnosis:
– To locate the cause(s) of misbehavior after the
incorrect behavior is detected

Ch1-5

Manufacturing Defects

• Material Defects
– bulk defects (cracks, crystal imperfections)
– surface impurities
• Processing Faults
– missing contact windows
– parasitic transistors
– oxide breakdown
• Time-Dependent Failures
– dielectric breakdown
– electro-migration
• Packaging Failures
– contact degradation
– seal leaks
Ch1-6

3
 Faults, Errors and Failures

• Fault:
– A physical defect within a circuit or a system
– May or may not cause a system failure
• Error:
– Manifestation of a fault that results in incorrect circuit
(system) outputs or states
– Caused by faults
• Failure:
– Deviation of a circuit or system from its specified behavior
– Fails to do what it should do
– Caused by an error

• Fault ---> Error ---> Failure

Ch1-7

Reliability Test

• Temperature Related
– Hi-Temperature Life Test
– Low-Temperature Life Test
– Temperature-Cycling Test
• Humidity Test
• Salt Mist Test
• UV (Ultra-Violet) Test
• ESD Test
– ESD stands for Electro-Static Discharge
• Whole Mechanical Test

Ch1-8

4
 Detailed Reliability Test Items
• Temperature Related
– Operation: 00C/120hr ~ 700C/120hr (商規)
– Operation: -400C/120hr ~ 850C/120hr (工規)
– Storage: -400C/200hr ~ 850C/500hr
– Junction Temperature: Max. 950C
• Humidity Test
– Operation: 250C/95% humidity (商規)
– Operation: 400C/95% humidity (工規)
– Storage: 850C/95% humidity
• Salt Mist Test
– Salt Water Spray
• UV Test
– UV (254nm), 15Ws/cm2
– X-ray exposure, 0.1Gy/1hr
• ESD Test
– For example, For Contact Pads, ±4KV, Human Body Mode
• Whole Mechanical Test
– Vibration (15G, 10 to 2KHz), Impact, Torque, Bending, Drop test
Ch1-9

Scenario of Manufacturing Test

TEST VECTORS

Manufactured
Circuits

CIRCUIT RESPONSE

CORRECT Comparator PASS/FAIL

RESPONSES

Ch1-10

5
 Courses on Agilent 93000 at CIC

Host
Test head

Sample Information: (What to expect from that kind of course)

Ch1-11

Purpose of Testing

• Verify Manufacturing of Circuit

– Improve System Reliability
– Diminish System Cost
• Cost of repair
– goes up by an order of magnitude each step
away from the fab. line

1000
1000

500
Cost 100
100

Cost
Per per 50
10
10

Faultfault
(Dollars)
5
(dollars)
1
1

0.5
IC
IC Test
Test Board
Board
Test System
System
Test Warranty
Warranty
Repair
Test Test Repair
B. Davis, “The Economics of Automatic Testing” McGraw-Hill 1982
Ch1-12

6
 Testing and Quality

Shipped Parts
ASIC
Testing
Fabrication Yield:
Quality:
Fraction of Defective parts
Good parts Per Million (PPM)

Or Parts Per Billion

(
(PPB))
R j t
Rejects

Quality of shipped part is a function of

yield Y and the test (fault) coverage T.

Ch1-13

Fault Coverage

• Fault Coverage T
– Is the measure of the ability of a set of tests to
detect a given class of faults that may occur on
the device under test (DUT)

No. of detected faults

T=
No. of all possible faults

Ch1-14

7
 Defect Level

• Defect Level
– Is the fraction of the shipped parts that
are defective (單位 ppm or ppb)

DL = 1 – Y(1-T)

Y: yield
T: fault coverage

Ch1-15

Defect Level v.s. Fault Coverage

Defect Level
1.0 Y = 0.01
Y = 0.1
01

0.8 Y = 0.25

0.6
Y = 0.5
0.4
Y = 0.75
02
0.2 Y = 0.9
09

0 20 40 60 80 100
(Williams IBM 1980) Fault Coverage ( % )

High fault coverage Low defect level

Ch1-16

8
 DPM v.s. Yield and Coverage

Yield Fault Coverage Defective PPM

50% 90% 67,000

75% 90% 28,000
90% 90% 10,000
95% 90% 5,000
99% 90% 1,000

90% 90% 10,000

90% 95% 5,000
90% 99% 1,000
90% 99.9% 100

Ch1-17

Why Testing Is Difficult ?

• Test application time could explode for

exhaustive testing of VLSI
– For a combinational circuit with 50 inputs, we need
250 = 1.126x1015 test patterns.
– Assume one test per 10-7sec, it takes 1.125x108sec =
3.57yrs. to test such a circuit.
– Test generation for sequential circuits are even more
difficult due to the lack of controllability and
observability at flip-flops (latches)

• Functional testing
– may NOT be able to detect the physical faults

Ch1-18

9
 DEC Alpha Chip (1994)

• 64-bit RISC
• 200 MHz
MH
• 400 MIPS
• 200 Mflops
• 16.8 x 13.9 mm2 die
• 0.68 million transistors
• 431-pin package
• 3.3 V
• 30 W power consumption

Ch1-19

The Infamous Design/Test Wall

30 years of experience proves that

test after design does not work!

Oh no!
What does
Functionally correct! this chip do?!
We're done!

Design Engineering Test Engineering

Ch1-20

10
 Old Design & Test Flow

spec.
Low-quality test patterns
design flow  high defect level

test
layout
patterns

manufacturing

Ch1-21

New Design and Test Flow

spec.
Introduces circuitry to
make design testable
Design flow DFT flow

better test good

layout chips
patterns

manufacturing

Ch1-22

11
 New Design Mission

• Design circuit to optimally satisfy their

design
g constraints in terms of area,,
performance and testability.

How high is the fault coverage

TESTABILITY we can achieve?

Power Consumption

PERFORMANCE AREA

Ch1-23

12
 國立清華大學電機系

EE-6250
超大型積體電路測試
VLSI Testing

Chapter 2
Fault Modeling

Functional v.s. Structural Testing

• I/O functional tests inadequate for

manufacturing
f t i

• Exhaustive testing is prohibitively

expensive

Question: How to Generate Compact yet High-Quality Test Vectors?

Ch2-2

1
 Why Fault Model ?

• Fault model identifies target faults

– Model faults most likely to occur
• F
Fault
lt model
d l li
limits
it th
the scope off ttestt
generation
– Create tests only for the modeled faults
• Fault model makes effectiveness
measurable by experiments
– Fault coverage can be computed for specific test
patterns to reflect its effectiveness
• Fault model makes analysis possible
– Associate specific defects with specific test patterns
Scientific Study: Hypothesis (Assumption)  Evaluation  Refinement

Ch2-3

Fault Modeling

• Fault Modeling
– Model the effects of physical defects on the
logic function and timing

• Physical Defects
– Silicon Defects
– Photolithographic Defects
– Mask Contamination
– P
Process V
Variation
i ti
– Defective Oxides

Ch2-4

2
 Common Fault Types
Used To Guide Test Generation

• Stuck-at Faults
• Bridging Faults
• Open Faults
• Transistor Stuck-On Faults
• Delay Faults
• IDDQ Faults (Quiescent current at VDD pin)
• Memory
M Faults
F lt

IDDQ Testing: canary in the coalmine, alarming of un-modeled defects

金絲雀

Ch2-5

Single Stuck-At Fault

Faulty Response
Test Vector
Fault-Free Response
0 0

1
1/0
1

1 1/0
stuck-at-0

Assumptions:
• Only One line is faulty
• Faulty line permanently set to 0 or 1
• Fault can be at an input or output of a gate

Ch2-6

3
 Multiple Stuck-At Faults

• Several stuck-at faults occur at the

same time
– Mostly used in logic diagnosis

• For a circuit with k lines

– there are 2k single stuck-at faults
– there are 3k-1 multiple stuck-at faults
• A line could be stuck-at-0, stuck-at-1, or fault-free
• One out of 3k resulting circuits is fault-free

Ch2-7

Why Single Stuck-At Fault Model?

• Complexity is greatly reduced

– Many different physical defects may be modeled by the
same logical single stuck-at
stuck at fault
• Stuck-at fault is technology independent
– Can be applied to TTL, ECL, CMOS, BiCMOS etc.
• Design style independent
– Gate array, standard cell, custom VLSI
• Detection capability of un-modeled defects
– Empirically, many defects accidentally detected by test
derived based on single stuck-at fault
• Cover a large percentage of multiple stuck-at
faults
Single SA model survives well (due to its simplicity and effectiveness)
Ch2-8

4
 Multiple Faults

• Multiple stuck-fault coverage by

single-fault tests of combinational
circuit:
– 4-bit ALU (Hughes & McCluskey, ITC-84)
All double and most triple-faults covered.
– Large circuits (Jacob & Biswas, ITC-87)
p faults covered for circuits
Almost 100% multiple
with 3 or more outputs.

Ch2-9

Bridging Faults

• Two or more normally distinct points

(lines) are shorted together erroneously
– Logic
L i effect
ff t d
depends
d on ttechnology
h l
– Wired-AND for TTL
A f A f
B g B g

– Wired-OR for ECL

A f A f
B g B g

– CMOS ?

Ch2-10

5
 Bridging Faults For CMOS Logic

• The result
– could be AND-bridging or OR-bridging
– depends on the inputs

VDD
E.g., (A=B=0) and (C=1, D=0) VDD
(f and g) are AND-bridging fault
A
pull to VDD C

f
bridging g
B A
C D
pull to zero
GND
GND Ch2-11

CMOS Transistor Stuck-On

IDDQ
VDD
Example:
N-type transistor ?
is always ON

0 stuck-on

GND
• Transistor Stuck-On
– May
y cause ambiguous
g logic
g level
– Depends on the relative impedances of the pull-up and pull-
down networks
• When Input Is Low
– Both P and N transistors are conducting, causing increased
quiescent current, could be detected by IDDQ test
Ch2-12

6
 CMOS Transistor Stuck-Open (I)

• Transistor stuck-open
– May cause the output to be floating
– The fault exhibits sequential behavior
– Need two-pattern test (to set it to a known value first)

stuck-open

Responses:
Fault-free 01
A two-pattern test Faulty 00

10

Ch2-13

Fault Coverage in a CMOS Chip

100 stuck faults only

%)
Coverage (%

80

60 stuck and open faults

40

20

0
1000 2000 3000

Test Vectors
Ch2-14

7
 Summary of Stuck-Open Faults

• First Report:
– Wadsack, Bell System Technology, J., 1978
• Recent Results
– Woodhall et. al, ITC-87 (1-micron CMOS chips)
– 4552 chips passed the test
– 1255 chips (27.57%) failed tests for stuck-at faults
– 44 chips (0.97%) failed tests for stuck-open faults
– 4 chips with stuck-open faults passed tests for stuck-at faults
• Conclusion
– Stuck-at faults are about 20 times more frequent than stuck-
open faults
– About 91% of chips with stuck-open faults may also have
stuck-at faults
– Faulty chips escaping tests for stuck-at faults = 0.121%

Ch2-15

Functional Faults

• Fault effects modeled at a higher

level than logic for functional
modules, such as
– Decoder
– Multiplexers
– Adders
– Counters
– ROMs

Ch2-16

8
 Functional Faults of Decoders

A’B’
A
AB’
Decoder
A’B
B
AB

• f(Li/Lk): One active output, but wrong one

– Instead of input line Li, Lk is selected

• f(Li/Li+k): More than one active outputs

– In addition to line Li, Lk is also selected

• f(Li/0): No active output

– None of the lines is selected

Ch2-17

Memory Faults

• Parametric Faults
– Any fault that causes the response to deviate from its
fault-free nominal value by some amount
– Ex. A cell with parametric delay fault (with for
example 93% more than normal)
– Due to all kinds of factors like PVT variation
• Functional Faults
– Stuck Faults in Address Register, Data Register,
and Address Decoder
– Cell Stuck Faults
– Adjacent Cell Coupling Faults
– Pattern-Sensitive Faults

Ch2-18

9
 Memory Faults

• Pattern-sensitive faults: the presence of a

f lt signal
faulty i l depends
d d on the
th signal
i l values
l
of the neighboring cells
– Mostly in DRAMs

0 0 0 a=b=0  d=0
0 d b a=b=1  d=1
0 a 0

• Adjacent cell coupling faults

– Pattern sensitivity between a pair of cells

Ch2-19

Memory Testing

• Test could be time-consuming

– The length
g of the test sequence
q for memory
y testing
g
could be prohibitively long

• Example:
– A pattern sensitive test is 5n2 long for an n-bit RAM
– Testing a 1-M bit chip at 10ns pattern would take 14
hours
– For a 64-M bit chip, it would take 6 years

Ch2-20

10
 PLA Faults

• Stuck-at Faults
• Cross-point Faults
– Extra/Missing Transistors

• Bridging Faults
• Break Faults

Ch2-21

Stuck-at Faults in PLA

• s-a-0 & s-a-1 faults

– on inputs, input inverters, product lines, and
outputs are easy to simulate in its gate-level
gate level
model

A B C f1 f2 A B C

Gate-level model

P1 P1
f1

P2
f2

AND-Array OR-Array P2

Ch2-22

11
 Missing Cross-Point Faults in PLA

• Missing Crosspoint in AND-array

– Growth Fault
• Missing Crosspoint in OR
OR-array
array
– Disappearance fault

Equivalent stuck fault

A B C f1 f2 A B C representation

Growth
s-a-1
s-a-0
x x f1

f2

Disappearance
Ch2-23

Extra Cross-Point Faults in PLA

• Extra cross-point in AND-array

– Shrinkage or disappearance fault
• Extra cross-point
cross point in OR-array
OR array
– Appearance fault

Equivalent stuck fault

A B C representation
A B C f1 f2

f1

f2
Disapp.
Shrinkage "1" "0"
Appearance
Ch2-24

12
 Summary of PLA Faults

• Cross-Point Faults
– 80 ~ 85% covered by stuck
stuck-fault
fault tests
– Layout-dependence in folded PLA

• Bridging Faults
– 99% covered by stuck-fault tests
– Layout-dependence in all PLAs

– (Ref: Agrawal & Johnson, ICCD-86)

Ch2-25

Delay Testing

• Chip with Timing Defects

– may pass the DC stuck-fault testing
testing, but fail
when operated at the system speed
– For example, a chip may pass the test under 10
MHz operation, but fail under 100 MHz

• Delay Fault Models

– Gate-Delay
y Fault
– Path-Delay Fault

Ch2-26

13
 Gate-Delay Fault (I)

• Slow to Rise
– x is slow to rise when channel resistance R1 is
abnormally
b ll hi
highh

VDD VDD

R1

X
X
HL

Cload

Ch2-27

Gate-Delay Fault (II)

slow

• Test Based on Gate-Delay Fault

– May not detect those delay faults that result
from the accumulation of a number of small
incremental delay defects along a path !!
(Disadvantage)

Ch2-28

14
 Path-Delay Fault

• Associated with a Path (e.g., A-B-C-Z)

– Whose delay exceeds the clock interval
• More
M complicated
li t d th
than gate-delay
t d l f lt
fault
– Because the number of paths grows exponentially

B
A Z

Ch2-29

Fault Detection

• Fault Activation
• Fault Propagation

15
 Definition Of Fault Detection

• A test (vector) t detects a fault f iff

– t detects f  z(t) ≠zf(t)

• Example
E l
X1
Z1
x
s-a-1 Z1=X1X2 Z2=X2X3
X2
Z1f =X1 Z2f =X2X3

Z2
X3

The test (x1,x2,x3) = (100) detects f because

z1(100)=0 while z1f (100)=1
Ch2-31

Fault Detection Requirement

• A test t that detects a fault f

– (1) Activate f (or generate a fault effect at the site of
the fault)
– (2) Propagate the fault effect to a primary output w
• Sensitized Line:
– A line whose faulty value is different from its fault-free
one is said to be sensitized by the test in the faulty
circuit
• Sensitized Path:
– A path composed of sensitized lines is called a
sensitized path

Ch2-32

16
 Fault Sensitization
G1
X1 1
X2 0 G3
1
X3 1
1
0/1
s-a-1
z
G2 G4
0/1 0/1
X4 1

z (1011)=0 zf (1011)=1
1011 detects the fault f (G2 stuck-at 1)
v/vf : v = signal value in the fault free circuit
vf = signal value in the faulty circuit

Ch2-33

Detectability

• A fault f is said to be detectable

– if there exists a test t that detects f ;
otherwise,
f is an undetectable fault

• For an undetectable fault f

– No test can simultaneously activate f and
create a sensiti
sensitized
ed path to a primar
primary o
output
tp t

Ch2-34

17
 Undetectable Fault

can be removed !
a
G1

s-a-0
b x z

• G1 output stuck-at-0 fault is undetectable

– Undetectable faults do not change the function of the circuit
– The related circuit can be deleted to simplify the circuit

Ch2-35

Test Set

• Complete detection test set:

– A set of tests that detect any detectable faults in a
class of faults
• The quality of a test set
– is measured by fault coverage
• Fault coverage:
– Fraction of faults that are detected by a test set
• The fault coverage
– can be determined by fault simulation
– >95% is typically required for single stuck-at fault
model
– >99.9% in IBM

Ch2-36

18
 Typical Test Generation Flow

Start Select a target fault

Generate a test (to be further discussed)

for the target fault

Fault simulation (to be further discussed)

Discard detected faults Fault dropping

yes no
More faults ? Done

Ch2-37

Fault Collapsing

• Fault Equivalence
• Fault Dominance
• Checkpoint
Ch k i t ThTheorem

19
 Fault Equivalence

• Distinguishing test
– A test t distinguishes
disting ishes faults
fa lts  and  if

Z t   Z t  1

• Equivalent Faults
– Two faults,  &  are said to be equivalent
in a circuit , iff the function under  is equal to
the function under  for any input combination
(sequence) of the circuit.
– No test can distinguish between and 

Ch2-39

Fault Equivalence

• AND gate:
– all s-a-0 faults are equivalent
x
x s-a-0
• OR gate:
s-a-0
– all s-a-1 faults are equivalent
• NAND gate: same effect
– all the input s-a-0 faults and the output
s-a-1 faults are equivalent
• NOR gate:
– all input s-a-1 faults and the output
s-a-0 faults are equivalent
• Inverter:
– input s-a-1 and output s-a-0 are equivalent
input s-a-0 and output s-a-1 are equivalent

Ch2-40

20
 Equivalence Fault Collapsing

• n+2 instead of 2(n+1) faults need to

be considered for n-input
input gates

s-a-1 s-a-0
s-a-1 s-a-1
s-a-0 s-a-0
s-a-1 s-a-0

s-a-1 s-a-0
s-a-1 s-a-1
s-a-0 s-a-0
s-a-1 s-a-0
Ch2-41

Equivalent Fault Group

• In a combinational circuit
– Many faults may form an equivalent group
– Th
These equivalent
i l t ffaults
lt can bbe ffound
dbby sweeping
i the
th
circuit from the primary outputs to the primary inputs

s-a-0 s-a-1
x
x

s-a-1
x

Three faults shown are equivalent !

Ch2-42

21
 Finding Equivalent Group

• Construct a Graph
– Sweeping the netlist from PO’s to PI’s
– Wh
When a fault
f lt  is
i equivalent
i l t tto a ffault
lt ,
 then
th an edge
d iis
connected between then
– Transitive Rule:
• When  connects  and  connects , then  connects 

a s-a-0
a d s-a-0
a s-a-1
b b s-a-0 d s-a-1
1
d

e s-a-0
c e e s-a-1

Equivalent group = { a/0, b/0, d/0, c/1, e/1}

Ch2-43

Fault Dominance

• Dominance Relation
– A fault  is said to dominate another fault
 in
i a circuit,
i it iff every ttestt ((sequence)) ffor  is
i
also a test (sequence)
for .
– I.e., test-set() > test-set()
– No need to consider fault  for fault detection

Test()  is dominated by 
Test()

Ch2-44

22
 Fault Dominance

• AND gate:
– Output s-a-1 dominates any input s-a-1 Easier-to-test

• NAND gate:
x
– Output s-a-0 dominates any input s-a-1 x s-a-1
• OR gate: s-a-1

– Output s-a-0 dominates any input s-a-0

harder-to-test
• NOR gate:
– Output s-a-1
s a 1 dominates any input s-a-0
sa0
• Dominance fault collapsing:
– The reduction of the set of faults to be analyzed
based on dominance relation

Ch2-45

Stem v.s. Branch Faults

D
x
C: stem of a multiple fanout A
A & B: branches C x
B
x
E
• Detect A sa1:
zt  z f t  CDCE D CE  D CD1
 C  0, D  1
• Detect C sa1:
zt  z f t  CDCE DE  1
 C  0,
0 D  1 or C  0,
0 E  1
• Hence, C sa1 dominates A sa1
• Similarly
– C sa1 dominates B sa1
– C sa0 dominates A sa0
– C sa0 dominates B sa0
• In general, there might be no equivalence or
dominance relations between stem and branch faults Ch2-46

23
 Analysis of a Single Gate

AB C A B C A B C
sa1 sa1 sa1 sa0 sa0 sa0
A
C 00 0 1
B
01 0 1 1
10 0 1 1
11 1 0 0 0

• Fault Equivalence Class Negligible fault

– (A s-a-0, B s-a-0, C s-a-0)

• Fault Dominance Relations
– (C s-a-1 > A s-a-1) and (C s-a-1 > B s-a-1)
• Faults that can be ignored:
– A s-a-0, B s-a-0, and C s-a-1
Ch2-47

Fault Collapsing

• Equivalence + Dominance
– For each n-input gate, we only need to consider
n+1 faults during test generation

s-a-1
s-a-0

s-a-1

Ch2-48

24
 Dominance Graph

• Rule
– When fault  dominates fault , then an arrow is
pointing from  to 
• Application
– Find out the transitive dominance relations among
faults

a s-a-0
a d s-a-0
a s-a-1
b d s-a-1
1
d

e s-a-0
c e e s-a-1

Ch2-49

Fault Collapsing Flow

Start Sweeping the netlist from PO to PI Equivalence

To find the equivalent fault groups analysis

Sweeping the netlist Dominance

To construct the dominance graph analysis

Discard the dominating faults

Select a representative fault from

each remaining equivalence group

Generate collapsed fault list Done

Ch2-50

25
 Prime Fault

 is a prime fault if every fault that is

dominated by  is also equivalent to


Ch2-51

Why Fault Collapsing ?

• Memory and CPU-time saving

• Ease testing generation and fault
simulation

* 30 total faults  12 prime faults

Ch2-52

26
 Checkpoint Theorem

• Checkpoints for test generation

– A test set detects every fault on the primary inputs
and fanout branches is complete
– I.e., this test set detects all other faults too
– Therefore, primary inputs and fanout branches form a
sufficient set of checkpoints in test generation
– In fanout-free combinational circuits, primary inputs
are the sole checkpoints

Stem is not a checkpoint !

Ch2-53

Why Inputs + Branches Are Enough ?

• Example
– Checkpoints are marked in blue
p g the circuit from PI to PO to examine every
– Sweeping y
gate, e.g., based on an order of (A->B->C->D->E)
– For each gate,
output faults are detected if every input fault is detected

A a

D
B

E
C

Ch2-54

27
 Fault Collapsing + Checkpoint

• Example:
– 10 checkpoint faults
– a s-a-0 <=> d s-a-0 , c s-a-0 <=> e s-a-0
b s-a-0 > d s-a-0 , b s-a-1 > d s-a-1
– 6 tests are enough

a
d
f
h
b
g
e
c
Ch2-55

28
 國立清華大學電機系

EE-6250
超大型積體電路測試
VLSI Testing

Chapter 3
Fault Simulation

Outline

• Fault Simulation for Comb. Ckt

– Basic
B i off L
Logic
i Si
Simulation
l ti
– Parallel Fault Simulation
– Deductive Fault Simulation
– Concurrent Fault Simulation

• Approximation Approach
• Techniques for Sequential Circuits

Note: Comb. Ckt: Combinational Circuits

Ch3-2

1
 Why Fault Simulation ?

• To evaluate the quality of a test set

– I.e., to compute its fault coverage

• Part of an ATPG program

– A vector usually detects multiple faults
– Fault simulation is used to compute the faults
accidentally detected by a particular vector

• To construct fault-dictionary
– For post-testing diagnosis

• To Evaluate the fault coverage of a

functional patterns

Ch3-3

Conceptual Fault Simulation

Patterns Response
(Sequences) Comparison
(Vectors) Faulty Circuit #n (D/0)

Faulty Circuit #2 (B/1)

Detected?
Faulty Circuit #1 (A/0)

Fault-free Circuit
Primary A B
Inputs D
(PIs) C
Primary Outputs
(POs)
Logic simulation on both good (fault-free) and faulty circuits

Ch3-4

2
 Some Basics for Logic Simulation

• For fault simulation purpose,

– mostly the gate delay is assumed to be zero unless the
delay faults are considered.
considered Our main concern is the
functional faults
• The logic values
– can be either two (0, 1) or three values (0, 1, X)
• Two simulation mechanisms:
– Oblivious compiled-code:
i it is
• circuit i ttranslated
l t d iinto
t a program and
d all
ll gates
t are executed
t d
for each pattern. (may have redundant computation)
– Interpretive event-driven:
• Simulating a vector is viewed as a sequence of value-change
events propagating from the PI’s to the PO’s
• Only those logic gates affected by the events are re-evaluated

Ch3-5

Compiled-Code Simulation

A
B E
Z
C
D

• Compiled code
– LOAD A /* load accumulator with value of A */
– AND B /* calculate A and B */
– AND C /* calculate E = AB and C */
– OR D /* calculate Z = E or D */
– STORE Z /* store result of Z */

Ch3-6

3
 Event-Driven Simulation

1 1 A 0?
0 1 B G1 E
0 1 C G2 Z 0?
00 D

Start Initialize the events at PI’s

In the event-queue

Pick an event
Evaluate its effect

Schedule the newly born events

In the event-queue, if any

yes no
More event in Q ? Done
Ch3-7

Complexity of Fault Simulation

#Gate (G)

#Fault (F)
#Pattern (P)

• Complexity ~ F ‧P‧G
P G ~ O(G3), where G is the no. of gates
• The complexity is higher than logic simulation by a factor of F,
while usually is much lower than ATPG
• The complexity can be greatly reduced using
• Fault dropping and other advanced techniques

Ch3-8

4
Characteristics of Fault Simulation

• Fault activity with respect to fault-free

circuit
– is
i often
ft sparse both
b th in
i time
ti and
d in
i space.

• For example
– F1 is not activated by the given pattern, while F2
affects only the lower part of this circuit.

0 F1(s-a-0)
×
×
1
F2(s-a-0)
1
×
Ch3-9

Fault Simulation Techniques

• Serial Fault Simulation

– trivial single-fault single-pattern

• Parallel Fault Simulation

• Deductive Fault Simulation
• Concurrent Fault Simulation

Ch3-10

5
 Parallel Fault Simulation

• Simulate multiple circuits at a time:

– The inherent parallel operation of computer words to
simulate
i l t faulty
f lt circuits
i it iin parallel
ll l with
ith ffault-free
lt f
circuit
– The number of faulty circuits, or faults, can be
processed simultaneously is limited by the word
length, e.g., 32 circuits for a 32-bit computer

• Extra Cost:
– A
An event,t a value-change
l h off a single
i l ffault
lt or ffault-free
lt f
circuit leads to the computation of the entire word
– The fault-free logic simulation is repeated for each
pass

Ch3-11

Example: Parallel Fault Simulation

• Consider three faults:

(J s-a-0, B s-a-1, and F s-a-0) fault-free
• Bit-space:
p (FF
( denotes fault-free))
J/0 B/1 F/0 FF

B/1 1 1 1 1
A J/0
1
0 1x 0 0 0 1 0 0 00 1 0 1
C 0 1 0 0 E G
0
× 1
B 1 0 1 1 ×
J
D
H
0 1 0 0 1 ×
F 1 0 0 1
1 1 00 1
Q: What faults are detected?
F/0
Ch3-12

6
 Example: Parallel-Pattern Simulation

• Consider one fault F/0 and four patterns: P3,P2,P1,P0

Bit-Space: P3 P2 P1 P0

1 1 1 1
A

0 1 0 1 1 1 0 1
C 0 1 0 1 G 0 1 0 1
B D E 1 0 1 0
J
0 1 0 1 H
x
F 1 0 0 0
1 0 0 1 1 0 0 1 0 0 0 0
0 0 0 0

Ch3-13

Parallel-Pattern v.s. Parallel-Fault

Parallel-pattern
• P1, P2, P3 are patterns events
P1 • F1,
F1 F2,
F2 F3 are faults
P2
PIs F POs • Complexity
– Is proportional to the events that
P3 need to be processed
– The value-change events (upper
figure) seems to be fewer than
Parallel-fault the fault-events (lower figure)
– Hence,, p
parallel-pattern
p seems to
F1 be more efficient than parallel-
fault methods
PIs P F2 POs
F3

Ch3-14

7
 Deductive Fault Simulation

• Simulate all faulty circuits in one pass

– For each pattern, sweep the circuit from PI’s to PO’s.
– During the process, a list of faults is associated with
each line
– The list contains faults that would produce a fault
effect on this line
– The union fault list at every PO contains the detected
faults by the simulated input vector

• Major operation: fault list propagation

– Related to the gate types and values
– The size of the list may grow dynamically, leading to a
potential memory explosion problem

Ch3-15

Controlling Value of a Logic Gate

A Whenever there is a ‘0’ in the inputs, Z will be ‘0’

Z  Controlling value for NAND gate is ‘0’
B
 Non
Non-Controlling
Controlling value is ‘1’1

Gate Type Controlling Non-Controlling

Value Value
AND ‘0’ ‘1’

OR ‘1’
1 ‘0’
0

NAND ‘0’ ‘1’

NOR ‘1’ ‘0’

Ch3-16

8
 Example: Fault List Propagation

Fault-free simulation results: {A=0, B=0, C=0}

Q: What is the detected fault list at line C?
(Reasoning) To create a fault effect at line C
C, we need {A=1
{A=1, B=1}
 which means that we need a fault effect at A as well as B
 It can be achieved in faulty circuits LA · LB
 Also C/1 is a new fault to be included in the fault list of C

0
LA A 0
0 C LC
LB B

LA, LB, LC are fault list propagated to their respective lines

LA is the set of all faults not in LA

Ch3-17

Example: Fault List Propagation

LA, LB, LC are detected fault list

at their respective lines
LA A
Consider a two-input
p AND-gate:
g C LC
LB B

Non-controlling case: Case 1: A=1, B=1, C=1 at fault-free,

LC = LA + LB + {C/0}
Controlling cases: Case 2: A=1, B=0, C=0 at fault-free,
LC = LA · LB + {C/1}
Case 3: A=0, B=0, C=0 at fault-free,
LC = LA · LB + {C/1}

LA is the set of all faults not in LA

Ch3-18

9
Example: Deductive Simulation (1)

• Consider 3 faults: B/1, F/0, and J/0

A G
1

0 0
B C
J
0 x
E 1 x 1
D
1 H
1
F
x

Fault List at PI’s:

LB = {B/1}, LF = {F/0}, LA = , LC=LD = {B/1}

Ch3-19

Example: Deductive Simulation (2)

• Consider 3 faults: B/1, F/0, and J/0

A G
1
G
0 0
B C
J
0 x
E E 1 x 1
D
1 H
1
F
x

Fault Lists at G and E:

LB = {B/1}, LF = {F/0}, LA =  LC=LD = {B/1},

LG = (LA * LC) = {B/1}
LE = (LD) = {B/1}
Ch3-20

10
Example: Deductive Simulation (3)

• Consider 3 faults: B/1, F/0, and J/0

A G
1

0 0
B C
J
0 x
E 1 x 1
D
H 1 H
1
F
x

Computed Fault List at H:

LB = {B/1}, LF = {F/0}, LC=LD = {B/1},

LG = {B/1}, LE = {B/1}
LH = (LE + LF) = {B/1, F/0}
Ch3-21

Example: Deductive Simulation (4)

• Consider 3 faults: B/1, F/0, and J/0

A
1 G

0 0
B C J
0 x
E 1
J x 1
D
1 H
F
1 x
Final Fault List at the output J:
LB = {B/1}, LF = {F/0}, LC=LD = {B/1},
LG = {B/1}, LE = {B/1}
LH = {B/1, F/0},
LJ = (LG · LH) {F/0, J/0}
Ch3-22

11
 Example: Even-Driven
Deductive Fault Simulation

• When A changes from 1 to 0

A G
10

0 C
B
J
0 x 00
E x 1
D 1
1 H
1
F
x
Event-driven operation:

LB = {B/1}, LF = {F/0}, LA = 
LC=LD = {B/1}, LG = ,
LE = {B/1}, LH = {B/1,F/0}, LJ = {B/1,F/0,J/0}
Ch3-23

Concurrent Fault Simulation

• Simulate all faulty circuits in one pass:

– Each gate retains a list of fault copies, each of which
stores the status of a fault exhibiting difference from
fault-free values
• Simulation mechanism
– is similar to the conceptual fault simulation except
that only the dynamical difference w.r.t. fault-free
circuit is retained.
• Theoretically,
y,
– all faults in a circuit can be processed in one pass
• Practically,
– memory explosion problem may restrict the number of
faults that can be processed in each pass

Ch3-24

12
 Concurrent Fault Simulation

Fault-free

1 Y
0 0
0

1 As compared to deductive fault simulation

survivor 1 F100 Concurrent fault simulation can process
1
multiple patterns in a single run of simulation

Can be 0 F73
0
dropped 0

1
survivor 1 F2
1

Ch3-25

Example: Concurrent Simulation (1)

• Consider 3 faults: B/1, F/0, and J/0

A
1 G
C
B 0
J
0 x E x 1
D 1
1 H
1
F
x

LG = {10_0, B/1:11_1} LE = {0_1, B/1:1_0}

Fault A fault B/1
Free
Ch3-26

13
Example: Concurrent Simulation (2)

• Consider 3 faults: B/1, F/0, and J/0

A
1 G
C
B 0
J
0 x
E x 1
D 1
1 H
1
F
x

LG = {10_0, B/1:11_1} LE = {0_1, B/1:1_0}

LH = {11_1, B/1:01_0, F/0:10_0}

Ch3-27

Example: Concurrent Simulation (3)

• Consider 3 faults: B/1, F/0, and J/0

A
1 G
C
B
J
0 x 0
E 1 x 1
D
1 H
1
F
x

LG = {10_0, B/1:11_1} LE = {0_1, B/1:1_0}

LH = {11_1, B/1:01_0, F/0:10_0}
LJ = {01_1, B/1:10_1, F/0:00_0, J/0:01_0}
dropped Ch3-28

14
Example: Concurrent Simulation (4)

• When A changes from 1 to 0

A G
10
C
B
J
0 x 00
E x 1
D 1
1 H
1
F
x

LG = {00_0, B/1:01_0} LE = {0_1, B/1:1_0}

LH = {11_1, B/1:01_0, F/0:10_0}
LJ = {01_1, B/1:00_0, F/0:00_0, J/0:01_0}
Ch3-29

Fault List Including New Borns

A 0
0 D
0
B

1
0 A/1
0

0
0 B/1
1

0
1 D/1
0

Ch3-30

15
 Fault List Propagation

A 0 D
0 0 E
B 0 0
C 0
These 2 faults are A/1: 10_0 C/1: 01_1
not propagated
after evaluation B/1: 01_0 D/1: 10_1
D/1: 00_1 propagated E/1: 00_1

A 1
* D
0 0 E
B 0 0
C 0

*A/0: 00_0 *B/1: 10_1

*B/1: 11_1 C/1: 01_1
*D/1: 10_1 *D/1: 10_1
E/1: 00_1
Ch3-31

Outline

• Fault Simulation for Comb. Circuits

• Approximation Approach
– Critical Path Tracing
– Probabilistic Approach

• Techniques for Sequential Circuits

Ch3-32

16
 Sensitive Input and Critical Path

Sensitized ?
Non-sensitive input 1 0
Z PO
Sensitive input 0
i

i is critical if Z is sensitized to at least one PO

• Sensitive Input of a gate:

– A gate input i is sensitive if complementing the value of i
changes the value of the gate output
• Critical line
– Assume that the fault-free value of w is v in response to t
– A line w is critical w.r.t. a pattern t iff t detects the fault
w stuck-at v
• Critical paths
– Paths consisting of critical lines only
Ch3-33

Basics of Critical Path Tracing

sensitization
1 0 Path(s)
Z is critical PO
0
i
PO is sensitive to i, or i is critical

• A gate input i is critical w.r.t. a pattern t if

– (1) the gate output is critical and
– (2) i is a sensitive input to t
– Use recursion to prove that i is also critical

• In a fanout-free circuit
– the criticality of a line can be determined by
backward traversal to the sensitive gate’s inputs from
PO’s, in linear time
Ch3-34

17
 Analysis of Critical Path Tracing

• Three-step Procedure:
– Step 1: Fault-free simulation
– Step 2: Mark the sensitive inputs of each gate
– Step 3: Identification of the critical lines by backward
critical path tracing)

• Complexity is O(G)
– Where G is the gate count
– for fanout-free circuits --- very
y rare in practice
p

• Application
– Applied to fanout-free regions, while stem faults are
still simulated by parallel-pattern fault simulator.

Ch3-35

Example of Critical Path Tracing

sensitive input, critical line

A
1
G
0 C
E 0
B D 1
J
(stem) 1 H 1
1 F (fanout-free region)

Detected faults in the fanout-free region:

{J/0, H/0, F/0, E/0, D/1}
Question: is B stuck-at-1 detected ?
Ch3-36

18
 Anomaly of Critical Path Tracing

• Stem criticality is hard to infer from branches.

E.g. is B/1 detectable by the given pattern?
1
G
C 0
0 x 1
D E
B 1
H 1 J
1
F

• It turns out that B/1 is not detectable even though both C

and D are critical, because their effects cancel out each
other at gate J, (i.e., fault masking problem)
• There is also a so-called multiple path sensitization problem.

Ch3-37

Multiple Path Sensitization

A
1
G 1
1 C 1
B D
H 1 J
(stem)
1
F (fanout-free region)

Both C and D are not critical, yet B is critical and B/0

can be detected at J by multiple path sensitization.

Ch3-38

19
Parallel and Distributed Simulation

• To share the fault simulation effort

– by a number of processors either tightly
connected as in parallel computation or loosely
connected as in distributed computation.
• The speed-up
– with respect to the processor number depends on
the degree of duplicated computation, and the
communication overhead among processors.
• The distributed simulation
– on a cluster of networked workstations is
especially appealing.

Ch3-39

Distributed Simulation Techniques

• Fault Partition
– Distributes faults among many processors.
– Works relatively well for both combinational and
sequential circuits.
• Pattern Partition
– Distributes patterns among processors.
• no duplicated logic simulation
– Works well for combinational circuits.
• Circuit
C Partition
– Difficult to achieve synchronization without
incurring excessive communication overhead.

Ch3-40

20
 Distributed Fault Simulation

• Typical Speed-up versus No. of Processors

Speed-up
Ratio

# Processor

• Diminished increase of speed-up ratio with more processors

Ch3-41

Fault Grading

• Approximate fault coverage

– Can be obtained in much shorter computational
time than regular fault simulation.
– Not suitable for high fault-coverage requirement.

• Typical fault grading methods:

– Toggle test, e.g. DATAS
– Detection probability computation, e.g. STAFAN
– Fault sampling
• estimate from a selected subset of total faults
– Test set sampling
• estimate from a subset of complete test sequence

Ch3-42

21
 STAFAN

• Compute fault detection probability

from logic simulation.
– dl = detection probability of s-a-0 on l = C1(l)O(l)
– dl = detection probability of s-a-1 on l = C0(l)O(l)
0 - count 1 - count
C0(l )  , C1(l ) 
n n
sensitization - count
S (l ) 
n l
O( l )  S ( l )O( m) m

- m is the immediate successor of l

- observability can be computed backwards from POs

Ch3-43

STAFAN (cont.)

dnf 1 (1 d f )n n is the no. of vectors

d n
f the summation of
Statistical Fault Coverage   each fault’s detection
 probability

 is the set of faults of interest

• More sophisticated than toggle test

with same computation complexity

Ch3-44

22
 Outline

• Fault Simulation for Comb. Circuits

• Approximation Approach
– Toggle Counting
– Critical Path Tracing
– Probabilistic Approach

• Techniques for Sequential Circuits

Ch3-45

Fault Grading for

Functional Input Sequence
Inputs:
(1) A test application program
(2) A sequential design

Output: The fault coverage

Application: High
High-Performance
Performance CPU Designs

Major challenge: often too time-consuming

23
 Sequential Design Model

Sequential Circuits

A Comb. Comb.
B logic FFs logic
C
FFs out1
out2

clk

A
OUT1
B Combinational OUT2
C Logic
Hoffman Model

FFs
Ch3-47

Time-Frame-Expansion Model

Ex: Input Sequence (‘0’, ‘0’, ‘0’)

State Sequence (S0  S1  S2  S3)
‘0’ ‘0’ ‘0’
PO
PO’s PO
PO’s PO
PO’s

f f f

S0 S1 S2 S3

PPI PPO
Notations: PPI: pseudo primary inputs (I.e., outputs of flip-flops)
Time-frame:PPO:
1 pseudo primary outputs
2 (I.e., inputs of 3
flip-flops)

A single fault becomes multiple faults in

the time-frame-expansion model
Ch3-48

24
 Hypertrophic Faults

• A hypertrophic fault
– Is a fault that diverges from the fault-free circuit with
a large number of Xs, which usually is a stuck-at fault
occurring at a control line and thus prevents the
circuit initialization
• A small number of hypertrophic faults
– account for a large percentage of fault events and
CPU time
• These faults are sometimes dropped
– as potentially detected faults to reduce simulation
time. However, the resultant fault coverage then
becomes approximate
A potentially detected fault is
a fault detected only when the circuit is
powered on in certain states, not every state.
Ch3-49

F lt E
Fault Emulation
l ti
We can utilize FPGA to speed up the sequential fault grading

25
 FPGA-Based Emulation Process

ASIC netlist

Compilation
p
(format translation, partitioning, mapping)

Bit-Stream

i.e.,
Bit-stream downloading Programming FPGA’s

Emulation
hardware
FPGA chips

Ch3-51

Serial Fault Emulation by FPGA’s

ASIC netlist

Compilation
Bit-stream
Bit t downloading
d l di Fault list generation

join
Fault-free FPGA’s Fault list

Fault injection

Test Fault emulation Pick next fault

sequence

More faults
yes
no
Fault
END Report fault coverage coverage
Ch3-52

26
Fault Injection Should Be Efficient !

• Fault Injection
– Is to convert a fault-free FPGA implementation to a
faulty one
– If not efficient, could become the new bottleneck

• (1) Static Fault Injection

– Directly changes the configuration of the fault-free
implementation to a faulty one

• (2) Dynamic Fault Injection

– Do not change the configuration directly
– Fault inject is injected through the control of some
hardware originally built-in to the netlist

Ch3-53

Static Fault Injection

Faulty CLB

A E s-a-0
0 A
Simplify to
B B

C Z C Z

Bit t
Bit-stream off th
the entire
ti circuit
i it

Portion that needs to be modified and re-programmed

into the FPGAs through partial re-programming
Ch3-54

27
 Example: FPGA-implementation

Two faults are being considered:

A stuck-at 1
G stuck-at-0

A
B

C
CLB2
CLB1
D G s-a-0
E

Ch3-55

Dynamic Fault Injection (I)

enable Fault Activation Control (Produce 1-hot output)

x y

A
B
C
CLB2
CLB1
D
E
F

(x=1, y=0)  The above netlist behaves like A s-a-1 faulty circuit
(x=0, y=1)  The above netlist behaves like G s-a-0 faulty circuit

Ch3-56

28
 Dynamic Fault Injection (II)
(1) Conservatively map only 4-input function to a CLB,
which is originally assumed to be capable of realizing 5-input function.
(2) Extra input, I.e., x, is reserved for the control of dynamic fault injection.

a
b Faulty
c Function
d f(a,b,c,d)
1
MUX Z
0
Good
Function
g(a,b,c,d)
X

A Configurable Logic Block (CLB)

with a dynamic fault injected (activated with x=1)
Ch3-57

Overview of Dynamic Fault

Injection (II)
In the following configuration:
5 faults are injected (one for each column), but only 1 is activated

FPGA CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

faulty CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CSR FF FF FF FF FF
clock 1 0 0 0 0
Circular shift-register

Ch3-58

29
 國立清華大學電機系

EE-6250
超大型積體電路測試
VLSI Testing

Chapter 4
Automatic Test Pattern Generation

General ATPG Flow

• ATPG (Automatic Test Pattern Generation)

– Generate a set of vectors for a set of target faults
• Basic
B i flow
fl
Initialize the vector set to NULL
Repeat
Generate a new test vector
Evaluate fault coverage for the test vector
If the test vector is acceptable, then add it to the vector set
Until required fault coverage is obtained
• To accelerate the ATPG
– Random patterns are often generated first to detect easy-
to-detect faults, then a deterministic TG is performed to
generate tests for the remaining faults
ch4-2

1
 Combinational ATPG

• Test Generation (TG) Methods

– Based on Truth Table
– Based on Boolean Equation
– Based on Structural Analysis

• Milestone Structural ATPG Algorithms

– D-algorithm [Roth 1967]
– 9-Valued
9 V l d D-algorithm
D l ith [Ch
[Cha 1978]
– PODEM [Goel 1981]
– FAN [Fujiwara 1983]

ch4-3

A Test Pattern

A Fully Specified Test Pattern

(every PI is either 0 or 1)

0 stuck-at
t k t1
0 0/1
1 0/1
1 1

A Partially Specified Test Pattern

(certain PI’s
PI s could be undefined)

1 stuck-at 0
1/0
x 1/0
x x
x x
ch4-4

2
 Test Generation Methods
(From Truth Table)

Ex: How to generate tests

for the stuck
stuck-at
at 0 fault
abc f f
(fault ?
000 0 0
001 0 0
 stuck-at 0 010 0 0
a
011 0 0
b 100 0 0
101 1 1
f 110 1 0
111 1 1

ch4-5

Test Generation Methods

(Using Boolean Equation)

a  stuck-at 0
b
f = ab+ac, f= ac
f
T = the
th sett off all
ll ttests lt 
t ffor ffault
= ON_set(f⊕f c

= ON_set(f)  OFF_set(f) + OFF_set(f) ON_set(f)

= {(a,b,c) | (ab+ac)(ac)' + (ab+ac)'(ac) = 1 } Boolean equation
= {(a,b,c) | abc'=1}
= { (110) }. High complexity !!
Since it needs to compute the faulty
function for each fault.

* ON_set(f): All input combinations to which f evaluates to 1.

OFF_set(f): All input combinations to which f evaluates to 0.
Note: a function is characterized by its ON_SET

ch4-6

3
 Boolean Difference

• Physical Meaning of Boolean Difference

– For a logic function F(X)=F(x1, ..., xi, ..., xn), find all the input
combinations that make a value-change at xi also cause a value-
change
g at F.
• Logic Operation of Boolean Difference
– The Boolean difference of F(X) w.r.t. input xi is

dF(x)/dxi = Fi(0)⊕Fi(1) = Fi(0) · Fi(1)’ + Fi(0)’ · Fi(1)

Where
where Fi(0) = F(x1F i(0)
, ..., 0, =
...,F(x
xn1) ,and
…,F 0, …, x , )..., 1, ..., x ).
i(1) = F(x1n n
Fi(1) = F(x1, …, 1, …, xn)

• Illustrations of Boolean Difference

x1 x1
1 F 1 0 F 0
xi circuit xi circuit
0 0 0 1 1 1
or or
xn 1 xn 0

ch4-7

Chain Rule

A f
G( f(A,
f(A B)
B), {C
{C, D} )
B
C {A,B} and {C,D} have no
variables in common
D

f = AB dG/df = (C’ + D’)

G = f + CD df/dA = B

dG/dA = (dG/df) · (df/dA) = (C’+D’) · B

An Input vector v sensitizes a fault effect from A to G

Iff v sensitizes the effect from A to f and from f to G

ch4-8

4
 Boolean Difference (con’t)

• Boolean Difference
– With respect to an internal signal, w, Boolean
diff
difference representst the
th sett off input
i t combinations
bi ti
that sensitize a fault effect from w to the primary
output F
• Calculation
– Step 1: convert the function F into a new one G that
takes the signal w as an extra primary input
– Step 2: dF(x1, …, xn)/dw = dG (x1, …, xn, w)/dw w

x1 . x1
w Free w .
. . x
. F G
.
xn xn

ch4-9

Test Gen. By Boolean Difference

Case 1: Faults are present at PIs.

a x
b
F = ab + ac
F(a=0) = 0
c F(a=1) = (b+c)

Fault Sensitization Requirement:

dF/d = F(
dF/da F(a=0)
0) ⊕ F(a=1)
F( 1) = 0 ⊕ (b+c)
(b ) = (b
(b+c))

Test-set for a s-a-1 = {(a,b,c) | a' (b+c)=1} = {(01x), (0x1)}.

Test-set for a s-a-0 = {(a,b,c) | a (b+c)=1} = {(11x), (1x1)}.
No need to compute Fault activation Fault sensitization
The faulty function !! requirement requirement
ch4-10

5
 Test Generation By Boolean
Difference (con’t)
Case 2: Faults are present at internal lines.
a x
b h
F = ab + ac

c
G(i.e., F with h floating ) = h + ac
dG/dh = G(h=0) ⊕G(h=1) = (ac ⊕ 1) = (a’+c’)

Test-set for h s-a-1 is

{ (a,b,c)| h‘ (a'+c')=1 } = { (a,b,c)| (a'+b') (a'+c')=1 } = { (0xx), (x00) }.
Test-set for h s-a-0 is
{(a,b,c)| h (a'+c')=1} = {(110)}.

For fault activation For fault sensitization

ch4-11

Outline

• Test Generation (TG) Methods

– Based on Truth Table
– Based on Boolean Equation
– Based on Structural Analysis
– D-algorithm [Roth 1967]
– 9-Valued D-algorithm [Cha 1978]
– PODEM [Goel 1981]
– FAN [Fujiwara 1983]

ch4-12

6
 Test Generation Method
(From Circuit Structure)
• Two basic goals
– (1) Fault activation (FA)
– (2) Fault propagation (FP)
– Both of which requires Line Justification (LJ), I.e., finding
input combinations that force certain signals to their desired
values
• Notations:
– 1/0 is denoted as D, meaning that good-value is 1 while
faulty value is 0
– Similarly, 0/1 is denoted D’
– Both D and D’ are called fault effects (FE)

1 a fault activation
1/0
1 b
f
0 fault propagation
0 c
ch4-13

Common Concepts for Structural TG

• Fault activation
– Setting the faulty signal to either 0 or 1 is a Line
Justification problem
• Fault propagation
– (1) select a path to a PO  decisions
– (2) Once the path is selected  a set of line
justification (LJ) problems are to be solved
• Line Justification
– Involves decisions or implications
– Incorrect decisions: need backtracking

To justify c=1  a=1 and b=1 (implication) a

c
To justify c=0  a=0 or b=0 (decision) b

ch4-14

7
 Ex: Decision on Fault Propagation
d G2
G5 f1
a { G5, G6 }
b G1
c
G6 f2 G5 G6
G3
G4 fail success
e

– Fault activation decision tree

• G1=0  { a=1, b=1, c=1 }  { G3=0 }
– Fault propagation: through G5 or G6
– Decision through G5:
• G2=1  { d=0, a=0 }  inconsistency at a  backtrack !!
– Decision through G6:
•  G4=1  e=0  done !! The resulting test is (111x0)

D-frontiers: are the gates whose output value is x, while one or more
Inputs are D or D’. For example, initially, the D-frontier is { G5, G6 }.
ch4-15

Various Graphs

A Combinational Circuit: is usually modeled as a DAG, but not tree

Graph = (V, E)

Digraph
(directed graph)

DAG
((Directed Acyclic
y Graph)
p )

Tree

ch4-16

8
 Ex: Decisions On Line Justification

a k q=1
b q l=1 k=1
c l fail rr=1
1
d
m m=1 o=1
n r s n=1
o success
The corresponding
e p decision tree
f
h
J-frontier: is the set of gates
whose output value is known
– FA  set h to 0 (I
(I.e., 0 or 1)
1), b
butt iis nott iimplied
li d
by its input values.
– FP  e=1, f=1 (o=0) ; FP  q=1, r=1
Ex: initially, J-frontier is {q=1, r=1}
– To justify q=1  l=1 or k=1 Decision point
– Decision: l =1  c=1, d=1  m=0, n=0  r=0  inconsistency at r 
backtrack !
– Decision: k=1  a=1, b=1
– To justify r=1  m=1 or n=1 (c=0 or d=0)  Done ! (J-frontier is )
ch4-17

Branch-and-Bound Search

• Test Generation
– Is a branch-and-bound search
– Every decision point is a branching point
– If a set of decisions lead to a conflict (or bound), a
backtrack is taken to explore other decisions
– A test is found when
• (1) fault effect is propagated to a PO
• (2) all internal lines are justified
– No test is found after all p
possible decisions are tried
 Then, target fault is undetectable
– Since the search is exhaustive, it will find a test if one
exists

For a combinational circuit, an undetectable fault is also a

redundant fault  Can be used to simplify circuit.

ch4-18

9
 Implications

• Implications
– Computation
p of the values that can be uniquely
q y
determined
• Local implication: propagation of values from one
line to its immediate successors or predecessors
• Global implication: the propagation involving a
larger area of the circuit and re-convergent fanout

• Maximum Implication Principle

– Perform as many implications as possible
– It helps to either reduce the number of problems
that need decisions or to reach an inconsistency
sooner

ch4-19

Local Implications (Forward)

Before After
0 x 0 0
x x

1 x 1 1
1 1

1 0 1 0
x J-frontier={ ...,a } 0 J-frontier={ ... }
a a

D' x D' 0
D D-frontier={ ...,a } D-frontier={ ... }
a D a

ch4-20

10
 Local Implications (Backward)

Before After
x 1 1 1
x 1

x 0 0
0
1 1

x x 0
0 x J-frontier={{ ...,a
, }
x a J-frontier={ ... } a
1 1 1
x
x 1

ch4-21

Global Implications

Before After
x d x
d
x x
D x D D
x g g
x x 1
x x
e e

• Unique D-Drive Implication

– Suppose D-frontier (or D-drive) is {d, e},  g is a dominator
for both d and e, hence a unique D-drive is at g

g is called a dominator of d:
because every path from d to an PO passes through g

ch4-22

11
 Learning for Global Implication

• Static Learning AB => ~B  ~A

– Global implication derived by contraposition law
– Learn static ((I.e.,, input
p independent)
p ) signal
g implications
p
• Dynamic Learning
– Contraposition law + other signal values
– Is input pattern dependent

A D 1 D
A

B 1 0
F B F

C E C E
F=1 implies B=1 F=0 implies B=0 When A=1
Because B=0  F=0 Because {B=1, A=1}  F=1
(Static Learning) (Dynamic Learning)
ch4-23

Early Detection of Inconsistency

Aggressive implication may

help to realize that the sub-
tree below is fruitless, thus
avoiding unnecessary search
q=1

s=
1 r=1

u= v=
t=1
1 1
Appotential
f f f f sub-tree
v=
1

f f
success
sub-tree without a solution
ch4-24

12
 Ex: D-Algorithm (1/3)

• Five logic values

Try to propagate
– { 0, 1, x, D, D’ } Fault effect thru G1
h  Set d to 1
d' 0
d
d 1 Try to propagate
i D’ Fault effect thru G2
G1
 Set j,k,l,m to 1

j 1
e'0
n
e G2
1 k D
a 0 g D
b 1 D’ ≠ 1
c 1
l Conflict at k
f' 1  Backtrack !
f
m
1
ch4-25

Ex: D-Algorithm (2/3)

• Five logic values

– { 0, 1, x, D, D’ }
h Try to propagate
d' 0
d Fault effect thru G2
d  Set j,l,m to 1
1 D’
G1 i

j 1
e' 0
n
e G2
1 D
a 0 g D k
b 1 D’ (next D-frontier chosen)
c 1
l
f' 0 1
Conflict at m
 Backtrack !
f
1 m
D’ ≠ 1
ch4-26

13
 Ex: D-Algorithm (3/3)

• Five logic values Try to propagate

– { 0, 1, x, D, D’ } Fault effect thru G2
h 1  Set j,l to 1
d' 0
d
Fault propagation
d 1 and line justification
i D’
G1 are both complete
 A test is found !
j 1
e' 0
n
e G2
1 D
a 0 g D k
b 1 D’
c 1
l This is a case of
f' 0 1 multiple path sensitization !
f
1 m
D’ (next D-frontier chosen)
ch4-27

D-Algorithm: Value Computation

Decision Implication Comments

e=1 Propagate via k
a 0
a=0 Active the fault k=D’
h=1 e’=0
b=1 Unique D-drive j=1
c=1 l=1 Propagate via n
g=D m=1
d=1 Propagate via i n=D
i=D’ f’=0
d’=0 f=1
j=1 Propagate via n m=D’ Contradiction
k=1 f=1 Propagate via m
l=1 m=D’
m=1 f’=0
n=D l=1
e’=0 n=D
e=1
k=D’ Contradiction
ch4-28

14
 Decision Tree on D-Frontier

• The decision tree below

– Node  D-frontier
– Branch  Decision Taken
– A Depth-First-Search (DFS) strategy is often used

h 1
d' 0 {i,k,m}
d 1
i D’ i
G1

j 1 {k,m,n}
e' 0
n
e G2 n k
1 k
a 0 g D D
b 1 D’
c 1 F {m,n}
l n m
f' 0 1
f
1 m F S
D’
ch4-29

9-Value D-Algorithm

• Logic values (fault-free / faulty)

– {0/0
{0/0, 0/1,
0/1 0/u,
0/u 1/0,
1/0 1/1,
1/1 1/u,
1/u u/0,
u/0 u/1,
u/1 u/u},
u/u}
– where 0/u={0,D'}, 1/u={D,1}, u/0={0,D}, u/1={D',1},
u/u={0,1,D,D'}.
• Advantage:
– Automatically considers multiple-path
sensitization, thus reducing the amount of search
i D-algorithm
in D l ith
– The speed-up is NOT very significant in practice
because most faults are detected through single-
path sensitization

ch4-30

15
 Example: 9-Value D-Algorithm
0/1
h 1/u  1/1
d' Decision Tree
0/u
d D’ ((=0/1)
D 0/1)
1/u
i
D’(0/1)
G1 {i, k, m}
1/u j i
e' u/1
u/0 n {k, m, n}
e G2
u/1 D(=1/0)
a 0/1 g k n
u/1 D ((1/0))
b u/1
c u/1
success
1/u
l D’ or 1
f' u/1
u/0
f u/1 No-backtrack !
m
u/1
ch4-31

Final Step of 9-Value D-Algorithm

• To derive the test vector

• A = (0/1)  0 (take the fault-free one)
• B = (1/u)  1
• C = (1/u)  1
• D = (u/1)  1
• E = (u/1)  1
• F = (u/1)  1

• The final vector

– (A,B,C,D,E,F) = (0, 1, 1, 1, 1, 1)

ch4-32

16
 Outline

• Test Generation (TG) Methods

– Based on Truth Table
– Based on Boolean Equation
– Based on Structural Analysis
– D-algorithm [Roth 1967]
– 9-Valued D-algorithm [Cha 1978]
– PODEM [Goel 1981]
– FAN [Fujiwara 1983]

ch4-33

PODEM: Path-Oriented DEcision

Making

• Fault Activation (FA) and Propagation (FP)

– lead to sets of Line Justification (LJ) problems. The LJ problems
can be solved via value assignments.

• In D-algorithm
– TG is done through indirect signal assignment for FA, FP, and LJ,
that eventually maps into assignments at PI’s
– The decision points are at internal lines
– The worst-case number of backtracks is exponential in terms of
the number of decision points (e.g., at least 2k for k decision
nodes)

• In PODEM
– The test generation is done through a sequence of direct
assignments at PI’s
– Decision points are at PIs, thus the number of backtracking might
be fewer

ch4-34

17
 Search Space of PODEM

• Complete Search Space

– A binary tree with 2n leaf nodes, where n is the number of PI’s

• Fast Test Generation

– Need to find a path leading to a SUCCESS terminal quickly

a
0 1

b b
0 1 0 1

c c c c
0 1 0 1 0 1 0 1

d d d d d d d d

F F F S F S F F
ch4-35

Objective() and Backtrace()

• PODEM
– Also aims at establishing a sensitization path based on fault
activation and propagation like D-algorithm
– Instead of justifying the signal values required for sensitizing the
selected path, objectives are setup to
guide the decision process at PI’s

• Objective
– is a signal-value pair (w, vw)

• Backtrace
– B
Backtrace
kt maps a ddesired
i d objective
bj ti iinto
t a PI assignment
i t that
th t is
i
likely to contribute to the achievement of the objective
– Is a process that traverses the circuit back from the objective
signal to PI’s
– The result is a PI signal-value pair (x, vx) 往輸入端追蹤
– No signal value is actually assigned during backtrace !

ch4-36

18
 Objective Routine

• Objective Routine Involves

– The selection of a D-frontier, G
– The
Th selection
l ti off an unspecified
ifi d input
i t gate
t off G

Objective() {
/* The target fault is w s-a-v */
/* Let variable obj be a signal-value pair */
if (the value of w is x) obj = ( w, v’ ); fault activation
else {
select a ggate (G)
( ) from the D-frontier; fault p
propagation
p g
select an input (j) of G with value x;
c = controlling value of G;
obj = (j, c’);
}
return (obj);
}
ch4-37

後追蹤 Backtrace Routine

• Backtrace Routine
– Involves finding an all-x path from objective site to a
PI,, I.e.,, every
y signal
g in this path
p has value x

Backtrace(w, vw) {
/* Maps objective into a PI assignment */
G = w; /* objective node */
v = vw; /* objective value */
while (G is a gate output) { /* not reached PI yet */
inv = inversion of G;
select
l t an input
i t (j) off G with
ith value
l x;
G = j; /* new objective node */
v = v⊕inv; /* new objective value */
}
/* G is a PI */ return (G, v);
}

ch4-38

19
 Example: Backtrace

Objective to achieve: (F, 1)

PI assignments:
(1) A = 0  fail
(2) B = 1  succeed

Dx F 0A C D1 F
xA C =>
xB x x xB 1 x
Ex Ex
The first time of backtracing

D1 F 0A C D1 F
0A C =>
xB 1 x 1B 1 1
Ex E0
The second time of backtracing
ch4-39

PI Assignment in PODEM

Assume that: PI
PI’s:
s: { a, b, c, d } a
Current Assignments: { a=0 } 0
Decision: b=0  objective fails
Reverse decision: b=1
Decision: c=0  objective fails 0
b
1
Reverse decision: c=1
Decision: d=0
failure c
0 1

Failure means fault effect cannot be failure d

propagated to any PO under current
PI assignments 0
S

ch4-40

20
 Example: PODEM (1/3)

h 1 Select D-frontier G2 and

d' 0 set objective to (k,1)
 e = 0 by backtrace
d 1
i D’  Break the sensitization
G1 across G2
 Backtrack !
j 0
e' 1
n
e G2
0 k 1
a 0 g D
b 1 1
c 1
l
f'
f
m

ch4-41

Example: PODEM (2/3)

h 1 Select D-frontier G3 and

d' 0 set objective to (e,1)
 No backtrace is needed
d 1
i D’  Success at G3
G1

j 1
e' 0
n
e G2
1 k
a 0 g D G3
b 1
c 1
l
f'
f
m
G4

ch4-42

21
 Example: PODEM (3/3)

h 1 Select D-frontier G4 and

d' 0 set objective to (f,1)
 No backtrace is needed
d 1
i D’  Success at G4 and G2
G1  D appears at one PO
 A test is found !!
j 1
e' 0
n
e G2
1 k D
a 0 g D G3
b 1 D’
c 1
l1
f' 0
f
1 m
G4
D’

ch4-43

PODEM: Value Computation

Objective PI assignment Implications D-frontier Comments
a=0 a=0 h=1 g
b=1 b=1 g
c=1 c=1 g=D ikm
i,k,m
d=1 d=1 d’=0
i=D’ k,m,n
k=1 e=0 e’=1 Assignments need to be
j=0 reversed during backtracking
k=1
n=1 m no solutions !  backtrack
e=1 e’=0 reverse PI assignment
j=1 h 1
d'
0
d
k=D’ m,n 1
i
D’
l=1 f=1 f’=0 j 1
e' 0
l=1 e
n
1 k
a 0 g D D
m=D’ b
c
1
1
D’

n=D f' 0 l
1
f
1 m
D’ ch4-44

22
 Decision Tree in PODEM

0 a

b
1
c

1
d
1
e
0 1

fail f

success

• Decision node: the PI selected through backtrace for value assignment

• Branch: the value assignment to the selected PI

ch4-45

Terminating Conditions

• D-algorithm
– Success:
(1) Fault
F lt effect
ff t att an output
t t (D
(D-frontier
f ti may nott b
be empty)
t )
(2) J-frontier is empty
– Failure:
(1) D-frontier is empty (all possible paths are false)
(2) J-frontier is not empty

• PODEM
– Success:
• Fault effect seen at an output
– Failure:
• Every PI assignment leads to failure, in which D-frontier
is empty while fault has been activated

ch4-46

23
 PODEM: Recursive Algorithm

PODEM () /* using depth-first-search */

begin
If(error at PO) return(SUCCESS);
If(test not possible) return(FAILURE);
(k, vk) = Objective(); /* choose a line to be justified */
(j, vj) = Backtrace(k, vk); /* choose the PI to be assigned */
Imply (j, vj); /* make a decision */
If ( PODEM()==SUCCESS ) return (SUCCESS);
Imply (j, vj’); /* reverse decision */
If ( PODEM()==SUCCESS ) return(SUCCESS);
Imply (j, x);
What PI to assign ?
Return (FAILURE);

end j=vj j=vj’

Recursive-call Recursive-call
If necessary
ch4-47

Overview of PODEM

• PODEM
– examines all possible input patterns implicitly but
exhaustively (branch-and-bound) for finding a test
– It is complete like D-algorithm (I.e., will find one if a
test exists)

• Other Key Features

– No J-frontier, since there are no values that require
justification
– No consistency check, as conflicts can never occur
– No backward implication, because values are
propagated only forward
– Backtracking is implicitly done by simulation rather
than by an explicit and time-consuming save/restore
process
– Experimental results show that PODEM is generally
faster than the D-algorithm

ch4-48

24
 The Selection Strategy in PODEM

• In Objective() and Backtrace()

– Selections are done arbitrarily in original PODEM
– The algorithm will be more efficient if certain
guidance used in the selections of objective node
and backtrace path
• Selection Principle
– Principle 1: Among several unsolved problems
•  Attack the hardest one 1
• Ex: to justify a ‘1’ at an AND-gate output
– Principle 2: Among several solutions for solving a
problem
•  Try the easiest one 1
• Ex: to justify a ‘1’ at OR-gate output

ch4-49

Controllability As Guidance

• Controllability of a signal w
– CY1(w): the probability that line w has value 1.
– CY0(w): the probability that line w has value 0.
– Example:
• f = ab
• Assume CY1(a)=CY0(a)=CY1(b)=CY0(b)=0.5
 CY1(f)=CY1(a)xCY1(b)=0.25,
 CY0(f)=CY0(a)+CY0(b)-CY0(a)xCY0(b)=0.75
• Example of Smart Backtracing
– Objective (c, 1)  choose path ca for backtracing
– Objective
Obj ti ((c, 0)  choose
h path
th ca
 ffor b
backtracing
kt i

CY1(a) = 0.33
CY0(a) = 0.67 a
c
CY1(b) = 0.5 b
CY0(b) = 0.5
ch4-50

25
 Testability Analysis

• Applications
– To give an early warning about the testing problems
that lie ahead
– To provide guidance in ATPG
• Complexity
– Should be simpler than ATPG and fault simulation, I.e.,
need to be linear or almost linear in terms of circuit
size
• Topology analysis
– Only the structure of the circuit is analyzed
– No test vectors are involved
– Only approximate, reconvergent fanouts cause
inaccuracy

ch4-51

SCOAP
(Sandia Controllability/Observability Analysis Program)

• Computes six numbers for each node N

– CC0(N) and CC1(N)
• Combinational 0 and 1 controllability of a node N
– SC0(N) and SC1(N)
• Sequential 0 and 1 controllability of a node N
– CO(N)
• Combinational observability
y
– SO(N)
• Sequential observability

值越大代表越困難
ch4-52

26
 General Characteristic of
Controllability and Observability

Controllability calculation: sweeping the circuit from PI to PO

Observability calculation: sweeping the circuit from PO to PI

Boundary conditions:
(1) For PI’s: CC0 = CC1 = 1 and SC0 = SC1 = 0
(2) For PO’s: CO = SO = 0

ch4-53

Controllability Measures

– CC0(N) and CC1(N)

• The number of combinational nodes that must be
assigned values to justify a 0 or 1 at node N

– SC0(N) and SC1(N)

• The number of sequential nodes that must be assigned
values to justify a 0 or 1 at node N

x1
Y
x2

CC0(Y) = min [CC0(x1) , CC0(x2) ] + 1

CC1(Y) = CC1(x1) + CC1(x2) + 1
SC0(Y) = min [SC0(x1) , SC0(x2) ]
SC1(Y) = SC1(x1) + SC1(x2)
ch4-54

27
Controllability Measure (con’t)

– CC0(N) and CC1(N)

• The number of combinational nodes that must be
assigned values to justify a 0 or 1 at node N

– SC0(N) and SC1(N)

• The number of sequential nodes that must be assigned
values to justify a 0 or 1 at node N

x1
x2 Y
x3

CC0(Y) = CC0(x1) + CC0(x2) + CC0(x3) + 1

CC1(Y) = min [ CC1(x1), CC1(x2), CC1(x3) ] + 1
SC0(Y) = SC0(x1) + SC0(x2) + SC0(x3)
SC1(Y) = min [ SC1(x1) , SC1(x2) , SC1(x3) ]
ch4-55

Observability Measure

– CO(N) and SO(N)

• The observability of a node N is a function of the
output observability and of the cost of holding all
other inputs at non-controlling values

Example: X1 observable: (Y observable) + (side-inputs 配合)

x1
x2 Y
x3

CO(x1) = CO(Y) + CC0(x2) + CC0(x3) + 1

SO(x1) = SO(Y) + SC0(x2) + SC0(x3)

ch4-56

28
 PODEM: Example 2 (1/3)

Initial objective=(G5,1).
G5 is an AND gate  Choose the hardest-1
 Current objective=(G1,1).
G1 iis an AND gatet  Choose
Ch the
th hardest-1
h d t1
 Arbitrarily, Current objective=(A,1). A is a PI  Implication  G3=0.

1A CY1=0.25 1/0
G1 G5
B
CY1=0.656
CY1 0.656 G7
C G2
G4 G6
0
G3

ch4-57

PODEM: Example 2 (2/3)

The initial objective satisfied? No!  Current objective=(G5,1).

G5 is an AND g gate  Choose the hardest-1  Current objective=(G1,1).
j ( )
G1 is an AND gate  Choose the hardest-1
 Arbitrarily, Current objective=(B,1). B is a PI  Implication  G1=1, G6=0.

1 1 CY1=0.25 1/0
A G1
1 B G5
CY1=0 656
CY1=0.656 G7
C G2 0

G4 G6
0
0
G3
ch4-58

29
 PODEM: Example 2 (3/3)

The initial objective satisfied? No!  Current objective=(G5,1).

The value of G1 is known  Current objective=(G4,0).
The value of G3 is known  Current objective=(G2,0).
A, B is known  Current objective=(C,0).
C is a PI  Implication  G2=0, G4=0, G5=D, G7=D.

1 A 1 CY1=0.25 1/0=D
G1 1
1 B G5
0 CY1=0.656 G7 D
0 C G2
G4 G6
0
0 0
G3
No backtracking !!

ch4-59

If The Backtracing Is Not Guided (1/3)

Initial objective=(G5,1).
Choose path G5-G4-G2-A  A=0.
Implication for AA=0
0  G1
G1=0,
0, G5
G5=0
0  Backtracking to A
A=1.
1.
Implication for A=1  G3=0.

1 A 1/0
G1
B G5
G7
C G2
G4 G6

G3
0

ch4-60

30
If The Backtracing Is Not Guided (2/3)

The initial objective satisfied? No!  Current objective=(G5,1).

Choose path G5 G5-G4-G2-B
G4 G2 B  B B=0.
0.
Implication for B=0  G1=0, G5=0  Backtracking to B=1.
Implication for B=1  G1=1, G6=0.

1
1 A 1/0
1
G1 G5
B
G7
C G2
G4 G6
0

G3
0

ch4-61

If The Backtracing Is Not Guided (3/3)

The initial objective satisfied? No!  Current objective=(G5,1).

Choose p path G5-G4-G2-C  C=0.
Implication for C=0  G2=0, G4=0, G5=D, G7=D.

1
1A 1/0=D
1B
G1 A
G5 0 1
0 1
G7 D F B
0C G2 0 1
G4 G6 F C
0
0 0
G3 S
0

Two times of backtracking !!

ch4-62

31
 ECAT Circuit: PODEM (1/3)

Fault activation
g 0->D'
0 a
x b
c h m
l p
d
e i
f
j
n
k

ch4-63

ECAT Circuit: PODEM (2/3)

g 0->D'
0 a
x b
1 h 1 m
c l
0 d p
1
e i side-input
f requirement

j 0
n
k

ch4-64

32
 ECAT Circuit: PODEM (3/3)

0->D'
0 a g
x b
1 c h 1 m
l p D
0 d D
0 1
e i 0
0 f objective

j 0 0
n
k 1

No backtracking !!

ch4-65

Outline

• Test Generation (TG) Methods

– Based on Truth Table
– Based on Boolean Equation
– Based on Structural Analysis
– D-algorithm [Roth 1967]
– 9-Valued D-algorithm [Cha 1978]
– PODEM [Goel 1981]
– FAN [Fujiwara 1983]

ch4-66

33
 FAN (Fanout Oriented) Algorithm

• FAN
– Introduces two major extensions to PODEM’s
backtracing algorithm

• 1st extension
– Rather than stopping at PI’s, backtracing in FAN
may stop at an internal lines

• 2nd extension
– FAN uses multiple backtrace procedure, which
attempts to satisfy a set of objectives
simultaneously

ch4-67

Headlines and Bound Lines

• Bound line
– A line reachable from at least one stem
• Free line
– A line that is NOT bound line
• Head line
– A free line that directly feeds a bound line

E H
F M
Head lines K
A Bound lines
B J
L
C
ch4-68

34
 Decision Tree (PODEM v.s. FAN)

E H
F M

Head lines K
Assume that:
A Bound lines Objective is (J, 0)
B J
L
C

J is a head line
A  Backtrace stops at J
1 All makes J = 0
 Avoid unnecessary search
B
0 1

S C
0 1 J
0 1
S
S

PODEM FAN
ch4-69

Why Stops at Head Lines ?

• Head lines are mutually independent

– Hence, for each given value combination at head
lines, there always exists an input combination
to realize it.

• FAN has two-steps

– Step 1: PODEM using headlines as pseudo-PI’s
– Step 2: Generate real input pattern to realize the
value combination at head lines.

ch4-70

35
 Why Multiple Backtrace ?

• Drawback of Single Backtrace

– A PI assignment satisfying one objective may preclude
achieving another one,
one and this leads to backtracking

• Multiple Backtrace
– Starts from a set of objectives (Current_objectives)
– Maps these multiple objectives into a head-line
assignment k=vk that is likely to
• Contribute to the achievement of a subset of the objectives
• Or show that some subset of the original objectives cannot
be simultaneously achieved

0
Multiple objectives 0
May have conflicting
1
Requirements at a stem 1
ch4-71

Example: Multiple Backtrace

A1 1
conflicting stem I1
A A2 0 E1
E 1 G 0
1 E2
B 1 H 1 0
Consistent stem J
C 1
Current_objectives Processed entry Stem_objectives Head_objectives

(I,1), (J,0) (I,1)

(J,0), (G,0) (J,0)
(G,0), (H,1) (G,0)
(H,1), (A1,1), (E1,1) (H,1)
(A1,1), (E1,1), (E2,1), (C,1) (A1,1) A
(E1,1), (E2,1), (C,1) (E1,1) A,E
(E2,1), (C,1) (E2,1) A,E
(C,1) (C,1) A,E C
Empty  restart from (E,1) A C
(E,1) (E,1) A C
(A2,0) (A2,0) A C
empty A C ch4-72

36
 Multiple Backtrace Algorithm

Mbacktrace (Current_objectives) {
while (Current_objectives ≠ ) {
remove one entry (k, vk) from Current_objectives;
switch (type of entry) {
1. HEAD_LINE: add (k, vk) to Head_objectives;
2. FANOUT_BRANCH:
j = stem(k);
increment no. of requests at j for vk; /* count 0s and 1s */
add j to Stem_objectives;
3. OTHERS:
inv = inversion of k; c = controlling value of k;
select an input (j) of k with value x;
if ((vk⊕ inv) == c) add(j, c) to Current_objectives;
else { for every input (j) of k with value x
add(j, c’) to Current_objectives; }
}
} TO BE CONTINUED …
ch4-73

Multiple Backtrace (con’t)

Mbacktrace (Current_objectives) {
while (Current_objectives ≠ ) {body in previous page}
if(Stem objectives≠ ) {
if(Stem_objectives≠
remove the highest-level stem (k) from Stem_Objectives;
vk = most requested value of k;
/* recursive call here */
add (k, vk) to Current_objectives;
return (Mbacktrace(Current_objectives);
}
else { remove one objective (k, vk) from Head_objectives;
return (k, vk)
}
}

ch4-74

37
 References
[1] Sellers et al., "Analyzing errors with the Boolean difference", IEEE Trans. Computers,
pp. 676-683, 1968.
[2] J. P. Roth, "Diagnosis of Automata Failures: A Calculus and a Method", IBM Journal
of Research and Development, pp. 278-291, July, 1966.
[2'] J. P. Roth et al., "Programmed Algorithms to Compute Tests to Detect and
Distinguish Between Failures in Logic Circuits", IEEE Trans. Electronic Computers,
pp. 567-579, Oct. 1967.
[3] C. W. Cha et al, "9-V Algorithm for Test Pattern Generation of Combinational Digital
Circuits", IEEE TC, pp. 193-200, March, 1978.
[4] P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational
Logic Circuits", IEEE Trans. Computers, pp. 215-222, March, 1981.
[5] H. Fujiwara and T. Shimono, "On the Acceleration of Test Generation Algorithms",
IEEE TC, pp. 1137-1144, Dec. 1983.
[6] M. H. Schulz et al., "SOCRATES: A Highly Efficient Automatic Test Pattern Generation
System", IEEE Trans. on CAD, pp. 126-137, 1988.
[6'] M. H. Schulz and E. Auth, "Improved Deterministic Test Pattern Generation with
Applications to Redundancy Identification", IEEE Trans CAD, pp. 811-816, 1989.

ch4-75

38
 國立清華大學電機系

EE-6250
超大型積體電路測試
VLSI Testing

Chapter 5
Design For Testability
& Scan Test

Outline

• Introduction
– Why DFT?
– What is DFT?

• Ad-Hoc Approaches
• Full Scan
• Partial Scan

ch5-2

1
 Why DFT ?

• Direct Testing is Way Too Difficult !

– Large number of FFs
– Embedded memory blocks
– Embedded analog blocks

• Design For Testability is inevitable

• Like death and tax

ch5-3

Design For Testability

• Definition
– Design For Testability (DFT) refers to those design
techniques that make test generation and testing
cost-effective
• DFT Methods
– Ad-hoc methods
– Scan, full and partial
– Built-In Self-Test (BIST)
– Boundary scan
• Cost of DFT
– Pin count, area, performance, design-time, test-time

ch5-4

2
 Why DFT Isn’t Universally Used
Previously?

– Short-sighted view of management

– Time-to-market pressure
p ss
– Life-cycle cost ignored by development
management/contractors/buyers
– Area/functionality/performance myths
– Lack of knowledge by design engineers
– Testing is someone else’s
else s problem
– Lack of tools to support DFT until recently

We don’t’ have to worry about this management barrier any more

 Most design teams now have DfT people

ch5-5

Important Factors

• Controllability
– Measure the ease of controlling
g a line

• Observability
– Measure the ease of observing a line at PO

• Predictability
– Measure the ease of predicting output values

• DFT deals with ways of improving

– Controllability
– Observability
– Predictability

ch5-6

3
 Outline

• Introduction
• Ad-Hoc Approaches
– Test Points
– Design Rules

• Full Scan
• Partial Scan

ch5-7

Ad-Hoc Design For Testability

• Design Guidelines
– Avoid redundancy
– Avoid asynchronous logic
– Avoid clock gating (e.g., ripple counter)
– Avoid large fan-in
– Consider tester requirements (tri-stating, etc.)

• Disadvantages
– High fault coverage not guaranteed
– Manual test generation
– Design iterations required

ch5-8

4
 Some Ad-Hoc DFT Techniques

• Test Points
• Initialization
input
• Monostable multivibrators Delay
element
output

– One-shot circuit
• Oscillators and clocks One-shot
• Counters / Shift-Registers
– Add control points to long counters input
p
• Partition large circuits
output
• Logical redundancy
• Break global feedback paths

ch5-9

On-Line Self-Test & Fault Tolerance

By Redundancy

• Information Redundancy
– Outputs = (information-bits) + (check-bits)
– Information bits are the original normal outputs
– Check bits always maintains a specific pre-defined
logical or mathematical relationship with the
corresponding information bits
– Any time, if the information-bits and check-bits violate
the pre-defined relationship, then it indicates an error

• Hardware
Hard are Red
Redundancy
ndanc
– Use extra hardware (e.g., duplicate or triplicate the
system) so that the fault within one module will be
masked (I.e., the faulty effect never observed at the
final output)

ch5-10

5
 Module Level Redundancy

• Triple Module Redundancy (TMR)

– majority voting on three identical modules’
outputs help mask out faults that occur in a
single module

Module 1

Majority verdict 0
0
Module voter

0
Module

ch5-11

Test Point Insertion

• Employ test points to enhance
– Controllability
– Observability
• CP: Control Points
– Primary inputs used to enhance controllability
• OP: Observability Points
– Primary outputs used to enhance observability
0 (extra PI) (extra PO)
OP
Add 0-CP

Add OP
1 (extra PI)
Add 1-CP

ch5-12

6
 0/1 Injection Circuitry

• Normal operation
When CP_enable = 0
• Inject
j 0
– Set CP_enable = 1 and CP = 0
• Inject 1
– Set CP_enable = 1 and CP = 1

0 w
C1 MUX C2
1

CP
CP_enable
Inserted circuit for controlling line w
ch5-13

Single I/O Port for Multiple Test

Points

• Constraints of using test points

– A large demand on I/O pins
– Thi
This constraint
t i t can b
be somewhat
h t relieved
li dbby
using MUX & DEMUX at the cost of increasing
the test time
dispatcher
CP1 OP1
CP2 OP2
Input pin CP3 OP3 output pin
For CP DEMUX MUX
For OP
CPN OPN

C1 C2 C3 Cn C1 C2 C3 Cn

N= 2n N= 2n
(demultiplexing control points) (multiplexing observation points)
ch5-14

7
 Sharing Between Test Points &
Normal I/O

• Advantage: Even fewer I/O pins for Test Points

• Overhead: Extra MUX delay for normal I/O

Normal Normal
Functional functional
inputs outputs
Input n n
pins n 1-to-2 n 2-to-1 Output
n
DEMUX’s MUX’s n pins
p
n n n
CP’s Observation
points
SELECT SELECT
PIN PIN

ch5-15

Control Point Selection

• Impact
– The controllability
y of the fanout-cone of the added
point is improved

• Common selections
– Control, address, and data buses
– Enable / Hold inputs
– Enable and read/write inputs to memory
– Clock and set/clear signals of flip-flops
– Data select inputs to multiplexers and
demultiplexers

ch5-16

8
 Example: Use CP to Fix DFT Rule
Violation
• DFT rule violations
– The set/clear signal of a flip-flop is generated by other
logic, instead of directly controlled by an input pin
– Gated clock signals

• Violation Fix
– Add a control point to the set/clear signal or clock signals

D D Q
Q
Violation
CK fix CK clear
clear

logic
logic

CLEAR
ch5-17

Example: Fixing Gated Clock

• Gated Clocks
– Advantage: power dissipation of a logic design can thus
reduced
– Drawback: the design’s testability is also reduced

• Testability Fix

D Q
D Q
CK
CK Violation
fix
MUX

Gated
CK CK_enable
CK_enable
CP_enable
CK
ch5-18

9
 Example: Fixing Tri-State Bus
Contention

• Bus Contention
– A stuck-at-fault at the tri-state enable line may cause
b contention
bus t ti – multiple
lti l active
ti drivers
di are connected
t d
to the bus simultaneously

• Fix
– Add CPs to turn off tri-state devices during testing
(A Bus Contention Scenario in the presence of a fault)
Enable line stuck-at-1
stuck at 1 x
0 0 Unpredictable voltage on bus may
cause a fault to go unnoticed
Enable line active
1 1

ch5-19

Example: Partitioning Counters

• Consider a 16-bit ripple-counter

– Could take up to 216 = 65536 cycles to test
– After being partitioned into two 8-bit counters below, it
can be tested with just 2x28 = 512 cycles

Trigger clock
Q0 For 2nd 8-bit start Q8
start Q9
Q1 counter
Q2 Q10
Q3 Q11
8-bit counters 8 bit co
8-bit counters
nters Q12
Q4
Q5 MUX Q13
Q6 CK_for_Q8 Q14
Q15
Q7
CP_enable
CK
ch5-20

10
 Observation Point Selection

• Impact
– The observabilityy of the fanin-cone ((or transitive
fanins) of the added OP is improved

• Common choice
– Stem lines having a large number of fanouts
– Global feedback paths
– Redundant signal lines
– Output
O t t off llogic
i ddevices
i h
having
i many iinputs
t
• MUX, XOR trees
– Output from state devices
– Address, control and data buses
(常為電路區塊間之介面訊號)

ch5-21

Problems of CP & OP

• Large number of I/O pins

– Add MUXes to reduce the number of I/O pins
– Serially shift CP values by shift-registers

• Larger test time

X Z

g
Shift-register R1 X’
X Z’
Z Shift-register R2

control Observe
ch5-22

11
 Outline

• Introduction
• Ad-Hoc Approaches
• Full Scan
– The Concept
– Scan Cell Design
– Random Access Scan

• Partial Scan

ch5-23

What Is Scan ?

• Objective
– To provide controllability and observability at internal
state variables for testing
g

• Method
– Add test mode control signal(s) to circuit
– Connect flip-flops to form shift registers in test mode
– Make inputs/outputs of the flip-flops in the shift register
controllable and observable

• Types
– Internal scan
• Full scan, Partial scan, Random access
– Boundary scan
ch5-24

12
 The Scan Concept

Combinational
Logic
Mode Switch
(normal or test)

Scan In
FF

FF

FF
Scan Out
ch5-25

A Logic Design Before Scan Insertion

Combinational Logic

input output
pins pins

D Q D D Q
Q

clock

Sequential ATPG is extremely difficult:

due to the lack of controllability and observability at flip-flops.

ch5-26

13
 Example: A 3-stage Counter

Combinational Logic

input q1 output
p
q2  g stuck-at-0
pins q3 pins

q1 q3
q2
D D D
Q Q Q
1 1 1

clock

It takes 8 clock cycles to set the flip-flops to be (1, 1, 1),

for detecting the g stuck-at-0 fault
(220 clock cycles for a 20-stage counter !)

ch5-27

A Logic Design After Scan Insertion

Combinational Logic
input
put q1
q2 output
 g stuck-at-0
pins q3 pins
q1 q3
q2

scan-output
MUX

MUX

D D
scan-input
MUX

Q Q D Q
1 1 1 (SO)
(SI)
scan-enable
clock

Scan Chain provides an easy access to flip-flops

Pattern Generation is much easier !!
Note: Scan Enable (SE), not shown here, controls every MUX.
ch5-28

14
 Procedure of Applying Test Patterns

• Notation
PI’s PO’s
– Test vectors T = < tiI, tiF > i= 1, 2, …
Comb.
– Output Response R = < riO, riF > i= 1,
1 2,
2 …
portion
PPI’s PPO’s
• Test Application
– (1) i = 1;
– (2) Scan-in t1F /* scan-in the first state vector for PPI’s */
– (3) Apply t iI /* apply current input vector at PI’s */
– (4) Observe riO //* observe current output response at PO’s
PO s *//
– (5) Capture PPOs to FFs as riF /* capture the response at PPO’s to FFs */
• (Set to ‘Normal Mode’ by raising SE to ‘1’ for one clock cycle)
– (6) Scan-out riF while scanning-in ti+1F /* overlap scan-in and scan-out */
– (7) i = i+1; Goto step (3)

ch5-29

Testing Scan Chain ?

• Common practice
– Scan chain is often first tested before testing the core logic
by a so-called flush test - which pumps random vectors in
and out of the scan chain

• Procedure (flush test of scan chain)

– (1) i = 0;
– (2) Scan-in 1st random vector to flip-flops
– (3) Scan-out (i)th random vector while scanning-in (i+1)th
vector for flip-flops.
• The (i)th scan-out vector should be identical to (i)th vector
scanned in earlier, otherwise scan-chain is mal-functioning
– (4) If necessary i = i+1, goto step (3)
ch5-30

15
 MUX-Scan Flip-Flop

– Only D-type master-slave flip-flops are used

– All flip-flop clocks controlled from primary inputs
• No g
gated clock allowed
– Clocks must not feed data inputs of flip-flops
– Most popularly supported in standard cell libraries

D
SC (normal / test)

Normal
Master-
Slave
SI (scan input)
Flip-flop

CLK

ch5-31

Two-Port Dual-Clock Scan FF

• Separate normal clock from the clock used for

scanning
– D: normal input data
– CK1: normal clock
– SI: scan input
– CK2: scan clock
Q1
master
D latch
CK1
D Q D Q Q2
CK2
SI CK CK

slave
latch

ch5-32

16
 Race-Free Scan FF

• Use two-phase clocking

– CK1 and CK2 are two-phase non-overlapping
clocks which insure race-free operation

CK1
CK2

Q1
D

D Q D Q Q2
SC
SI CK CK

CK1
CK2
ch5-33

LSSD flip-flop (1977 IBM)

• LSSD: Level Sensitive Scan Design

– Less performance degradation than MUX-scan FF
• Clocking
– Normal operation: non-overlapping CK1=1  CK3=1
– Scan operation: non-overlapping CK2=1  CK3=1

D Q1 Q2

CK1
C

SD
想辦法將 MUX
融入FF設計中，
以降低 Scan 對速度的負面影響
CK2
CK3
ch5-34

17
 Symbol of LSSD FF

Latch 1

D 1D Q Q1 (normal level-sensitive
latch output)
SI 2D
C CK1
A CK2

Latch 2

D Q SO

B CK

ch5-35

Scan Rule Violation Example

Q1 Q2
D1 D2
D D
Flip Flip
Fl
Flop Fl
Flop

Clock Rule violation:

Flip-flops cannot form a shift-register

A workaround

D1 Q2
D D
Flip Flip
Flop D2 Flop

Clock
All FFs are triggered by the same clock edge
Set and reset signals are not controlled by any internal signals
ch5-36

18
 Some Problems With Full Scan

Major Commercial Test Tool Companies

Synopsys
• Problems Mentor-Graphics
SynTest (華騰科技)
– Area overhead Cadence

– Possible performance degradation

– High test application time
– Power dissipation

• Features of Commercial Tools

– Scan-rule violation check (e.g., DFT rule check)
– Scan insertion (convert a FF to its scan version)
– ATPG (both combinational and sequential)
– Scan chain reordering after layout

ch5-37

Performance Overhead

• The increase of delay along the

normal data p
paths include:
– Extra gate delay due to the multiplexer
– Extra delay due to the capacitive loading of the
scan-wiring at each flip-flop’s output

• Timing-driven partial scan

– Try to avoid scan flip-flops that belong to the
timing critical paths
– The flip-flop selection algorithm for partial scan
can take this into consideration to reduce the
timing impact of scan to the design

ch5-38

19
 Scan-Chain Reordering

– Scan-chain order is often decided at gate-level

without knowing the physical locations of the cells
– Scan-chain consumes a lot of routing resources, and
could be minimized by re-ordering the flip-flops in the
chain after layout is known

3 2

Scan-In Scan-In
1 1
5 3
S
Scan-Out
O t S
Scan-Out
O t

4 4
Scan cell
2 5

Layout of a scan design A better scan-chain order

ch5-39

Overhead of Scan Design

– Number of CMOS gates = 2000

– Fraction of flip-flops = 0.478

Normalized
Scan Predicted Actual area
operating
implementation overhead overhead
frequency

None 0 0 1.0

Hierarchical 14.05% 16.93% 0.87

Optimized 14.05% 11.9% 0.91

ch5-40

20
 Random Access Scan

• Comparison with Scan-Chain

– More flexible – any FF can be accessed in constant time
– Test time could be reduced
– More hardware and routing overhead

Normal
FF 0
data D Q
Y decoder

MUX
Y address FF Test 1
data

Y-enable

X address X decoder X-enable

ch5-41

Outline

• Introduction
• Ad-Hoc Approaches
• Full Scan
• Partial Scan

ch5-42

21
 Partial Scan

• Basic idea
– Select a subset of flip-flops for scan
– Lower overhead (area and speed)
– Relaxed design rules

• Cycle-breaking technique
– Cheng & Agrawal, IEEE Trans. On Computers, April 1990
– Select scan flip-flops to simplify sequential ATPG
– Overhead is about 25% off than full scan

• Timing-driven partial scan

– Jou & Cheng, ICCAD, Nov. 1991
– Allow optimization of area, timing, and testability
simultaneously

ch5-43

Full Scan vs. Partial Scan

scan design

full scan partial scan

every flip-flop is a scan-FF NOT every flip-flop is a scan-FF

test time longer shorter

hardware overhead more less
fault coverage ~100% unpredictable
ease-of-use easier harder

ch5-44

22
 A Partial-Scan DfT Flow

Circuit file

Flip-flop selection

Circuit modifier Flip-flop list Test model generator

Test model
Circuit with
Partial scan

Test generation (stg3)

Test vectors

ch5-45

Directed Graph Of A Synchronous

Sequential Circuit

primary A circuit with six flip-flops

inputs 3

primary
primary outputs
inputs 1 2 4 5 6

primary
inputs
3
Graph of the circuit
L=3
1 2 4 5 6
L=2
L=1

Depth D=4
ch5-46

23
 Partial Scan For Cycle-Free
Structure

• Select minimal set of flip-flops

– To eliminate some or all cycles

• Self-loops of unit length

– Are not broken to reduce scan overhead
– The number of self-loops in real design can be quite large

• Limit the length of

– Consecutive self-loop paths
– Long consecutive self-loop paths in large circuits may
pose problems to sequential ATPG

ch5-47

Test Generation for Partial Scan

Circuits

• Separate scan clock is used

• Scan flip-flops are removed
– And their input and output signals are added to the
PO/PI lists

• A sequential circuit test generator

– is used for test generation

• The vector sequences

– Are then converted into scan sequences
– Each vector is preceded by a scan-in sequence to set
the states of scanned flip-flops
– A scan-out sequence is added at the end of applying
each vector

ch5-48

24
 Partial Scan Design

PI PO
PPI PPO
3
Scan Out
Scan In

1 2 4 5 6 Scan In

Scan Flip-Flops: {2, 5} Scan Out

Non-Scan FFs: {1, 3, 4, 6}

ch5-49

Trade-Off of Area Overhead v.s.

Test Generation Effort

CPU
Time

Test Area Overhead

Generation
Complexity
Area
overhead

Non-Scan Only Self-Loops Feedback Full-Scan

Remain Free Circuit

ch5-50

25
 Summary of Partial-Scan

• Partial Scan
– Allows the trade-off between test generation effort
and hardware overhead to be automatically explored

• Breaking Cycles
– Dramatically simplifies the sequential ATPG

• Limiting the Length of Self-Loop Paths

– Is crucial in reducing test generation effort for large
circuits

• Performance Degradation
– Can be minimized by using timing analysis data for
flip-flop selection

ch5-51

26
 Chapter 6

Delay Testing

Acknowledgements:
Mainly based on the lecture notes of
“VLSI Test Principles and Architectures”

ch6-1

Introduction of Delay Testing

 Delay Faulty:
 Fault that cause delay across a circuit to
violate certain timing constraint

 Delay Fault Models:

 Path delay fault
– Too much delay along a path
 Transition fault (or Gate delay fault)
– Too much delay across a particular gate

ch6-2

1
Basic Delay Testing
 Delay Test Pattern:
 A two-pattern test: <v1, v2>
 v1 is an initialization vector
 v2 causes the fault to be detected

V1  V2
00 Captured
Next Clock Cycle

01 Passing
circuit
11 Failing

Challenge: The launch time and capture time are just away
by a high-speed clock cycle time

ch6-3

Applications of Delay Tests

 Launch-off shifting
g (LOS)
( )
 Aka (also known as) skewed-load
 v1 is arbitrary, v2 is derived by a 1-bit shift of v1
 Launch-off capture (LOC)
 Aka broadside or double-capture
 v1 is arbitrary, v2 is derived from v1 through the
circuit function

ch6-4

2
Timing Sequence of Launch
Launch--off-
off-Shifting
PROS: Easier Test Generation to achieve a Higher Fault Coverage
CONS: Hard to produce the Scan-Enable signal ‘SE’
(Note: ‘SE’ has to go LOW between S1 and C1)

Shift Window Launch Window Shift Window

V1 V2
S1 C1
CK … …

d
SE

S1 is a shifting cycle
C1 is a capture cycle
d is the fast clock cycle time

ch6-5

Example of LOS
Question:
v1 is {y1=‘0’, y2=‘0’, y3=‘1’}
What is vector v2 if using LOS?
Assuming scan chain order y3y2y1
V1  V2
0? y1

0? y2 circuit

1? y3

SI (‘1’)

ch6-6

3
Timing Sequence of Launch
Launch--off-
off-Capture
PROS: Scan-Enable signal ‘SE’ to easy to produce
CONS: Fault Coverage is Lower than LOS

Shift Window Launch Window Shift Window

V1 V2
C1 C2
CK … …

d
SE

Easier to produce

C1 is a capture cycle
C2 is a capture cycle, too
d is the fast clock cycle time

ch6-7

Transition Fault Model

 Assumption:
 a large/gross delay is present at a circuit node
 Path independence:
p
 Irrespective of which path the effect is propagated, the
gross delay defect will be arriving late at an observable
point
 De-facto standard in Industry
 Simple and the number of faults is linear to circuit size
 Also needs 2 vectors to test a fault
 Formulation of transition-fault test generation:
 Node x slow
slow-to-rise
to rise (x
(x-STR)
STR) can be modeled simply as
two stuck-at faults
 (1) First time-frame: x/1 needs to be excited
 (2) Second time-frame: x/0 needs to be excited and
propagated

ch6-8

4
 Ex: LOS Pattern Generation
y1
 Target fault: y2
A
x Slow-to-rise
- A slow-to-rise
B
Test Requirement: y3
1st time frame: initialize a1 to ‘0’
2nd time frame: detect a2 s-a-0 fault SI

0 y1 1 y2
A 0 A 1/0
1 y2 x a1 1 y3 x a2

B 0 B 0/1
1 y3 0 SE
Detected
1st Time Frame 2nd Time Frame
Final 1st Pattern: (y1, y2, y3, SE) = (0, 1, 1, 0)  Shifted to become 2nd Pattern
ch6-9

Ex: LOC Pattern Generation

Free
x1
 Target fault: PIs x2
A
x Slow-to-rise
- A slow-to-rise
B
x3
Test Requirement:
1st time frame: initialize a1 to ‘0’
2nd time frame: detect a2 s-a-0 fault

0 x1 1 x1’ 1/0
A 0 A
0 x2 x a1 1 x2’ x a22

B 0 B 0/1 Detected
1 y

1st Time Frame 2nd Time Frame

ch6-10

5
Summary
 More and more ICs require delay testing (or called
timing testing, performance testing), to ensure that
an IC can perform up to its target speed.
 Better understand what LOS, LOC means, since
It’s industrial practice.
 Some IC, e.g., CPU, needs to go through speed
binning process, to determine the “quality bin” of
each IC and its sell price.
 Delay test is still a tough issue and still evolving.
evolving
Rigorous delay testing also aims to detect “small
defects” so as to reduce the test escape of latent
defects that might hurt an IC’s reliability in its field.

ch6-11

6
 國立清華大學電機系

EE-6250
超大型積體電路測試
VLSI Testing

Chapter 7
Built-In Self-Test

Design-for-Testability

• Design activities for generating a set of

test patterns with a high fault coverage.
• Methodology
– Logic
• Automatic Test Pattern Generation (ATPG)
• Scan Insertion (to ease the ATPG process)
• Built-In Self-Test
– Memory (SRAM, DRAM, …) SRAM
• Built-In Self-Test
Logic
SRAM
User Core

ch7-2

1
 Outline

• Basics
• Test Pattern Generation
• Response Analyzers
• BIST Examples
• Memory
y BIST

ch7-3

Definition & Advantages of BIST

• Built-In Self-Test (BIST) is a design-for-

t t bilit (DFT) ttechnique
testability h i iin which
hi h testing
t ti
(test generation , test application) is
accomplished through built-in hardware
features.
– [ V.D. Agrawal, C.R. Kime, and K.K. Saluja ]

Can lead to significant test time reduction

Especially attractive for embedded cores

ch7-4

2
 Good Things About BIST

• At-Speed Testing
– catching timing defects

• Fast
– reduce the testing time and testing costs
– a major advantage over scan

• Board-level or system-level testing

– can be conducted easily in field

ch7-5

General Organization of BIST

Simple on-chip Test Generator

pattern generation

off-line
pre-computed
Circuit Under Test
fault-free
(CUT)
signature

To avoid expensive signature

bit-to-bit comparison Response Compressor +

Pass-or-fail

ch7-6

3
 Why Compression ?

• Motivation
– Bit-to-bit comparison is infeasible for BIST
• Signature
Si t analysis
l i
– Compress a very long output sequence into a single
signature
– Compare the compressed word with the pre-stored
golden signature to determine the correctness of the
circuit
• Problems
– Many output sequences may have the same signature
after the compression leading to the aliasing problem
– Poor diagnosis resolution after compression

ch7-7

Aliasing Effect in Response

Compression

• Aliasing - the probability that a faulty

response is mapped to the same signature as
th ffault-free
the lt f circuit
i it (魚目混珠) 錯變成對的機率
output response space signature space



fault-free 
 
 

Response compression is a mapping

from the output response space to the signature space
In this example, aliasing prob. = 1 / 4 = 25%
ch7-8

4
 BIST Issues

• Area Overhead
• Performance
P f D
Degradation
d ti
• Fault Coverage
– Most on-chip generated patterns may not
achieve a very high fault coverage

• Diagnosability
– The chip is even harder to diagnose due to
response compression

ch7-9

Random Pattern Resistant Faults

• An RPRF cannot be detected by random patterns

• is a major cause of low fault coverage in BIST

Fault coverage inadequate coverage can be boosted by

test points, ATPG patterns, … ?

Pseudo-random pattern length

ch7-10

5
 Example: Hard-To-Detect Fault

• Hard-to-detect faults
– Faults that are not covered by random testing
– E.g., an output signal of an 18-input AND gate

Hard-to-detect fault

x
stuck-at-0

ch7-11

Reality of Logic BIST

• BIST is NOT a replacement for scan

– it is built on top
p of full-scan

• BIST does NOT result in fewer patterns

– it usually uses many more patterns than ATPG patterns

• BIST does NOT remove the need for testers

– tester still required to
• initiate test
• read response
• apply ATPG patterns to other part of IC

ch7-12

6
 BIST Techniques

• Stored-Vector Based
– Micro-instruction
Micro instruction support
– Stored in ROM

• Hardware-Based Pattern Generators

– Counters
– Linear Feedback Shift Registers
– Cellular
C ll l A Automata
t t

ch7-13

Linear Feedback Shift Register

(LFSR)

• Flip-Flop: one cycle delay

• XOR gate: modulo-2 addition
• Connection: modulo-2 multiplication

Type 1: Out-Tap Type 2: In-Tap

z D1 D2 D3 D4 D1 D2 D3 + D4
y1 y2 y3 y4 z y1 y2 y4
y3

z = y4 + y1 = D4(z) + D(z) z = y4 = D(y3 + y4) = D(D3(z) + z)

= D4(z) + D(z)
ch7-14

7
 LFSR – Example

16-bit
16 bit shift register

7th 9th 12th 16th

This sixteen-stageg LFSR will autonomously yggenerates a maximum length

g of
216-1 = 65,535 state before the sequence repeats
The seed (I.e., initial state of the LFSR) should not be all-0 state.
All 0-state is called a forbidden seed.

ch7-15

LFSR Example

D4 D3 D2 D1
+
1 0 0 0
0 0 0 1
D1 D2 D3 D4 0 0 1 1
z y1 y2 y3 y4 0 1 1 1
1 1 1 1
1 1 1 0
y1(t+1) 1001 y1(t) 1 1 0 1
y2(t+1) 1000 y2(t) 1 0 1 0
＝
y3(t+1) 0100 y3(t) 0 1 0 1
y4(t+1) 0010 y4(t) 1 0 1 1
0 1 1 0
1 1 0 0
Characteristic polynomial
1 0 0 1
g ( x )  x 4  x1  1 0
0
0
1
1
0
0
0
repeating 1 0 0 0

ch7-16

8
Ex: Primitive LFSR – State Diagram

0000

1000 0001
1100
0010

1110 0100

The register cycles through all 24-1 states

1111 if the seed is not all-0 1001
 Such a LFSR is called primitive

0111 0011

1011 0110
0101 1101
1010
ch7-17

Primitive Polynomials
(Up to Degree 100)
Note: “24 4 3 1 0” means p ( x)  x 24  x 4  x 3  x1  x 0

ch7-18

9
 Galois Field GF(2)
• Operation
– Modulo-2 addition, subtraction, multiplication, and
division of binary data
• Properties
– Modulo-2 addition and subtraction are identical
– 0+0=0, 0+1=1, 1+0=1, 1+1=0
– 0-0=0, 0-1=1, 1-0=1, 1-1=0

Bit-stream Bit-stream
multiplication division

ch7-19

Why LFSR ?

• Simple and regular structure

– D-flip-flops and XOR gates

• Compatible with scan DFT design

• Capable of exhaustive and/or pseudo
exhaustive testing
– If the LFSR is properly configured

• Low aliasing
gpprobability
y
– The fault coverage lost due to the response
compression is less than other compression schemes

ch7-20

10
 LFSR – Definitions

• Maximum-length sequence
– A sequence generated by an n-stage LFSR is called a
maximum-length sequence if it has a period of 2n-1
– A maximum-length sequence is called m-sequence
• Primitive polynomial
– The characteristic polynomial associated with a
maximum-length sequence is called a primitive
polynomial
• Irreducible
I d ibl polynomial
l i l
– A polynomial is irreducible if it cannot be factorized
into two (or more) parts, I.e., it is not divisible by any
polynomial other than 1 and itself.

ch7-21

LFSR – Properties

• No. of 1s and 0s
– The number of 1s in an m-sequence differs from the
y only
number of 0s by y one
• Pseudo-random sequence
– The sequence generated by an LFSR is called a pseudo-
random sequence
• The correlation
– Between any two output bits is very close to zero
• Consecutive run of 1s and 0s
– An m-sequence produces an equal number of runs of 1s
and 0s.
– In every m-sequence, one half the runs have length 1,
one fourth have length 2, one eighth have length 3, and
so forth
ch7-22

11
 LFSR – Polynomial Multiplication

1101
g ( x )  x4  x3  1 x3  x 2  1

+ D4 + D3 D2 D1

Output stream D 4 D3 D2 D1 Input stream

0 0 0 0 1 1 0 1
Add-and-shift
1 1 0 0 1 1 0 1
1 0 1 0 1 1 0 1
1 0 1 0 1 1 0 1
1 0 1 1 0 1 0 1
x7 x5 x4 x2 1

x 4
 x 3  1   x 3  x 2  1  x 7  x 5  x 4  x 2  1

ch7-23

LFSR – Polynomial Division

(Example)

Input g( x )  x 4  x 3  1 Output Q(x)

011011011 11001
M(x) + D1 D2 D3 + D4
x+x2+x4+x5+x7+x8 1+x+x4

M(x) D1 D2 D3 D4 Q(x) Quotient

0 1 1 0 1 1 0 1 1 0 0 0 0
after 4 0 1 1 0 1 1 0 1 1
shifts 0 1 1 0 0 1 0 0 1
0 1 1 0 0 1 0 0 1
0 1 1 0 0 1 0 0 1
0 0 1 0 1 1 0 0 1
1 0 1 1 1 1 0 0 1
Remainder 1 +x2+x3 1 +x +x4

(x8+x7+x5+x4+x2+x)  (x4+x3+1) = x4+x+1

R(x) = x3+x2+1
ch7-24

12
 LFSR – Summary

• LFSRs have two types

– In-tap and Out-tap

• LFSRs
– Can be used to implement polynomial
multiplication and division in GF(2)

• As polynomial multiplier
– LFSRs are capable of generating pseudo random
vectors

• As polynomial divisors
– LFSRs are capable of compressing test response

ch7-25

Cellular Automaton (CA)

– An one-dimensional array of cells

– Each cell contains a storage device and next
state logic
g
– Next state is a function of current state of the
cell and its neighboring cells

Next Next Next

... State State State ...

D D D
Q Q Q

Three-cell neighbor
ch7-26

13
 Cellular Automata – Name

• Name of CA functions
– Is determined by its truth table

State A0 A1 A2 A3 A4 A5 A6 A7 Next State K

K-Map
Map FCA
Ci+1 0 0 0 0 1 1 1 1 A0 A2 A4 A6
Ci 0 0 1 1 0 0 1 1 A1 A3 A5 A7
Ci-1 0 1 0 1 0 1 0 1
7
Name   Ai 2i ((defined byy Wolfram))
i0

Example: FCA  Ci 1  Ci
CiCi-1
Ci+1 00 01 11 10 Name = 64+32+4+2
0 0 1 0 1 = 102
1 0 1 0 1 ch7-27

Cellular Automata – Hardware

CA with Null Boundary Condition

0 0

Fca Fca Fca Fca Fca Fca

D D D D D D
Q Q Q Q Q Q

Standard – All the CAs are of the same type

Hybrid – The CAs are of different type
ch7-28

14
Cellular Automata – Hardware

CA with cyclic Boundary Condition

Fca Fca Fca Fca Fca Fca

D D D D D D
Q Q Q Q Q Q

ch7-29

Outline

• Basics
• Test
T t Pattern
P tt G
Generation
ti
– How to generate patterns on chip using
minimum hardware, while achieving
high fault coverage

• Response Analyzers
• BIST Examples
• Memory BIST

ch7-30

15
 On-Chip Pattern Generation

PG Hardware Pattern Generated

• Stored Patterns • Deterministic

• Counter Based • Pseudo-Exhaustive
• LFSR Based • Pseudo-Random
• Cellular
C ll l Automata
A t t • Pseudo-Random
P d R d

Pseudo Random Patterns: Random patterns with a specific sequence

defined by a seed

ch7-31

Counter Based Pattern Generation

• Generates regular test sequences

– Such as walking sequence and counting sequence for
memory interconnect testing

cycle Walking Sequence Counting Sequence

1 1 0 0 0 0 0 0 0 0 0 0
2 0 1 0 0 0 0 0 0 0 0 1
3 0 0 1 0 0 0 0 0 0 1 0
4 0 0 0 1 0 0 0 0 0 1 1
5 0 0 0 0 1 0 0 0 1 0 0
6 0 0 0 0 0 1 0 0 1 0 1 chip1 chip2
7 0 0 0 0 0 0 1 0 1 1 0
8 0 0 0 0 0 0 0 1 1 1 1
coupling between interconnects
can be tested by walking sequence
line id 1 2 3 4 5 6 7 8
ch7-32

16
 On-Chip Exhaustive Testing

• Exhaustive testing
– Apply all possible input combinations to CUD
– A complete functional testing
– 100% coverage on all possible faults

• Limitation
– Only applicable for circuits with medium number of
inputs

Signature
6-stage Circuit Under Test
Analyzer
LFSR (CUD)
(SA)

ch7-33

Pseudo Exhaustive Testing (PET)

– Apply all possible input combinations to

every partitioned
titi d sub-circuits
b i it
– 100% fault coverage on single faults and
multiple faults within the sub-circuits
– Test time is determined by the number
of sub-circuits and the number of inputs
to the sub-circuit
– Partitioning is a difficult task

ch7-34

17
 Example for Pseudo-Exhaustive
Testing

10 vectors are enough to pseudo-exhaustively test this circuit,

Compared to 26=64 vectors for naive exhaustive testing

ch7-35

LFSR-Based Pattern Generation

– Apply random test sequence generated

b LFSR/CA
by
– Simplest to design and implement
– Lowest in hardware overhead
– Fault coverage
• Is a function of the test length and the
random testability of the circuits
• Certain circuits are more resistant to random
patterns than others

ch7-36

18
Pseudo Random Testing Hardware

Combinational Sequential

LFSR LFSR

Combinational Combinational
circuit circuit

SA SA

(Circular BIST)
ch7-37

BIST – Pseudo Random Testing

Hardware

10-stage LFSR
Shift register
LFSR

S S S
Circuit Under Test CUT CUT
R R R

SA SA

(CEBT) (STUMPS)

test-per-clock configuration test-per-scan configuration

ch7-38

19
 Weighted Pseudo Random Testing

It was observed that weighted random patterns could

achieve higher fault coverage in most cases !

LFSR Based Weighted Cellular Automaton

0
LFSR
0

123 193 61 114 228 92 25

D D D D D D D

Q Q Q Q Q Q Q

1/8 3/4 1/2 7/8 1/2 0.8 0.6 0.8 0.4 0.5 0.3 0.3
ch7-39

Signal of An Arbitrary Weight

• To implement a signal
– with a signal-1 probability (weight) of 5/32

• Procedure
(1) Decompose into a sum of basic weights
5/32 = 4/32 + 1/32 = 1/8 + 1/32
(2) Use AND and OR gates to realize the weight

y1 1/8
y2
y3
z = y 1y2y3 + y 1y2y3y4y5
LFSR

a signal with a
weight of 5/32

y4
1/32
y5
ch7-40

20
 Outline

• Basics
• Test
T t Pattern
P tt G
Generation
ti
• Response Analyzers
– How to compress the output response
without losing too much accuracy

• BIST Examples
p
• Memory BIST

ch7-41

Types of Response Compression

• Ones-counting compression
• Transition-counting compression
• Signature Analysis

ch7-42

21
 Ones-Counting Signature

• Procedure
– Apply the predetermined patterns
– Count the number of ones in the output
sequence
R0=00000000
R1=11000000
Test R2=10000000
CUT
Pattern

Counter
Clock
signature OC(R0) = 0
OC(R1) = 2
OC(R2) = 1
ch7-43

Zero-Aliasing Test Set for Ones-

Counting

• Notations
– T0: set of test vectors whose fault
fault-free
free response is 0
– T1: set of test vectors whose fault-free response is 1

• Theorem
– The following new test set does NOT suffer from
fault masking using ones count testing
– T = {T0, (|T0|+1) copies of every pattern in T1}
– Note that the fault masking only occurs when a fault
is detected by the same number of patterns in T0
and T1; the above new test set avoid this condition

ch7-44

22
 Transition-Counting Signature

• Procedure
– Apply
pp y predetermined
p patterns
p
– Count the number of 01 and 10 transitions

DFF
Test
CUT
Pattern

Clock Counter

Transition count
ch7-45

Aliasing of Transition-Counting

• Consider a sub-sequence of bits

( rj-1
(… j 1 rj rj+1 …)

If rj-1 is not equal to rj+1, then an error occurring at

rj will not be detected by transition counting.

• Example
1. (0, 1, 1)  (0, 0, 1)
2. ((0,, 0,, 1))  ((0,, 1,, 1))
3. (1, 1, 0)  (1, 0, 0)
4. (1, 0, 0)  (1, 1, 0)

ch7-46

23
 Aliasing of Transition Counting

• Aliasing Probability
– Notations
• m: the test length
• r: the number of transitions
– Highest when r=m/2
– No aliasing when r=0 or r=m
– For combinational circuits, permutation of the
i
input
t sequence results
lt iin a diff
differentt signature
i t
– One can reorder the test sequence to minimize
the aliasing probability

ch7-47

Signature Analysis by LFSR

• Procedure
– Apply predetermined patterns
– Divide the output sequence by LFSR

Test
CUT LFSR
Pattern

ch7-48

24
 Example: Aliasing Probability

• Assume that
– Output
p number to be compressed
p has m=4 bits
– The compression is done by dividing output
number by a divisor of 2n-1, (e.g., the divisor is
22-1 = 3 when n=2)
– The remainder is taken as the signature

• Possible signatures
output = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
remainder = 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0
aliasing prob. when signature is 0 = (2m/(2n-1)) / 2m
= 1/ (2n-1) ~ 2-n

ch7-49

Multiple Input Shift Register (MISR)

(Temporal Compression)

• A MISR compacts responses from multiple

p
circuit outputs into a signature
g

+ D Q + D Q + D Q + D Q

clock

Aliasing probability of m stage = 2-m

ch7-50

25
 Outline

• Basics
• Test Pattern Generation
• Response Analyzers
• BIST Examples
• Memory BIST

ch7-51

Key Elements in a BIST Scheme

• Test pattern generator (TPG)

• Output response analyzer (ORA)
– Also called Signature Analyzer (SA)

• The circuit under test (CUT)

• A distribution system (DIST)
– which transmits data from TPG’s to CUT’s and from
CUT’s to ORA’s
– e.g., wires, buses, multiplexers, and scan paths

• A BIST controller
– for controlling the BIST circuitry during self-test
– could be off-chip

ch7-52

26
 HP Focus Chip (Stored Pattern)

• Chip Summary
– 450,000 NMOS devices, 300,000 Nodes
– 24MHz clocks, 300K-bit on-chip ROM
– Used in HP9000-500 Computer

• BIST Micro-program
– Use microinstructions dedicated for testing
– 100K-bit BIST micro-program in CPU ROM
– Executes 20 million clock cycles
– Greater than 95% stuck-at coverage
– A power-up test used in wafer test, system test,
field test

ch7-53

Logic BIST Example

• Features
– [Bardell 1982, 84]
g LFSR and Parallel MISR
– Self-Test using
– Multiple scan chains to reduce test time

PIs
...

Scan path
LF

M
MISR

Scan path
FSR

CUT
Scan path

...
Seed POs Signature
ch7-54

27
 Scan-Based Logic BIST
Architecture

called STUMPS architecture by Mentor Graphics

pseudo-random
d d pattern
tt generator
t

chain 3
chain 2

chain 4
chain 1

primary primary
input pins output pins

multiple input signature register

ch7-55

Built-In Logic Block Observation

(BILBO)
c Z1 c Z2 c Zn
...
B1

...
B2
MUX

Si 0
scan-in D Q D Q D Q D Q
Scan-out
1
...
Q Q Q Q S0

Q1
Q2 Qn-1 Qn

...

B1 B2 operation mode c
0 0 shift register 0
0 1 LFSR pattern generation 0
1 1 MISR response compressor 0
1 0 parallel load (normal operation) 1
ch7-56

28
 Example: BILBO-Based BIST

• Test procedure
– each logic block C1, C2, C3 are tested in a serial
manner
– BIST controller needs to configure each BILBO
registers properly during self-testing

BILBO1
when testing C1
BILBO1 is a PRPG C1
BILBO2 is a MISR
BILBO2

C2

BILBO3

C3
ch7-57

Concurrent BILBO

Logic with self-loop

top-row of D-FFs  MISR
bottom-row of D-FFs  PRPG

BILBO

C1

concurrent BILBO

needs to be
PRPG and MISR
simultaneously

ch7-58

29
 Outline

• Basics
• Test Pattern Generation
• Response Analyzers
• BIST Examples
• Memory BIST

ch7-59

The Density Issues

• Historical -Rule
– The number of bits per chip has quadrupled
roughly every 3.1 (or ) years

• Density Induced Faults

– The cells are closer together
– More
o e sensitive
se s t e to influences
ue ces of
o neighbors
e g bo s
– More vulnerable to noise on the address and
data lines

ch7-60

30
 Test Time May Get Too Long !

• For today’s memory chips

– Test time becomes a big issue !
– We can afford nothing but linear test algorithm

• Example
– assume that the clock cycle time is 100 ns
Algorithm Testing time (in seconds)
complexity
3/2 2
Capacity n 64n n•log2n 3n 2n
16k 0.1 0.023 0.63 54
64k 0.4 0.1 5.03 14 Mins
256k 1.7 0.47 40.3 3.8 Hrs
1M 6.7 2.1 5.4 Mins 61 Hrs
4M 26.8 9.2 43 Mins 41 Days
16M 1.8 Mins 40.3 5.7 Hrs 2 Years

ch7-61

IC Failure Rate Versus Time

Def: failure rate

The no. of failures per unit time as a fraction of
total population
IC’s
C s failure
a u e rate
ate is
s like
e a bat
bathtub
tub curve
cu e with
t three
t ee stages:
stages
1. Infant mortality stage: typically a few weeks
2. Normal life failure stage: up to 25 years or so
3. Wear-out stage

failure infant
wear-out
rate mortality
normal life failures
 failure rate

>>

Time
Short period of accelerated stress test prior to shipment
 To eliminate the infant mortality
ch7-62

31
 Memory Model

address register column decoder refresh logic

address

row decoder write drive

Memory
address Cell
decoder Array data
R/W
data register

enable read/write
sense amplifier control circuit
clk

ch7-63

Memory Array
P ro b lem : A S P E C T R A T IO o r H E IG H T > > W ID T H

2L- K B it Li n e
S t o rag e C ell

AK
Row Decoder

AK +1 W o rd L in e

A L -1

M .2 K

S en se A m p lifi ers / D ri v ers A m p lify s w i ng t o

r a il- to -ra i l a m p lit u d e

A0
C o l u m n D ec o de r S elect s a p p ro p ria t e
A K -1 w o rd

In p u t- O u tp u t
(M b its)

ch7-64

32
 Fault Models

• Stuck-At Faults (SAF)

– cell, data line, address line, etc.
• Open Faults (SAF)
– open in data line or in address line
• Transition Faults (TF)
1 0 1
– Cell can be set to 0, but not to 1
0 0
• Address Faults (AF)
1 0 1
– faults on decoders

• Coupling Faults (CF) cell is affected

– short or cross-talk between data (or address) lines
– A cell is affected by one of its neighboring cells

• Neighborhood Pattern Sensitive Fault (NPSF)

– A cell is affected by when its neighbors form a pattern

ch7-65

Example Faults
• SAF : Cell stuck
• SAF : Driver stuck
Fault Models
• SAF : Read/write line stuck
• SAF : Chip-select line stuck
• SAF : Data line stuck
• SAF : Open in data line
• CF : Short between data lines
• CF : Cross-talk between data lines
• AF : Address line stuck
• AF : Open in address line
• AF : Open decoder
• AF : Shorts between address lines
• AF : Wrong access
• AF : Multiple access
• TF : Cell can be set to 0 but not to 1 (or vice-versa)
• NPSF : Pattern sensitive interaction between cells
ch7-66

33
 Simple Test Algorithms

• Test Algorithm
– is an abstract description of a sequence of test patterns.

• Commonly Used Algorithms

– Background patterns
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
– Checkerboard patterns 0 0 0 0 1 1 1 1

0 1 0 1 1 0 1 0
1 0 1 0 0 1 0 1
– March Patterns 0 1 0 1 1 0 1 0
1 0 1 0 0 1 0 1

ch7-67

A March Algorithm

(Forward march that changes each cell’s content from 0 to 1)

0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

(Backward march that changes each cell’s content from 1 back to 0)

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ch7-68

34
 Example: A Memory BIST

normal
inputs tester/BIST

BIST
S CCircuit
cu
pattern generator

MUX
clock
FSM-1

output bufffer
test Memory
patterns
delay buffer

reset
memory
response
comparator

pass_or_fail test_done
ch7-69

Finite State Machine for March Alg.

0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

if(a != N) a++; if(a != N) a++;

if(a != N) a++;

S1 S2 S3 S4 S5
WRITE-0 READ-0 WRITE-1 READ-1 READ-1
if(a == N) if(a == N)
a=0;; aa=0;
0;
a = 0;
Notations of this extended state transition graph:
a: variable for address
N: number of cells
START END

ch7-70

35
 Testing Procedure of BISTed Memory
Start
normal tester/
inputs BIST
set the test mode to BIST

apply clocking signals to input pin clk

clk
set input signal reset to 1 for

MUX
more than one clock cycles
reset
set input signal reset to 0 to test
start the BIST operation BIST patterns Memory

wait until the output response pass_or_fail

of the output pin test_done is 1 memory
response
test_done
catch the response of output pin pass_or_fail

Done
ch7-71

A Waveform Example

clock
reset

cmd R W R R W R R W R R W R R W R

data 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1

address 0 0 0 1 1 1 2 2 2 3 3 3 4 4 4

test_done
pass_or_fail

ch7-72

36
 Quality Measures of BIST

BIST-vs.-Tester Tester
Profile
pass fail

B (I) 漏網之魚
pass (III)
I
S 誤殺者
fail (II) (IV)
T

To minimize region (II) and (III):

1. False Negative Ratio: (II) / #chips e.g., (1/20) = 5%
2. False Positive Ratio: (III) / #chips e.g., (2/20) = 10%

ch7-73

37
 Chapter 8

Test Compression

Acknowledgements:
M i l based
Mainly b d on the
th lecture
l t notes
t off
Chapter 6, “VLSI Test Principles and Architectures”

ch8-1

What is this Chapter about?

 Introduce the basic concepts of test data

compression
 Focus on stimulus compression and
response compaction techniques
 Present and discuss commercial tools on
test compression

ch8-2

1
 Test Compression
 Introduction
 Test Stimulus Compression
 Test Response Compaction
 Industry Practices
 Concluding Remarks

ch8-3

Introduction

 Why do we need test compression?

 Test data volume
 Test time
 Test pins
 Why can we compress test data?
 Test vectors have a lot of “don’t care” (X’s)

ch8-4

2
Test Data Volume v.s
v.s.. Gate Count
Tes
70
st Data Volume (G

60
50
40
30
20 Test data volume
10 increases with circuit size
Gb)

0
1 2 4 8 16 32 64

Gate count (M)

(Source: Blyler, Wireless System Design, 2001)

ch8-5

Test Compression Categories

 Test Stimulus Compression

 (1) Code-based schemes
 (2) Linear-decompression-based schemes
 (3) Broadcast-scan-based schemes
 Test Response Compaction
 Space
p compaction
p
 Time compaction
 Mixed time and space compaction

ch8-6

3
 Architecture for Test Compression

Compressed

Decompressor
Stimulus Core Compacted

Compactor
Stimulus Response
Response
Low-Cost
ATE

ch8-7

Test Stimulus Compression

 Code-based schemes
 Dictionary code (fixed-to-fixed)
 Huffman code (fixed-to-variable)
 Run-length code (variable-to-fixed)
 Golomb code (variable-to-variable)
 Linear-decompression-based schemes
 Broadcast-scan-based schemes

ch8-8

4
 Dictionary Code
 Dictionary code (fixed-to-fixed)

A test vector is considered as a two-dimensional image

In multiple scan chains (e.g., n scan chains as shown)

ch8-9

Huffman Code
 Huffman code (fixed-to-variable)

Each is code from ATE

A test vector is partitioned into a number of 4-bit patterns

ch8-10

5
 Huffman Tree
(More Frequent Symbol, Shorter Code)
 Huffman code (fixed-to-variable)

Bottom-up
construction
ch8-11

Run--Length Code
Run
 Run-length code (variable-to-fixed)

ch8-12

6
 Golomb Code
 Golomb code (variable-to-variable)

ch8-13

Example of Golomb Code

 Golomb code (variable-to-variable)

ch8-14

7
 Test Stimulus Compression

 Code-based schemes
 Linear-decompression-based schemes
 Broadcast-scan-based schemes

ch8-15

Linear--Decompression-
Linear Decompression-Based Schemes
Seed of LFSR: (X1, X2, X3, X4)

Compressed
Test vector
To be applied
From ATE

ch8-16

8
 Matrix Form
(Linear--Decompression-
(Linear Decompression-Based Schemes)
Decompressor Compressed Test Vector + Seed (?)
Matrix (?)

Original
Test
Vector
(Given)

ch8-17

Solving Linear Decompressor & Its Seed

(Z is Test Vector)

(Z Vector with only care bits) Pivot elements indicated in circles

ch8-18

9
Hardware for Linear-
Linear-Decompressor

XOR XOR Network

Network

MISR

ch8-19

XOR Network: a 3-
3-to-
to-5 Example
s1 s2 s3

o1 o2 o3 o4 o5
ch8-20

10
 Test Stimulus Compression

 Code-based schemes
 Linear-decompression-based schemes
 Broadcast-scan-based schemes

ch8-21

Basic Concept: Broadcast

Broadcast--Scan
{SC1, SC2, …, SCk} shares the same test patterns applied by ATE

ch8-22

11
ATPG Supporting Broadcast-
Broadcast-Scan
 Force ATPG tool to generate patterns for
broadcast scan ((by
y binding
g certain PI’s together)
g )

ch8-23

Reconfigurable Broadcast Scan

 Reconfigurable broadcast scan

 Static reconfiguration
– The reconfiguration can only be done when a new
pattern is to be applied
 Dynamic reconfiguration
– The configuration can be changed while scanning in
a pattern

ch8-24

12
 Broadcast--Scan Based Scheme
Broadcast
 First configuration is: 1->{2,3,6}, 2->{7}, 3->{5,8}, 4->{1,4}
 Second configuration
g is: 1->{1,6},
, , 2->{2,4},
, , 3->{3,5,7,8}
, , ,

First Partition Second Partition

ch8-25

Compatibility Graph – Finding Cliques

O i i l Test
Original T t Pattern
P tt

2 First Partition Second Partition

1 3 Cliques (fully connected sub-graphs):

(1){SC2, SC3, SC6, SC7}  (000X1)
(2){SC5, SC8}  (0X1XX)
4 8
(3){SC1, SC4}  (111X0)
 Overall 8 sub-patterns down to 3
5 7
6 ch8-26

13
 Broadcast--Scan Based Scheme
Broadcast

ch8-27

Test Response Compaction

(or Called Output Compaction)
 Space compaction
 Time compaction
 Mixed time and space compaction

Unlike lossless input stimulus compression,

O t t compaction
Output ti isi often
ft lossy,
l l di to
leading t aliasing…
li i

ch8-28

14
 Test Response Compaction

ch8-29

Space (Output) Compaction

 Space (output) compaction

 Zero-aliasing output compaction
 X-compactor
 X-blocking & X-masking techniques
 X-impact-aware ATPG

ch8-30

15
 Zero--Aliasing Output Compaction
Zero

 Zero-aliasing linear compaction

ch8-31

Example: Response Graph

Faulty response

Fault-free 00 01

3-colorable

Faulty response 10 11 Fault-free

ch8-32

16
 Architecture of X-
X-Compactor
 X-compactor with 8 inputs and 5 outputs

ch8-33

X-compact Matrix
Out1 Out2 Out3 Out4 Out5

1 1 1 0 0 SC1  SC1 drives {Out1, Out2, Out3}

1 0 1 1 0 SC2
  Matrix Form:
1 1 0 1 0 SC3
   Out1
1 1 0 0 1 SC4
M   Out 2
1 0 1 0 1 SC5  
  SC1 x 8  M 8 x 5  Out 3  Out5 x1
1 0 0 1 1 SC6
 
0 1 0 1 1 SC7 Out 4
  Out 5
0 0 1 1 1 SC8

SC  SC1 SC2 SC3 SC4 SC5 SC6 SC7 SC8

ch8-34

17
 X-Blocking or Masking Techniques

 X-blocking (or X-bounding, X-avoiding)

 X’s can be blocked before reaching the response
compactor
 To ensure that no X’s will be observed
 May still have fault coverage loss
 Add area overhead and may impact delay

ch8-35

X-Blocking by Selection
 Illustration of the X-blocking scheme

(This is a bit stream provided by ATE)

Final Output
To ATE

ch8-36

18
 X-Masking by Masking Logic
‘X’

‘1’

Final Output
To ATE

Could be on-chip LFSR

When there is an X in a scan chain output,

a controlling value , i.e., ‘1’ in this example, is issued to mask it out

ch8-37

X-Tolerance by
Counter--Based Output Selection
Counter

X X

{0, +1, -1, +2, -2, etc.)

Dynamic path means counter operation can be changed at any scan cycle
ch8-38

19
 X-Impact-
Impact-Aware ATPG

 Concept
 Simply use ATPG to algorithmically handle the
impact of residual X’s on the space compactor
 Without adding any extra circuitry

ch8-39

Example: Handling X in ATPG

Path (G5G6SC4G8q) might be contaminated by ‘X’ at f
(1) Propagate the fault effect through (f1G3G2SC2G7p)  b=0, c=1
((2)) Kill the X by g g to ‘1’  SC4=0  q is observable
y assigning
g

ch8-40

20
 Output--Compactor-
Output Compactor-Aware ATPG
 f2/1
fault could be masked as propagated to p
 Block aliasing by assigning a to ‘0’

ch8-41

Time Compaction

 Time compaction
 A time compactor uses sequential logic to
compact test responses
 MISR is most widely adopted
 n-stage MISR can be described by specifying a
characteristic polynomial of degree n

ch8-42

21
 Multiple--Input Signature Register
Multiple

ch8-43

Mixed Time & Space Compaction

 Mixed time and space compaction

ch8-44

22
 Industry Practices
 OPMISR+
 Embedded
E b dd d Deterministic
D t i i ti Test
T t
 Virtual Scan and UltraScan
 Adaptive Scan
 ETCompression

ch8-45

Industry Solutions Categories

 Linear-decompression-based schemes
 Two steps
– ETCompression, LogicVision
– TestKompress, Mentor Graphics
– SOCBIST, Synopsys
 Broadcast-scan-based schemes
 Single step
– SPMISR+
SPMISR+, Cadence
– VirtualScan and UltraScan, SynTest
– DFT MAX, Synopsys

ch8-46

23
General Scan Architecture for OPMISR+

ch8-47

EDT ((TestKompression
TestKompression)) Architecture

ch8-48

24
 Concluding Remarks
 Test compression is
 An effective method for reducing test data volume
and test application time with relatively small cost
 An effective test structure for embedded hard cores
 Easy to implement and capable of producing high-
quality tests
 Successful as part of standard design flow

ch8-49

25
 國立清華大學電機系

EE-6250
超大型積體電路測試
VLSI Testing

Chapter 9
Boundary Scan

Objectives

• Standards for board level testing

• Used for
– Chips
– Chip interconnections
Through-hole Surface
– Modules mounting mount
– Modules interconnections
53 ICs + 40 discrete devices
– Subsystems
– Systems
– Multi-chip modules
• Die-to-board integration

ch9-2

1
 Board Testing Setup

TDI: Test Data In

TDO: Test Data Out
TMS: Test Mode Selection
TCK: Test Clock
TRST*: Test Reset

ch9-3

A Printed Circuit Board with

Boundary Scan
Boundary scan use 4 or 5 wire bus to provide accessibility to the
I/O pins of selected on-board IC  thereby facilitating board-level testing

TDI

TDO

ch9-4

2
 History

• 1985
– Joint European Test Action Group (JETAG, Philips)
• 1986
– VHSIC Element-Test & Maintenance (ETM) bus standard (IBM et al.)
– VHSIC Test & Maintenance TM Bus Structure (IBM et al.)
• 1988
– Joint Test Action Group (JTAG) proposed Boundary Scan Standard
• 1990
– Boundary Scan approved as IEEE Std. 1149.1-1990
– Boundary Scan Description Language (BSDL) proposed by HP
• 1993
– 1149.1a –1993 approved to replace 1149.1-1990
• 1994
– 1149.1b BSDL approved
• 1995
– 1149.5 approved ch9-5

Overview of P1149 Family

Number Title Status

1149.1 Testing of digital chips and Std. 1149.1-1990
Interconnections between Std. 1149.1a-1993
Chips Std. 1149.1b-1994 (BSDL)

1149.2 Extended Digital Serial Near Completion

Interface

1149.3 Direct Access Testability Discontinue

Interface

1149 4
1149.4 Mixed Signal Test Bus
Mixed-Signal Started Nov
Nov. 1991

1149.5 Standard Module Test and Std. 1149.5-1995

Maintenance (MTM) Bus
Protocol

1149 Unification Not yet started

ch9-6

3
 Basic Chip Architecture of 1149.1

Boundary Boundary
Scan Cell Scan path

I/O Pins I/O Pins

Internal
Logic

Sin Sout

TDI Miscellaneous registers M

U TDO
Instruction register
X
TRST* Bypass register

TAP controller TCK

TMS

ch9-7

Boundary Scan Circuitry in a Chip

TDI: Test Data In

TDO: Test Data Out Test Data Registers
TMS: Test Mode Selection
TCK: Test Clock Design Spec Reg
Design-Spec. Reg.
TRST*: Test Reset
Device-ID Reg. M
U
M
TDO Boundary Scan Reg. X 1D
U
TDI X
Bypass Reg. (1 bit) C1 EN
T
A ClockDR
3 ShiftDR select
P Reset
TRST*
S p
UpdateDR
TMS TAP
TCK
TCK Controller ClockIR IR decode
3 ShiftIR
UpdateIR Enable

Instruction Register

ch9-8

4
 Hardware Components of 1149.1

• TAP (Test Access Port)

– TMS, TCK, TDI, TDO, TRST* (optional)
• TAP Controller
– A finite state machine with 16 states
– Input: TCK, TMS
– Output: 9 or 10 signals including ClockDR, UpdateDR,
shiftDR, ClockIR, UpdateIR, ShiftIR, Select, Enable, TCK,
and the optional TRST*
• IR (Instruction Register)
• TDR (Test Data Register)
– Mandatory: boundary scan register and bypass register
– Optional: device-ID register, design-specific registers,
etc.

ch9-9

Bus Protocol

IR Configuration Scan-In Launch Capture Scan-Out

Serially
y send instruction over
TDI into instruction register

Test circuitry is configured

To respond to instruction
(Scan in data through TDI)

Execute test instruction

Shift out test results through TDO

New test data on TDI can be shifted in simultaneously

ch9-10

5
 A Typical Boundary Scan Cell

SOUT
IN 0
MUX OUT
1
0
MUX
1 1D Q 1D Q

QA QB Mode_Control
SIN ShiftDR
ClockDR UpdateDR

• Operation Modes
– Normal: Mode_control=0; INOUT
– Scan: ShiftDR=1, ClockDR; TDI…SINSOUT…TDO
捕 – Capture: ShiftDR=0, ClockDR; INQA, OUT driven by IN or QB
投 – Update: Mode_Control=1, UpdateDR; QBOUT

ch9-11

State Diagram of TAP Controller

Control of data registers Control of instr. registers

Test-Logic-
Reset
0 1 1
1 1 S l t DR S
Select-DR-Scan S l t IR S
Select-IR-Scan
0 0
Run-Test / Idle
Capture-DR Capture-IR
1 0 0 0
0
0
Shift-DR Shift-IR
1 1
1
Exit1-DR Exit1-IR 1
0 0
Pause-DR Pause-IR
0 1 0 0 1 0
Exit2-DR Exit2-IR
1 1
Update-DR Update-IR
1 1 0
0
ch9-12

6
 States of TAP Controller

– Test-Logic-Reset: normal mode

– Run-Test/Idle: wait for internal test such as BIST
– Select-DR-Scan: initiate a data-scan sequence
– Capture-DR: load test data in parallel
– Shift-DR: load test data in series
– Exit1-DR: Finish phase-1 shifting of data
– Pause-DR: Temporarily hold the scan operation
(allow the bus master to reload data)
– Exit2-DR: finish phase-2 shifting of data
– Update-DR: parallel load from associated shift registers

ch9-13

Instruction Set

• EXTEST
– Test Interconnection between chips and board

• SAMPLE/PRELOAD
– Sample and shift out data or shift data only

• BYPASS
– Bypass data through a chip

• Optional
– Intest, RunBist, CLAMP, Idcode, usercode, High-Z,
etc.

ch9-14

7
 EXTEST
Chip1 Chip2

1. Shift-DR Internal 0 Internal

(chip 1) g
Logic Logic

TDI Registers TDO TDI Registers

TAP Controller TAP Controller

2. Update-DR
Internal 0 0 Internal
(chip 1) Logic
Logic
3. Capture-DR
(chip 2) TDO TDI Registers
TDI Registers
g TDO
TAP Controller TAP Controller

Internal 0 Internal
4. Shift-DR Logic Logic
(chip 2)
TDI Registers TDO TDI Registers

TAP Controller
TAP Controller
ch9-15

EXTEST

Input
M M
Internal Output
1. Shift-DR QA QB
U
X
Logic U
X
QA QB
(Chip1) TDI
TDO

Input Output to
M M Chip2
2. Update-DR U
Internal
Logic U
QA QB X X
(Chip1) QA QB

TDI
TDO
Input from
Chip1
M M
Internal Output
3. Capture-DR QA
U
Logic U
QB X QA QB X
(C
(Chip2)
)
TDI
TDO

Input
4. Shift-DR M
Internal M Output
U
(Chip2) QA QB X
Logic
QA QB
U
X

TDI
TDO

ch9-16

8
 SAMPLE/PRELOAD

Input

M Internal
SAMPLE U Logic M Output
U
X
QA X
QB
QA QB

TDI TDO

Input

Internal
M
PRELOAD U
Logic M
U
Output
X
QA X
QB QA QB

TDI TDO

Sample/Preload is one instruction that allows

1. Sample and shift (out) or
2. Shift (in) only

ch9-17

BYPASS

Internal
Logic

Bypass
TDI Register TDO
(1 bit)

TAP Controller

ch9-18

9
 INTEST

Internal Internal
0
Logic 0
Logic
1 Shift-DR
1.Shift-DR 2.Update-DR
2.Update DR

TDI TDO TDO

Registers TDI Registers

TAP Controller TAP Controller

Internal 0 Internal 0

3.Capture-DR Logic 4. Shift-DR Logic

TDI TDO TDI Registers TDO

Registers

TAP Controller TAP Controller

ch9-19

INTEST

Input
M M
Internal Output
U
1. Shift-DR QA QB X
Logic
QA QB
U
X

TDI
TDO

Input
M M Output
Internal
2. Update-DR QA QB
U
X
Logic
QA QB
U
X

TDI
TDO

Input
M M
Internal Output
U U
Logic
3 Capture
3. Capture-DR
DR QA QB X QA QB X

TDI
TDO

Input
M M Output
Internal
U
4. Shift-DR QA QB X
Logic
QA QB
U
X

TDI
TDO

ch9-20

10
A Printed Circuit Board With 1149.1
(Ring configuration, test controller on board)

Chip1 Chip2

Internal Internal
Logic Logic

M M
Registers U
X
Registers U
X

TAP Controller TAP Controller

TAP Controller
M
U
X
Registers
TDI

MASTER TDO
Internal
Controller TMS
Logic
TCK

Chip3

ch9-21

Test Bus Configuration

Application chips Application chips

TDI TDI
TCK TCK
#1 TMS #1
TMS
Bus TDO Bus TDO
master master

TDI TD0 TDI

TD0 TDI
TCK TCK
#2 TMS1 #2
TDI TMS TMS
TMS2
TDO TDO
TMS
TMSN
TCK TCK

TDI
TDI
TCK
#N TCK
TMS #N
TMS
TDO
TDO

Ring configuration Star configuration

ch9-22

11
 國立清華大學電機系

EE-6250
超大型積體電路測試
VLSI Testing

Chapter 10
High-Speed Interconnect Testing

Outline

 Introduction
 Problem,
Problem Objective,
Objective Review
Review, and Motivation
 Pulse-Vanishing Test (PV-Test)
 VOT-Based Oscillation Test

1
 Testing Interconnects in 3D IC

Problem Addressed:
To develop a low-cost method to test the delay fault
associated
i t d with
ith th
the TSV (Through
(Th h Silicon
Sili Via)
Vi )

TSV

TSV DIE2
DIE1
TSV

TSV
Delay fault

3D-IC using TSVs

3

SEM Photos of TSV Defects

(0.18um Through Silicon Stacking at ITRI)
A partially faulty TSV may not operate as fast as we expect
(and it could deteriorate over time…)
TSV Void Misaligned micro-bump
26.3µm
61.4µm
51.7µm

Missing bump Structural damage

2
 Testing Interconnects in 2.5-D IC

 For each die, interposer wires are like Pseudo-IOs

 Boundary scan cells needed for (1) Die Test, and (2) Interconnect Test

TAP : IEEE-1149 TAP controller : Boundary scan cell

Die #1 Die Die Die

TAP
TAP #2 TAP
#3 TAP
#4

interposer
TSV TSV

Controls TDI TDO

Controls: Boundary Scan Control Signals {TCK, TRST, TMS}

Parametric Faults in
High-Speed Die-to-Die Interposer Wires

(1) Resistive Open Fault in an interposer wire 1

(2) Resistive Bridging Fault between two interposer wires 2

Micro-bump Die #1 Die #2 Die #3 Die #4

Inter
2
-poser 1

C4 bumps for connecting to package substrate

3
 Objective and Challenge

Objective: To detect parametric faults (e.g., <1ns delay fault)

May need to maintain a pitcher-catcher timing relationship across dies
(This type of cross-die clock synchronization may not be easy)
 There are so other choices
choices…

wrapper

wrapper
×
Pitching Catching
die die

TCK1 TCK2

TCK1

TCK2

delay threshold (e.g., 1ns)

Note: test clocks TCK1 and TCK2 are low-speed test clocks (e.g., 10MHz)

Outline

 Introduction
 Pulse-Vanishing Test (PV-Test)
- At-speed testing for high-speed interconnects
 VOT-Based Oscillation Test

4
 Electrical Model of an Interposer Wire

An interposer wire is decomposed into multiple segments of r and c

rmb is tthee resistance
esista ce of the
t e micro-bump
ic o bu p

Driver Receiver
rmb r r r r r r r r r r rmb
A
c c c c c c c c c c WO

‘IW-delay’: interposer wire delay from A to WO

Resistive Open Fault Model

Rwire = N · r
Driver
rmb r r r r r r r r r r rmb
A B
c c c c c c c c c c WO

(a) Fault-free model of an interconnect.

Excessively large resistance Ropen

Driver
rmb r r r r r r r r r rmb
A WO B
c c c c c c c c c c

(b) Faulty model of an interconnect with a resistive open fault.

10

5
 Resistive Bridging Fault Model

11

Pulse-Vanishing Test (PV-Test)

Pulse-Vanishing Test:
(1) Test Stimulus: A short-duration pulse (0-1-0)
(2) Fault Detection Criterion:
If the p
pulse vanishes at the receiver’s output,
p then there is a delay
y fault

Driver Receiver
A fault-free interposer wire WO B

Threshold

at-speed clock cycle time (e.g., 1ns)

faulty interposer wire

Driver (with high resistance) Receiver
A WO B
‘0’

Threshold

12

6
 Primitive DfT Circuit
(for Pulse-Vanishing Test)
LAUNCH CAPTURE
CELL TM CELL
functional Driver Interposer Wire (IW) Receiver
input
p 0 A under test WO B
D Q 1
FF
‘1’ D Q ‘1’
R
1ns FF
SE
Threshold (‘0’ initially)

(‘0’ initially)

A two-pulse signal (shared by all IWs)

At-speed clock cycle time (e.g., 1ns) PV-test

controller

13

Vanishing Pulse Width

(for 1000 m Long Interposer Wire)
Def: Vanishing Pulse-Width (VPW)
The pulse-width of the applied test pulse above which
the pulse will vanish at the receiver
2.1
nishing-Pulse Width

1.9
1.7
1.5
(ns)

1.3
1.1
0.9
Van

0.7 fault-free
0.5
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1

Interposer wire delay (ns)

Comment: A larger test pulse width implies larger delay test threshold

14

7
 Boundary-Scan Compatible Launch Cell

When ‘PVT_fire’ is ‘1’:

(1) 2nd FF behaves like a toggle-type FF
(2) Two-Pulse signal ‘TP’ is applied to the clock port of 2nd FF

SO TM
In
(from core) 0 Out
0 Q1 1 (to IW)
Q 1 Q
D D
Q2
SI 1
FF
0
FF
1
Shift_DR PVT_fire
0

Clock_DR TP
PVT_fire
Update_DR1
Note: Q2 needs to be initialized to ‘0’ before a test session
15

Boundary-Scan Compatible Capture Cell

When ‘PVT_fire’ is ‘1’:

(1) 1st FF is set to ‘1’ if receiving a clock pulse, otherwise stays ‘0’
(2) Input signal ‘IN’ is applied to the clock port of 1st FF

SO TM
In
(from IW) 0
PVT_fire Out
0 ‘1’ 1 Q1 Q 1 (to core)
D Q D
0 Q2
SI 1
FF
‘0’’1’
FF
In 1
Shif DR
Shift_DR 0
PVT_fire Update_D
Clock_DR R2
Note: Q1 needs to be initialized to ‘0’ before a test session
The final test result is stored at Q1
16

8
 Built-In Self-Test Architecture

: launch cell : capture cell

Interposer
Wires

PV Test Wrapper
P

PV Test Wrappeer
Die 1 Die 2
(Master) (Slave)
Test
Scheduler
TDO TDI

PV-test
{TCK, Controller
Start_BIST} pass/fail {TCK, TRST, TMS}

Tester
17

PV-Test Procedure
(Scan-In, Init, Pulse, Scan-Out)

Time
Scan Scan Scan Scan Init Pulse Scan Scan Scan Scan

Scan-In all-’0’ pattern Initialize Pulse Scan-Out Results

to Q1 of every launch cell Launch cells Cycle from Q1 of each capture cell

‘Init’: Update the value of Q1 to Q2 in every launch cell

‘Pulse’: Perform pulse-launch and pulse-capture in the same test clock cycle

18

9
 Simulation Waveforms of a PV-Test

TCLK

States Scan-In
Scan In Init Pulse Scan-Out
Scan Out
PVT_fire

Test_Pulse All launch cells fire

Out_IW1
Inadequate pulse at
Out_IW2 2nd capture cell

Out IW3
Out_IW3
Failing bit
Out_IW4

Pass/Fail

Test Result: Interposer wire IW2 is faulty!

19

Test Time

 A PV-test session using 10MHz test clock is about

0 82 ms for 1024 interposer wires
0.82
26.21 ms for 32K (32,768) interposer wires

20

10
 Area Overhead
Estimation is based on a 90nm CMOS process

Area overhead
yp
Type Cell Name y
Layout Area (  )
(m*m)
INVERTER 2.82
Basic 2-input NAND Cell 2.94
Cells MUX Cell 8.47
FF Cell 17.64
Boundary Scan Cell 52.22
B i
Basic Launch Cell 92 56
92.56
Macros Capture Cell 69.16
PV-test controller 670.3
Overhead 55.55% for 1024 interposer wires
Percentage
Over 1149.1 54.9% for 32,768 interposer wires
21

Summary of PV-Test

The interposer needs to be tested alone and thoroughly.

And also, when a 2.5-D IC fails,
We know if the interposer should be responsible.
responsible

 Advantages of Pulse-Vanishing Test

- Simple fault detection scheme (No post-processing)
- Delay Test without die-to-die high-speed clock synchronization
- Boundary-Scan-Like Test Architecture (55.55% overhead)
- On-the-spot Diagnosis (good for future self-repair)

22

11
 Outline

 Introduction
 Pulse-Vanishing Test (PV-Test)
 VOT-Based Oscillation Test
- Characterization-based parametric fault testing

23

Concept 1:
It’s a matter of transition time measurement!

A TSV with delay fault  Longer Rise/Fall Time

TSV1

Observation point

Normal TSV
 Shorter
Sh t rise
i time
ti

Resistive TSV
 Longer rise time
To be measured…
24

12
 Concept 2: Use Schmitt-Trigger Inverter
- Hysteresis proportional to the input Transition time
Smaller hysteresis

Schematic

VDD
Larger hysteresis
Vout (v)
1.8

Vin Vout
VDD
Vin(v)
1.8

VTH(0-1) =0.54(v) VTH(1-0) =1.27(v)

25

Architecture of VOT Scheme (Per TSV Pair)

(VOT: Variable Output Threshold)
Use Variable-Threshold Output Inverter for each TSV:
(1) Control signal Z = 0  Normal Inverter
(2) Control signal Z = 1  Schmitt-Trigger Inverter (WITH HYSTERESIS)

Z1 OR_enable2

TSV1

Die1 Die2

TSV2

OR_enable1 Z2

26

13
 Brief Summary of our Idea

TSV Delay  Transition Time

Transition Time  Oscillation Period Change

(from normal to Schmitt-Trigger)

(Easily Measurable)

27

Schematic of a VOT Inverter

(a) overall schematic (b) normal inverter (Z=0) (c) ST inverter (Z=1)
VDD VDD VDD
Z

Vin Vout Vin Vout Vin Vout

VDD VDD

28

14
 Three Oscillation Periods in VOT-Analysis

(1) Normal mode:

Oscillation period=TREF

(2) TSV1-in-ST mode

Oscillation period=TST1
TSV1 delay ~ T1 (TST1 – TREF)

(3) TSV2-in-ST mode

Oscillation period=TST2
TSV2 delay ~ T2 (TST1 – TREF)
29

Example: Predict the Delay of Each TSV

RTSV1=10 (Ω) CTSV1=400 (fF) RTSV2 =1 (kΩ) CTSV2=800 (fF)
Waveforms under the normal configuration TREF = 4.42 ns
Smaller
endpoint of TSV1
Transition times
Larger
endpoint of TSV2
Transition times

Waveforms under the Schmitt-Trigger configuration

endpoint of TSV1 TST1 = 5.05 ns

endpoint
d i t off TSV2 TST2 = 6.49
6 49 ns

Normal Configuration: TREF = 4.42 ns

TSV1-in-ST Configuration: TST1 = 5.05 ns (smaller increase from TREF)
TSV2-in-ST Configuration: TST2 = 6.49 ns (larger increase from TREF)
∆TST1 = 5.05 – 4.42 = 0.63 ns
∆TST2 = 6.49 – 4.42 = 2.07 ns
30

15
Ex: Correlation between TSV Delay and T
 Fault Population: Resistive Open Faults
 An outlier in measurable T is an outlier in TSV delay

T = TST  TREF
T

Fault
F lt
Free

31

RO, MUX Tree, and Measurement Circuits

32

16
 Ring Oscillator (RO)
(for One Pair of Interposer Wires)

Two extra Control Signals (to support bridging fault detection):

(1) ‘Osc_en’: enabling signal for oscillation
(2) ‘Tri
Tri_en
en’:: tri
tri-state
state enabling signal for the driver of IW2

Test_Mode ‘1’ output ‘Z1’

Interposer
functional
input
IW1
Observ.
point Die 1 Die 2
IW2
functional
input
‘Osc_en’ ‘Z2’ output ‘Tri_en’ Test_Mode

33

Three Test Strategies

Principles:
(1) All ROs oscillate concurrently to detect “resistive open faults”
(2) One RO oscillates at a time to detect “inter-RO resistive bridging faults”
(3) No RO oscillates to detect “intra-RO resistive bridging faults”

Test Strategy RO Settings Test Actions

Measure
Test AO-strategy {TREF ,TST1 ,TST2}
OPEN
Every RO is Active
(All Oscillation) of every RO in
sequence
Measure
Test Target
g RO is Active
{TREF,T
TST1 ,T
TST2}
Inter-RO OO-strategy (One RO at a time)
BRIDGING of the target RO
(One Oscillation)
The others are
NA
Grounded
Test
Intro-RO
NO-strategy Every RO is Half- Measure {TREF }
BRIDGING (No Oscillation) Floating of every RO
34

17
 AO-strategy (All-Oscillation)
(to detect an open fault)
Test_Mode ‘1’ ‘Z1’
Interposer

slow IW
Die 1 Active RO Die 2

‘Osc_en’ = ‘1’ ‘Z2’ ‘Tri_en’ = ‘1’ Test_Mode

An open fault occurring to an interposer wire.

35

OO-strategy (One-Oscillation)
(to detect an inter-RO bridging fault)
An inter-RO bridging fault will slow down the speed over a victim IW.
‘1’ ‘Z1’
Interposer

Active RO
victim IW

‘Osc_en’ = ‘1’ ‘Z2’ ‘Tri_en’ = ‘1’Test_Mode

Test_Mode ‘1’ Die 1 Die 2 ‘Z1’

‘0’ aggressor IW
Grounded RO

‘0’
‘Osc_en’ = ‘0’ ‘Z2’ ‘Tri_en’ = ‘1’ 36

18
 NO-strategy (No-Oscillation)
(to detect an intro-RO bridging faults)

The existence of an intro-RO bridging fault will

cause a half-floating RO to oscillate abnormally.

Test_Mode ‘1’ ‘Z1’

Interposer

Die 1Oscillation Floating Die 2

Half-Floating RO
‘Osc_en’ = ‘1’ ‘Z2’ ‘Tri_en’ = ‘0’ Test_Mode

37

Waveform of ‘End Point’ and ‘Observation point’ in NO-strategy

100ns 200ns 100ns 200ns

1V 1V
Test Mode
0V 0V
ult

1V 1V
Weaker Inttra-Bridging Fau

1 kΩ
0V 0V
Intrra Bridge Fault

1V 1V
100 kΩ
Resistance

0V 0.5v 0V
1V 1V
500 kΩ Fault is Detected!
0V 0V
1V 0.4v 1V
1 MΩ Fault is not Undetected!
0V 0V
100ns 200ns 100ns 200ns
End point Observation point
38

19
 Example for an Inter-Bridging Fault

Consistent slower rise time

39

Example for an Inter-Bridging Fault

50
AO‐strategy
urrences

40
30
No. of occu

20
10
0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95
Normalized Tdriff (%)
50
OO‐strategy
ences

5K Inter Bridging Fault 1000um IW

40
Resistance at mid‐point 1K Open Fault
No. of occurre

30 of 500um and 1000um IWs at micro bump

20
10
0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95
Normalized Tdriff (%)
40

20
 Fault Type Classification

41

Normalized Tdrift for Outlier Analysis

For each IW wi, we have two versions of T:

Tsim ( wi )  TST _ sim ( wi )  TREF _ sim ( wi )

Tmeasure ( wi )  TST _ measure ( wi )  TREF _ measure ( wi )

Tdrift(wi) respresents the drifting amount of a measurement

version of T away from its simulation version:

Tdrift ( wi )  Tmeasure ( wi )  Tsim ( wi )

To take into account of the wire-length diversity, we further

normalize it:
 T  Tsim 
( Normalized _ Tdrift )   measure  100%
  T sim 
42

21
 Testing and Characterization Flow

* IW : Interposer Wire 43

Fault Detection
(Finding Outliers in Normalized Tdrift)

50
urrences

Population: 1000 interposer wires of various wire

40 lengths in [100 m, 1000 m] ,
30 among which three are faulty.
No. of occu

20
10
0
0 0.05 0.1 0.15 0.2 0.25
Tdrift (ns)
50
No. of occurreences

100um IW 550um IW 1000um IW

40 1K Delay Fault 1K Delay Fault 1K Delay Fault
30 at micro bump at micro bump at micro bump
20
10
0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
Normalized Tdrift (%)
44

22
 Fault Detection Capability
(For Resistive Open Faults)

MDRopen: Minimum Detectable Open Fault Resistance 245 

This metric refers to the open fault resistance value beyond which
the
h proposed d test method
h d can detect
d the
h fault
f l successfully
f ll based
b d
on the outlier analysis using 3 rule.

Detectable Extra-RC: (MDRopen) * (Cdownstream) 50.7 ps

MDRopen
Di
Driver R
Receiver
i
rmb r r r r r r r r r rmb

A Y WO
c c c c c c c c c c

Cdownstream
45

Resistive Open Fault Detection Capability

A resistive open fault occurring at the micro-bump of the

driver side of a 1000um long interposer wire.

MDRopen
Pseudo Detectable
(Min. Detectable Open
Chip Conditions Extra‐RC
Fault Resistance)
#1 (FF & ‐10% RC) 245  50.7 ps
#2 (FF) 76  17.5 ps
#3 (SS) 113  26.0 ps
#4 (SS
( & +10%
% RC)) 78  19.7 ps
Average 145  31.4 ps

46

23
 Process Drift from Simulation Model

50
FF-corner
45
40 SS-corner
# of occurrences

35 FF-corner &
- 10% {RIW & CIW} SS-corner &

Simulation Model
30
+ 10% {RIW & CIW}
25
20
15
10
5
0
-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40
Normalized T drift (%)

47

Fault-Free IW-Delays vs. T

for Various Pseudo Chip Conditions

Implication: Regression mode derived by TT corner

Is applicable under process variations.
05
0.5
Average Error: 7.9 ps
Maximum Error: 30.9 ps
0.4
IIW‐Delay (ns)

0.3

0.2 ╳ SS‐corner & +10% {RIW , CIW}

▲ SS‐corner
▓ TT‐corner
TT corner
0.1 ◆ FF‐corner
┼ FF‐corner & ‐10% {RIW , CIW}

0
0 0.1 0.2 0.3 0.4
T (ns)
48

24
 Summary of VOT-Based Oscillation Test

The interposer needs to be tested alone and thoroughly.

And also, when a 2.5-D IC fails,
We know if the interposer should be responsible.
responsible

Test Time Layout of an RO

11 ms for 1024 wires ~55%

413 ms for 32K wires Over boundary
Using 10MHz TCLK scan test

49

Conclusion

Criterion PV-test VOT-based oscillation test

Basic Concept Check if pulse will vanish Measure T
Fault Detection
Test threshold based Outlier analysis
Scheme
Area overhead 55.5% over IEEE-1149.1 55.7% over IEEE-1149.1
0.82 ms for 1024 wires 4.7 ms for 1024 wires
Test time
26.21 ms for 32K wires 177 ms for 32K wires
No post-processing
Delay characterization
Other benefits On the spot diagnosis
On-the-spot
P
Process tracking
ki
Easier self-repair

Outlier analysis: A measurement sample that significantly deviates away from

the entire population indicates a fault

50

25
 國立清華大學電機系

EE-6250
超大型積體電路測試
VLSI Testing

Chapter 11
Logic Diagnosis

Outline

 Introduction
 Combinational Logic Diagnosis
 Scan Chain Diagnosis
 Logic BIST Diagnosis
 Conclusion

Ch11-2

1
 What would you do when chips fail?
 Is it due to design bugs?
 If most chip fails with the same syndrome when
running an application
 I it
Is i due
d to parametric
i yield
i ld loss?
l ?
 Timing-related failure?
– Insufficient silicon speed?
 Noise-induced failure?
– supply noise, cross-talk, leakage, etc.?
 Lack of manufacturability?
– inappropriate layout?
 Is it due to random defects?
 Via misalignment, Via/Contact void, Mouse bite,
 Unintentional short/open wires, etc.

Ch11-3

Problem: Fault Diagnosis

This chapter focuses more on diagnosis of defects or faults, not design bugs

Circuit expected response

Under
Diagnosis
test patterns (CUD)
= not equal !

faulty response

a chip with defects inside

Question: Where are the fault locations ?

Ch11-4

2
 Diagnosis For Yield Improvement

Golden
Reference
Model Physical Failure Analysis
Scanning Electronic Microscope (SEM)
Focused Ion Beam (FOB)

Via void
Mouse bite, etc.
Logic Diagnosis
Defect Mechanisms

A Set Of Tune the Manufacturing

Potential Process or Design
Defect Locations for Yield Improvement

Ch11-5

Quality Metrics of Diagnosis

 Success rate
 The percentage of hitting at least one defect in the physical failure
analysis
 This is the ultimate goal of failure analysis
 Di
Diagnostic
ti resolution
l ti
 Total number of fault candidates reported by a tool
 The perfect diagnostic resolution is 1
 Though perfect resolution does not necessarily imply high hit rate
 First-hit index
 Used for a tool that reports a ranked list of candidates
 Refers to the index of the first candidate in the ranked list that turns
outt to
t be
b a true
t defect
d f t site
it
 Smaller first-hit index indicates higher accuracy
 Top-10 hit
 Used when there are multiple defects in the failing chip
 The number of true defects in the top 10 candidates

Ch11-6

3
 Challenge

Do whatever you want,

but give me that damn
bug(s) in less than 5
candidates.

failure analysis people

under time-to-market pressure

Ch11-7

Supporting Circuitry
Supporting Circuitry:
Makes Logic’s inputs controllable and outputs observable

ff
MUX

Test input
Logic
op_mode

memory
ff ff
Logic shift
register Scan out

Logic Logic

Ch11-8

4
 Design For Diagnosis

Complexity Original
Of Design
Di
Diagnosis
i
interface circuitry

Separated
Logic &
Memory
Scan-chain

Logic Design
With Full-Scan

More Supporting Circuitry

Ch11-9

Possible Assumptions Used in Diagnosis

 Stuck-At Fault Model Assumption
 The defect behaves like a stuck-at fault
 Single Fault Assumption
 Only one fault affecting any faulty output
 Logical Fault Assumption
 A fault manifests itself as a logical error
 Full-Scan Assumption
 The chip under diagnosis has to be full-scanned

Note: A diagnosis approach less dependent on the fault assumptions

is more capable of dealing with practical situations.

Ch11-10

5
 Examples of Faults
 Node Fault  Short Fault (Bridging)
VDD


A 


bridging

C Most diagnosis algorithms performs

B A at the gate level, trying to identify the
troubling signals or cells

GND

Ch11-11

Byzantine Open Fault

 Definition of Byzantine Fault:
 A fault that causes an ambiguous voltage level

‘1’ ‘1’
G2
 ~ 2.5 v
pseudo ‘1’
G1
open fault pseudo ‘0’
‘0’
‘1’ G3

Ch11-12

6
 A Byzantine Node Type
VDD Truth Table

C driver to ‘1’ A B C Z Zf
0 0 0 1 1
B 0 0 1 0 0

Z 0 1 0 1 1
0 1 1 0 0
A faulty 1 0 0 1 ~0
bridging C min-term
1 0 1 0 0
B
1 1 0 0 0
The faulty output 1 1 1 0 0
driver to ‘0’ could be ambiguous
GND

Ch11-13

Fault Classification

Fault in Logic IC

affects affects
functionality timing

Functional Fault Delay Fault

Node Fault
Gate-Delay Path-Delay
Open Fault
Fault Fault
Short Fault
Byzantine Fault

Ch11-14

7
 Outline

 Introduction
 Combinational Logic Diagnosis
 Cause-Effect Analysis
 Effect-Cause Analysis
 Chip-Level Strategy
 Diagnostic Test Pattern Generation
 Scan Chain Diagnosis
 Logic BIST Diagnosis
 Conclusion

Ch11-15

Terminology
 Device Under Diagnosis (DUD): The Failing Chip
 Circuit Under Diagnosis (CUD): The Circuit Model
 Failing
g Input
p Vector: Causes Mismatches
Failing chip

input
vector x mismatched PO
v o matched
t h d PO
o matched PO
o matched PO
x mismatched PO

Gate-level CUD

Ch11-16

8
 Cause--Effect Analysis
Cause

 Fault dictionary (pre-analysis of all causes)

 Records test response of every fault under the applied
test set
 Built by intensive fault simulation process
 A chip is diagnosed (effect matching)
 By matching up the failing syndromes observed at the
tester with the pre-stored fault dictionary

Ch11-17

Fault Dictionary Example

A diagnosis session:
a g traverse from a path from root to a leaf
b Circuit under
c Diagnosis {f1, f2, f3, f4, f5}

output=0 output=1
(a) Circuit under diagnosis v1

Test vectors in terms of (a, b, c) {f1, f4, f5} {f2, f3}

Circuits
v1 v2 v3 v4 v5 0 1 0 1
v2 v2
fault-free 0 0 0 0 1
f1 0 1 1 1 1 f4 {f1, f5} f3 f2
f2 1 1 1 0 1 0 1
f3 1 0 0 1 1 v4
f4 0 0 1 0 0 f5 f1
f5 0 1 1 0 1
(c) Diagnostic tree
(b) Full-response dictionary

Ch11-18

9
 Fault Dictionary Reduction – P&R
(a) Full-response table
Output Response (z1, z2)
Fault t1 t2 t3 t4
(c) P&R compression dictionary
f1 10 10 11 10
f2 00 00 11 00 Pass-fail + Extra outputs
f3 00 00 00 00 Fault
ID t1 t2 t3 t4
f4 01 00 00 01
f5 01 00 01 01 f1 1 1 1 0 1 1
f6 01 00 01 01 f2 1 0 0 0 1 1
f7 10 00 10 00 f3 1 0 0 1 0 1
f8 11 11 11 11 f4 1 0 0 1 0 0
Pass (0) or Fail (1) f5 1 0 0 1 1 0
Fault
t1 t2 t3 t4 f6 1 0 0 1 1 0
f1 1 1 0 1 f7 1 1 0 1 0 1
f2 1 0 0 1 f8 0 1 1 0 1 1
f3 1 0 1 1
f4 1 0 1 0
f5 1 0 1 0
f6 1 0 1 0 Response of z1 Response of z2
f7 1 0 1 1
f8 0 1 0 1
(b) Pass-fail dictionary
Ch11-19

Detection Fault Dictionary

(a) Full-response table
Output Response (z1, z2)
Fault
ID t1 t2 t3 t4
failing output vectors
f1 10 10 11 10
f2 00 00 11 00
f3 00 00 00 00 (c) Detection dictionary
f4 01 00 00 01
f5 01 00 01 01 Fault Detection information
f6 01 00 01 01 ID (Test ID : Output Vector)
f7 10 00 10 00 f1 t1:10 t2:10 t4:10;
f8 11 11 11 11 f2 t1:00 t4:00;
Pass (1) or Fail (0) f3 t1:00 t3:00 t4:00;
Fault f4 t1:01 t3:00;
ID t1 t2 t3 t4
f5 t1:01 t3:01;
f1 1 1 0 1 f6 t1:01 t3:01;
f2 1 0 0 1 f7 t1:10 t3:10 t4:00;
f3 1 0 1 1 f8 t2:10 t4:11;
f4 1 0 1 0
f5 1 0 1 0
f6 1 0 1 0
(b) Pass-fail dictionary
f7 1 0 1 1
f8 0 1 0 1 Ch11-20

10
 Outline

 Introduction
 Combinational Logic Diagnosis
 Cause-Effect Analysis
 Effect-Cause Analysis
 Chip-Level Strategy
 Diagnostic Test Pattern Generation
 Scan Chain Diagnosis
 Logic BIST Diagnosis
 Conclusion

Ch11-21

Terminology: Mismatched Output

Effect-cause analysis does not build fault dictionary
It predicts fault locations by analyzing CUD from mismatch PO’s

failing chip
0 failing PO
0
0
0
0 failing PO
input
vector 1 mismatched PO
v 0
0
0
CUD 1 mismatched PO

Ch11-22

11
Structural Pruning – Intersection or Union?

z2 z2
primary
inputs z3 z3

CUD Fault candidate set

(a) Cone intersection.

z1 z1

z2 z2
primary
inputs z3 z3

CUD Fault candidate set

(b) Cone union when there are multiple faults.
Ch11-23

Backtrace Algorithm
 Trace back from each mismatched PO
 To find out suspicious faulty locations
 Functional Pruning
 During the traceback, some signals can be
disqualified from the fault candidate set based
on their signal values.
 Rules
 (1) At a controlling case (i.e., 0 for a NAND
gate): Its fanin signals with non-controlling
values (i.e., 1) are excluded from the candidate
set.
 (2) At a non-controlling case (i.e., 1 for a NAND
gate): Every fanin signal remains in the
candidate set.
Ch11-24

12
Backtrace Example

All suspicious fault locations are marked in red.

0 Target
b 1 mismatched
1 output
e
0 1
0
c
1
1 f
a
1
d 1
0

Ch11-25

Terminology – Injection
An injection at a signal f flips its current value
which could create value-change events downstream.

x f = ‘0’ x
f = ‘1’ o o
o o
v x v xo?
x x
O: correct output A mismatched output
X: failing output could be fixed by the injection!

Ch11-26

13
 Terminology – Curable Output
 Diagnosis Criterion
 A signal is more suspicious if it has more curable outputs

x f = ‘0’ x
f = ‘1’ o o
o o
v x v o cured
x o cured

O: correct output An injection at f fixes two mismatched outputs

X: failing output  Thus, f has two curable outputs !

Ch11-27

Terminology – Curable Vectors

v is a curable vector by f
 because an injection at f exists such that
it cures all mismatches without creating new one
Curable vector is a stronger
g diagnosis
g indicator than curable output
p !

x f = ‘0’ o cured

f = ‘1’ o o
o o
v v o
x cured
x o cured

Ch11-28

14
Example of Curable Vector
x1 = 0
x2 = 1 0 failing
x3 = 1 1
x4 = 1
(a) Failing Chip

x1 0
1

1 0 cured
f
x2 1 0 1
0
1
1
1
x3 1
0
x4 1

(b) Circuit Under Diagnosis

Ch11-29

Why Curable Vector ?

 Information theory
 A less probable event contains more information
 Curable output is an easy-to-satisfy criterion, high aliasing
 Curable
C bl vector
t isi a hard-to-satisfy
h dt ti f criterion,
it i low
l aliasing
li i

 Not all failing input vectors are equal !

 Niche input vector

– Is an failing input vector that activates only one fault
– Likely to be a curable vector of certain signals
– Few, but tells more about the real fault locations

Ch11-30

15
 Inject--and
Inject and--Evaluate Paradigm
design failing chip
input vectors
model response

Calculate the no. of “curable vectors” of each signal

Calculate the no. of “curable outputs” of each signal

Sorting Sort the signals by the no. of “correctable vectors”,

Criteria If tied, sort by
y the no. of “correctable outputs”
p

ranking of each signal’s possibility

of being a defect location

Ch11-31

Detailed Computation –
Inject--and
Inject and--Evaluate Paradigm
CUD failing failing chip
netlist test vectors syndromes

Set initial candidate set by structural pruning

for each failing input vector v {

Step 1: perform logic simulation;
Step 2: for each candidate signal f {
Step 2.1: flip the value at f ; /* injection */
Step 2.2: run event-driven fault simulation; /*evaluation */
Step 2.3: calculate certain metrics /* ranking */
}
}
Sort the candidate signals by the calculated metrics;

a list of ranked candidate signals

Ch11-32

16
 Reward--and
Reward and--Penalty Heuristic
Rank1: curable vector count
Rank2 = (curable output count – 0.5 * new mismatched output count)

x1 =0
x2 =1 0 failing
x3 =1 1 passing
x4 =0
(a) Failing Chip.

x1 0
1

1 0
cured
f
x2 1 0
0 1
1
new
10
1 mismatch
x3 1
1
x4 0
(b) Circuit Under Diagnosis.
Ch11-33

Targeting Bridging Faults

Even in a realistic bridging fault, there is only one victim at any time.
This victim will expose his location by owning some curable vectors.

A w1
B
bridging
C
D w2

Ch11-34

17
SLAT Paradigm
Ref: SLAT (Single Location At a Time) paradigm [Bartenstein 2001]
Note: A SLAT vector is a curable vector

failing failing chip

CUD
input vectors response

Phase 1: Finding SLAT (Single Location at A Time) vectors:

(1) Fault simulation, (2) Output matching

Phase 2: Finding valid fault multiplets

(1) Finding single-fix candidates
(2) Finding double-fix candidates
(3) Finding triple-fix candidates, etc.

A number of valid fault multiplets

Ch11-35

Example: SLAT Paradigm

Failing Signals in the CUD
Input
Vectors f1 f2 f3 f4 f5 f6 f7
v1 * *
v2 * * *
v3 * * *
v4 * *
v5 * *
v6 * *
v7 * *
v8 * *
v9 * *
v10 * *

A mark * means the corresponding vector is (f3 and f5)

a SLAT vector of the corresponding signal. is a valid fault multiplet

Ch11-36

18
Outline

 Introduction
 Combinational Logic Diagnosis
 Cause-Effect Analysis
 Effect-Cause Analysis
 Chip-Level Strategy
 Diagnostic Test Pattern Generation
 Scan Chain Diagnosis
g
 Logic BIST Diagnosis
 Conclusion

Ch11-37

Structurally Dependent and Independent

Faults
fault f1 z1 mismatched output

fault f2 z2 mismatched output

inputs

z3 mismatched output

f lt f3
fault

Fault f1 is an independent fault.

Faults f2 and f3 are dependent faults.
Ch11-38

19
 Dependency Graph
Direct divide-and-Conquer
does not work well !
fault z1
f1

z2 dependency graph
z1
fault
f2 z3
z2 z3

one connected component

Two independent faults, f1 and f2, lead to one diagnosis block.

Ch11-39

Main Strategy:
Strategy:
Detach--Divide
Detach Divide--and
and--then
then--Conquer
 Phase 1: Isolate Independent Faults
 Search for prime candidates
 Use word-level information
 Phase 2: Locate Dependent Faults As Well
 Perform partitioning
 Aim
Ai att fifinding
di one ffaultlt iin each
h bl
block
k

Ch11-40

20
 Prime Candidates

A signal f is a prime candidate if

(1) All failing input vectors are partially curable by f
(2) Curable-Output-Set(f) is not covered by any other’s

f1 syndrome
f3 set 1

f1 & f2
are p
prime !
f2 syndrome
set 2

Ch11-41

Fake Prime Candidates

 Structurally Independent Faults
 are often prime candidates
 Fake Prime Candidates
 are prime candidates that are NOT really faults - aliasing

f1 f3
Example: Dependent Double Faults f1 & f2
May create fake prime candidates {f1, f2, f3}. f4

f2
f5

Ch11-42

21
 Word--Level Registers and Outputs
Word
Signals in a design are often defined in words.
This property can be used to differentiate fake prime candidates from the real ones.

Word-Level Output: O1
Word-Level Registers: R1, R2, State
module design( O1, ...)
output[31:0] O1;
reg[31:0] R1, R2;
reg[5:0] State
...
endmodule

Ch11-43

Word--Level Prime Candidates

Word
Note: Z and R are two word-level output groups.

f1
f3 Z f1 f3 Z

f4
f2 f2
f5
R R

Assumed original prime candidates: {f3, f4 , f5}

Original prime candidates: {f1, f2}
{f4 , f5} will be identified as fake
Word-level prime candidates {f1, f2}
 Final Word-level prime candidates {f3}

Ch11-44

22
Efficiency of Using Word-
Word-Level Info.
 Without word-level Information
 2.4 real faults out of 72.3 candidates
 With word-level Information
 1.23 real faults out of 3.65 candidates
After Filtering
# of candidates Original
Filtering Ratio
Prime
Candidates
2 375
2.375 1 23
1.23 48 2 %
48.2
Fake Prime
Candidates
69.96 2.42 96.5 %

Ch11-45

Overall Flow
failing design failing chip
input vectors model response

Phase 1:
(1) Find Word-Level Prime Candidates

Phase 2:
(1) Remove explained outputs and their fanin cones
(2) Partition the rest model into blocks
(3) P
Perform
f di
diagnosisi ffor each
h bl
block
k

Rank candidates produced

in phases 1 & 2

Ch11-46

23
 Grouping Using Dependency Graph
An example with five faults
One of them is identified as the prime candidate

X a b
a
X b
X c c
X c
d
prime
X e
e
candidates z y
X y
X z
X f i f
X g j
X h
g
X i k h
X j
X k

Ch11-47

Removed Explained Faulty Outputs

X a X a
X b X b
X c X c
X d X d
X e X e
prime
candidates syndromes
X y at y and z
X z are fully
explained
X f X f
X g X g
X h X h
X i X i
X j X j
X k X k

Ch11-48

24
Grouping Example

X a b
a
X b
X c c
X d d
X e e

i f
X f j
X g
X h g
k h
X i
X j
X k Two independent diagnosis blocks
Are successfully derived!

Ch11-49

Summary
 Strategy
 (1) Search For Word-Level Prime Candidates
 (2) Identify Independent Faults First
 (3) Locate Dependent Faults As Well
 Effectiveness
 identify 2.98 faults in 5 signal inspections
 find 3.8 faults in 10 signal inspections

Ch11-50

25
 Diagnostic Test Pattern Generation
a1 DTPG helps to increase diagnostic resolution
e
a
b d d1 g
Model for differentiating vector generation
c d2
d1 stuck-at 1
a2 f
a e
⊕
fault-free circuit b d g
c d2 x
a2 f z/0

d2 stuck-at 0 ⊕

e
d d1 g

a2 f
Ch11-51

Outline

 Introduction
 Combinational Logic Diagnosis
 Scan Chain Diagnosis
 Preliminaries
 Hardware-Assisted Method
 Signal-Profiling Based Method
 Logic BIST Diagnosis
 Conclusion

Ch11-52

26
 Scan Test and Diagnosis

Flush test of scan chains

(pumping random patterns and checking response)

Pass Pass or Fail? Fail

Find failing scan chain(s)

Test Combinational Logic Classify fault types

Scan Chain Diagnosis

Ch11-53

Commonly Used Fault Types in Scan Chains

Scan Chain Faults

Functional Faults Timingg Faults

Setup-Time Hold-Time
Stuck-at
Violation Fault Violation Fault
Bridging

Slow-To-Rise Slow-To-Fall
Fault Fault

Each fault could be permanent or intermittent.

Ch11-54

27
 A Stuck-
Stuck-At Fault In the Chain
Effect: A killer of the scan-test sequence

Combinational Logic
input output
pins pins

scan-input scan-output
(SI) (SO)
MU

MU

M
MUX
11010100 D Q D Q D Q 00000000
UX

UX

s-a-0 ?
All-0 syndrome
scan-enable
clock

Ch11-55

A Realistic Bridging Fault Model



bridging
Scan Scan
MU

MU

input output
MU

MU

D Q
X

(SI) F1 F2 F3 F4 (SO)
clock

(a) Bridging between a flip-flop and a logic cell.


If(==1) faulty =  faulty

else faulty = F2
F2

(b) Our bridging fault model.

Ch11-56

28
 Potential Hold-
Hold-Time Fault?
(Negative Edge-Triggered Flip-Flop)

Y
D Q
Master Slave
normal
CLK = low
Y
D Q
shut down
Master Slave too slowly
Y
D Q
faulty
CLK = high Master Slave

CLK = low

Ch11-57

Example: Faulty Syndrome of a Scan Chain

A scan chain

SI SO
(scan input pin) (scan output pin)

A faulty flip-flop
Fault Type Scan-In Pattern Observed Syndrome
Stuck-at-0 1100110011001100 0000000000000000
Stuck-at-1 1100110011001100 1111111111111111
Slow-to-Rise 1100110011001100 1000100010001000
Sl
Slow-to-Fall
t F ll 1100110011001100 1101110111011100

The rightmost bit goes into the scan first

The rightmost bit gets out of the scan first
A underlined bit in the observed image is failing.

Ch11-58

29
 Augmentation of a Flip
Flip--Flop for Easy
Diagnosis
(From logic)
MUX D Q
(from scan chain) DFF

SC
(a) A normal scan flip-flop.

(From logic)
MUX D Q
((from scan chain))
DFF

Invert SC

(b) A modified scan flip-flop for easy inversion.

Ch11-59

Fault Location via Inversion Operation

A scan chain

SI SO

Stuck-at-0

SI-to-fault Fault-to-SO

(1) Original bitstream pattern = (1111111111111111)

(2) After scan-in: snapshot image = (1111000000000000)
(3) After inversion: snapshot image = (0000011111111111)
(4) After scan-out: observed image = (0000011111111111)

The fault location is at the edge between 0’s and 1’s

Ch11-60

30
 Scan Chain Diagnosis Flow

Circuit Diagnostic
Diagnostic
Under Test Sequence
Test Sequences
q
Di
Diagnosis
i G
Generator
t

Test Application
Fault-Free
Observed Images

Signal Profiling
Di
Diagnosis
i Based Observed
Obser ed Images
Diagnosis Program Of Failing Chip

Faulty FF’s
location

Definition: Snapshot Image

Def: A snapshot image is the combination of flip-flop values
at certain time instance

Mission Logic
input output
pins pins

Scan Scan
MUX

MUX

MUX

MUX

D
input
p 0
Q
1 x 0 1
output
p
X

s-a-0
(SI) F1 F2 F3 F4 (SO)
clock

Snapshot image: {(F1, F2, F3, F4) | (0, 1, 0, 1)}

Ch11-62

31
 Definition: Observed Image
Def: An observed image is the scanned-out version of
a snapshot image.

Mi i Logic
Mission L i
input output
pins pins

Scan Scan
MUX

MUX

MUX

MUX
input D
0
Q
1 x 0 1 output
s-a-0
(SI))
(S F1 F2 F3 F4 (SO)
clock

Snapshot image: {(F1, F2, F3, F4) | (0, 1, 0, 1)}

Observed image: {(F1, F2, F3, F4) | (0, 0, 0, 1)}

Ch11-63

Modified Inject-
Inject-and
and--Evaluate Paradigm
Step 2: Capture the response to FF’s

Step 1: Scan-in an ATPG pattern core

logic

core
1 0 x 0 0
logic
1011 x
x x x x

core
llogic
i
A stuck-at-0 fault is assumed 0010
at the output of the 2nd FF from SI 0 1 x 1 0

Step 3: Scan-out and compare

Ch11-64

32
 Test Application: Run-
Run-and
and--Scan
Step 1: Apply a test sequence from PI’s
 Setting up a snapshot image at FF’s

Test core
logic
Sequence
S-A-0 core
x logic
0 1 1 0
Less distorted image S-A-0
x 0010
0 1 1 0
SO
up-stream part
will be distorted
Step 2: Scan-out an observed image

The fault location is embedded in the observed image

Ch11-65

Signal Profiling
A profile is the distribution of certain statistics of the flip-flops.

Failing chip
core faulty flip-flop
logic Scan
x Shifting
0.41 0.51 0.61 0.41 0 0 0.65 0.35
Test
perturbed image
Sequences
Up-stream Down-stream
core
different similar
logic

0.4 0.5 0.6 0.4 0.4 0.5 0.6 0.4

fault-free image
Fault-free profile
Comparing failing profile with the fault-free profile
Fault-free model
 Could reveal the fault location

Ch11-66

33
 Profile Analysis

Fault-free images Failing images

Collected from tester
(say 100 of them) (say 100 of them)

Derive the fault-free profile

Derive the failing profile

A difference image
Derive the difference profile = fault-free image ⊕ failing image

Perform filtering on the difference profile

report
Perform edge detection to derive ranking profile a ranked list
of fault locations

Ch11-67

Example: Filtering & Edge Detection

(%)

Profiling difference
Difference Profile
equency

0.8

0.6
SP(%)

0.4
Signal-1 Fre

0.2

0
1 12 23 34 45 56 67 78 89 100 111 122 133 144 155
DFF Index

Filtering & Edge Detection

0.8
Filtered
Smooth
Difference
Profile Profile Ranking (orProfile
Ranking suspicion) Profile
0.6
0.4
0.2
0
1

13

25

37

49

61

73

85

97

109

121

133

145

157

-0.2
-0.4
-0.6
-0.8

Scan Input  FFDFF Index  Scan Output

index

34
Computation of Average-
Average-Sum Filtering

 (Average-sum filtering) Assume that the difference

profile is given and denoted as D[i], where i is the index
of a flip
flip-flop.
flop. We use the following formula to compute
a smoothed difference profile, SD[i]:

SD[i] = 0.2*(D[i-2]+ D[i-1]+ D[i]+ D[i+1]+ D[i+2])

Ch11-69

Computation of Edge Detection

 The true location of the faulty flip-flop is likely to be the left-

boundary of the transition region in the difference profile. To detect
this boundary, we can use a simply edge detection formula defined
b l
below.
 (Edge detection) On the smoothed difference profile SD[i], the
following formula can be used to compute the faulty frequency of
each flip-flop as a suspicious profile.
 SD [i ]  SD [i  3] 
 SD [i ]  SD [i  2 ] 
 
 SD [i ]  SD [i  1] 
suspicion [i ]  [  1,  1,  1,1,1,1]  
SD [i ]  SD [i  1] 
 
 SD [i ]  SD [i  2 ] 
 SD [i ]  SD [i  3] 

Ch11-70

35
Summary of Scan Chain Diagnosis

 Hardware Assisted
 Extra logic on the scan chain
 Good for stuck-at fault
 Fa lt Simulation
Fault Sim lation Based
 To find a faulty circuit matching the syndromes [Kundu 1993]
[Cheney 2000] [Stanley 2000]
 Tightening heuristic  upper & lower bound [Guo 2001][Y.
Huang 2005]
 Use single-excitation pattern for better resolution [Li 2005]
 Profiling-Based Method
 Locate the fault directly from the difference profiles obtained
b run-and-scan
by d t t
test
 Applicable to bridging faults
 Use signal processing techniques such as filtering and edge
detection

Ch11-71

Outline

 Introduction
 Combinational Logic Diagnosis
 Scan Chain Diagnosis
 Logic BIST Diagnosis
 Overview
 Interval-Based Method
 Masking-Based Method
 Conclusion

Ch11-72

36
A Logic BIST Architecture
PRPG (Pseudo-Random Pattern Generator)

Core
Logic

MISR (Multiple-Input Signal Analyzer) scan out

(as the signature)
All flip-flops are assumed to be observable
through scan chains.

Ch11-73

Diagnosis for BISTed Logic

 Diagnosis in a BIST environment requires

 determining from compacted output responses
which test vectors have produced a faulty response
(time information)
 determining from compacted output responses
which scan cells have captured errors (space
information)
 The true fault location inside the logic
g
 Can then be inferred from the above space and time
information using previously discussed
combinational logic diagnosis

Ch11-74

37
 Binary Search To Locate 1st Failing Vector
Time (or test vector index)

S
Space 3rd
(or scan cell 2nd BIST session length:
index) 147423
 First failing at vector #4
1st BIST session

Ch11-75

Interval Unloading-
Unloading-Based Diagnosis
Time (or test vector index)

Space
(or scan cell
index)

failing failing
interval interval
Interval index 1 2 3 4 5 6 7

A signature is scanned out to the tester

for comparison at the end of each interval

Ch11-76

38
 Deterministic Masking-
Masking-Based Diagnosis
PRPG (Pseudo-Random Pattern Generator) Scan chain index (X)

1 2 3 4 5 6 7 8

Scan slice indeex

6
5
Core 4
Logic 3
2
1

Scan slice Cell partition:

X = {3,4} (chain set)
Y = 2 (lower bound)
MISR (Multiple-Input Signal Analyzer) Z = 6 (upper bound)

(a) STUMP-based BIST architecture (b) Scan cell matrix

Ch11-77

Circuitry to Support Deterministic Masking

PRPG (Pseudo-Random Pattern Generator)

Core
Logic

0
0
1
1
0 ≧ ≦
0
0
0 0 1 0 1 1 0
X Y Z
Counter
MISR (Multiple-Input Signal Analyzer)

Ch11-78

39
 A Search for Scan Cells Capturing Errors
PRPG (Pseudo-Random Pattern Generator)
Scan cells
Core Capturing errors
Logic

MISR (Multiple-Input Signature Register)

(a) Scan cells capturing errors in the fourth scan chain

(Y, Z)=(1, 7)

(Y, Z)=(1, 4) (Y, Z)=(5, 7)

(Y, Z)=(1, 2) (Y, Z)=(3, 4) (Y, Z)=(5, 6) (Y, Z)=(7, 7)

(Y, Z)=(3, 3) (Y, Z)=(4, 4) 9 BIST sessions

(b) The search tree
Ch11-79

Conclusions
 Logic diagnosis for combinational logic
 Has been mature
 Good for not just stuck-at faults, but also bridging faults
 Scan chain diagnosis
 Making good progress …
 Fault-simulation-based, or signal-profiling based
 Diagnosis of scan-based logic BIST
 Hardware support is often required
 Interval-unloading, or masking-based
 Future challenges
 Performance (speed) debug
 Diagnosis for logic with on-chip test compression and
decompression
 Diagnosis for parametric yield loss due to nanometer effects

Ch11-80

40