7.

Design for Testability 7-1

Chapter 7 Design for Testability

Definition 1
1) A fault is testable if there exists a well-specified procedure to expose it, which
is implementable with a reasonable cost using current technologies. 2) A circuit is
testable with respect to a fault set when each and every fault in this set is testable.
3) Design for testability (DFT) is a class of design methodologies which put con-
straints on the design process to make test generation and diagnosis easier.

Ad Hoc DFT Guidelines

☞ No single methodology solves all VLSI testing problems; no single DFT

technique is effective for all kinds of circuits.
☞ Two classes of DFT techniques: ad hoc techniques and structured (system-
atic) techniques.

1. Partition large circuits into smaller subcircuits to reduce test generation cost
(using MUXes and/or scan chains).
T1 T2
S Mode T1 T2
1
M Normal 0 0
0
Test C1 0 1
C1 C2 Test C2 1 0
S
1
M
0

0 1 1 0
M S S M

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-2

2. Employ test points to enhance controllability & observability (testpoints:

control points (CPs) & observation points (OPs)).

OP
C1 .
.
. C2 .
.
. C3
M
CP1 CP2 CP3 CP4

3. Design circuits to be easily initializable.

4. Disable internal one-shots (monostables) during test (due to difficulty for
tester to remain synchronized with UUT).
5. Disable internal oscillators and clocks during test.
6. Provide logic to break global feedback paths.
7. Partition large counters into smaller ones.
8. Avoid the use of redundant logic.
9. Keep analog and digital circuits physically apart.
10. Avoid the use of asynchronous logic.
11. Avoid diagnostic ambiguity groups such as wired-OR/wired-AND junctions
and high-fanout nodes.
12. Consider tester requirements (pin limitation, tristating, etc.).

☞ High fault coverage not guaranteed.

☞ Manual test generation still required.
☞ Design iterations also required.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-3

 Syndrome-Testable Design [1, 2]

Definition 2
The syndrome of a boolean function f is S (f )  k2(fn ) , where k is the number of
1s (minterms) in f and n is the number of independent input variables.

Exhaustive Syndrome
UUT Comparator
patterns register Go/No-go
(Counter)
Reference syndrome
Figure 1: A typical syndrome testing set-up.

✯ 0  S (f )  1.
✯ A circuit is syndrome testable iff 8 fault , S (f ) 6= S (f ).

Gate ANDn ORn XORn NOT

S 1 1 1 1 1
2n 2n 2 2

Consider a circuit having 2 blocks, f and g , with unshared inputs:

O/p gate OR AND XOR NAND NOR
S Sf + Sg Sf Sg Sf Sg Sf + Sg 2Sf Sg 1 Sf Sg 1 Sf Sg + Sf S g

Exercise 1
Show that for blocks with shared inputs (circuits having reconvergent fanouts):

S (f + g ) = Sf + Sg S (fg )
S (fg ) = Sf + Sg + S (fg) 1
S (f  g ) =  )
S (f g) + S (fg

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-4

S1

S2 S

S4

S3

Example 1
Calculate the syndrome of the following circuit.

1 3
S1 = 1 =
4 4
1 3
S2 = 1 =
4 4
1
S3 =
8
S4 = 1 (S2 + S3 S2S3 ) = 7=32

) S = S1S4 = 21=128. 2
☞ Syndrome is a property of function, not of implementation.
Definition 3
A logic function is unate in a variable xi if it can be represented as an sop or
pos expression in which the variable xi appears either only in an uncomplemented
form or only in a complemented form.
Theorem 1
A 2-level irredundant circuit realizing a unate function in all its variables is syndrome-
testable.
Theorem 2
Any 2-level irredundant circuit can be made syndrome-testable by adding control
inputs to the AND gates.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-5

Example 2
Let f = xz + y z. Then S = 12 . If  z=0, then f = y. )S = 1
2
= S.
) Syndrome untestable.
Now add a control input c 3 f 0 = cxz + yz, where

1
c
when in normal operation mode
normal i/p when in test mode

S 0 = 83 , f 0 = y , and S 0 = 1
2
6= S 0. ) Syndrome testable. 2

Drawbacks:

✯ Only for combinational logic.

✯ Exhaustive: all patterns applied, and # of 1s recorded. Only applicable to
small circuits (larger circuits ) partition).
✯ Modification doubles test set size.

Scan Design Approaches

☞ They are effective for circuit partitioning.

☞ They provide controllability and observability of internal state variables for
testing.
☞ They turn the sequential test problem into a combinational one.
☞ Four Major Approaches:
✏ Shift-register modification [3];
✏ Scan path [4, 5];
✏ LSSD [6, 7];
✏ Random access [8].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-6

Shift-Register Modification (MUX Scan) [M. Williams & Angell, IEEE TC-
22(1), 1973]

☞ Invented at Stanford in 1973 by M. Williams & Angell.

☞ Later adopted by IBM—heavily used in IBM products.

X Combinational Z
Logic

y Y
State Vector

To make elements of state vector controllable and observable, we add:

① A TEST mode pin (T).

② A SCAN-IN pin (SI).
③ A SCAN-OUT pin (SO).
④ A MUX (switch) in front of each FF (M).

Test procedure:

① Switch to the shift-register mode and check the SR operation by shifting in

an alternating sequence of 1s and 0s, e.g., 00110 (functional test).
② Initialize the SR—load the first pattern.
③ Return to the normal mode and apply the test pattern.
④ Switch to the SR mode and shift out the final state while setting the starting
state for the next test. Go to ③.

☞ The SI pin may be a redefined input pin (using a MUX) in test mode.
☞ The SO pin may be a redefined output pin (using a MUX) in test mode.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-7

x C/L z

SI M FF M FF M FF SO
C
T

DI
L1 L2
D Q D Q
SI
T
C

Scan Path [Funatsu et al., DA Symp., 1975, & ITC, 1978]

☞ Invented by Kobayashi et al. in 1968, and reported by Funatsu et al. in 1975,

and adopted by NEC.
☞ Uses raceless D-FFs: each FF consists of 2 latches operating in master-slave
fashion, and has 2 clocks to select either SI or DI.
☞ Also called the Clock Scan approach.

C2
SI

DI DO
SO

C1
L1 L2
2-port raceless master-slave D FF

✯ Normal mode: C2 = 1 to block SI; C1 = 0 ! 1 to load DI.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-8

✯ SR (test) mode: C1 = 1 to block DI; C2 = 0 ! 1 to load SI.

Level-Sensitive Scan Design (LSSD) [Eichelberger & T. Williams, DAC, 1977,

& JDAVTC-2(2), 1978]

☞ By Eichelberger and T. Williams, 1977, 1978.

☞ Latch-based design used at IBM.
☞ Race- & hazard-free operation and testing: insensitive to rise time, fall time,
delay, etc.
☞ Faster than SR modification; lower hardware complexity.
☞ More complicated design rules.
☞ Uses 2 latches: one for normal operation and one for scan.
Definition 4
A logic circuit is level sensitive iff the steady state response to any allowed in-
put change is independent of the delays within the circuit. Also, the response is
independent of the order in which the inputs change.

Polarity-Hold Latch:
D C D +L
C
D 0 0 L
L +L
L C 0 1 L
1 0 0
1 1 1

☞ The correct change of the latch output (L) is not dependent on the rise/fall
time of C , but only on C being ‘1’ for a period of time  data propagation
and stabilization time.

Polarity-Hold Shift-Register Latch (SRL):

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
 7. Design for Testability 7-9

DI +L1 DI
C
L1 +L1
SI
C A

SI +L2 L2 +L2
B

A
B

✯ Normal mode: A = B = 0; C = 0 ! 1.
✯ SR (test) mode: C = 0; AB = 10 ! 01 to shift SI through L1 and L2.

☞ Polarity-hold, hazard-free, and level-sensitive.

☞ To be race-free, clocks C & B as well as A & B must be nonoverlapping.
☞ Avoids performance degradation introduced by the MUX in shift-register
modification.
☞ Can replace B with A + C , i.e., NOR(A; C ).

x C/L z x C/L z
C C
A A
SI L1 L1 L1 SO SI L1 L1 L1 SO
L2 L2 L2 L2 L2 L2
B B
double-latch LSSD single-latch LSSD

LSSD design rules:

① Internal storage elements must be polarity-hold latches.

② Latches can be controlled by 2 or more nonoverlapping clocks that satisfy:
❶ A latch X may feed the data port of another latch Y iff the clock that
sets the data into Y does not clock X .

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-10

❷ A latch X may gate a clock C to produce a gated clock Cg , which drives

another latch Y iff Cg , or any other clock Cg0 produced from Cg , does not
clock X .
③ There must exist a set of clock primary inputs from which the clock inputs to
all SRLs are controlled either through (1) single-clock distribution tree or (2)
logic that is gated by SRLs and/or nonclock primary inputs. In addition, the
following conditions must hold:
❶ All clock inputs to SRLs must be OFF when clock PIs are OFF.
❷ Any SRL clock input must be controlled from one or more clock PIs.
❸ No clock can be ANDed with either the true or the complement of an-
other clock.
④ Clock PIs cannot feed the data inputs to latches, either directly or through
combinational logic.
⑤ Every system latch must be part of an SRL; each SRL must be part of some
scan chain.
⑥ A scan state exists under the following conditions:
❶ Each SRL or scan-out PO is a function of only the preceding SRL or
scan-in PI in its scan chain during the scan operation.
❷ All clocks except the shift clocks are disabled at the SRL inputs.
❸ Any shift clock to an SRL can be turned ON or OFF by changing the
corresponding clock PI.

☞ A network that satisfies rules ①–④ is level-sensitive.

☞ Race-free operation is guaranteed by rules ②.❶ & ④.
☞ Rule ③ allows a tester to turn off system clocks and use the shift clocks to
force data into and out of the scan chain.
☞ Rules ⑤ & ⑥ are used to support scan.

✯ Advantages with LSSD:

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-11

✩ Correct operation independent of AC characteristics.

✩ Reduce FSM to C/L as far as testing is concerned.
✩ Eliminate hazards & races; simplifies test generation and fault simula-
tion.
✯ Problems with LSSD:
✩ Design rules imposed on designers—no freedom to vary from the overall
schemes, and higher design and hardware costs (4-20% more h/w & 4
extra pins).
✩ No asynchronous designs.
✩ Sequential routing of latches can introduce irregular structures.
✩ Faults changing combinational function to sequential may cause trouble,
e.g., bridging and CMOS stuck-open.
✩ Function to be tested has been changed into a quite different combina-
tional one, so specification language won’t be of any help.
✩ Slow test application; normal-speed testing is impossible.
✩ Not good for memory intensive designs.

Random Access [Ando, COMPCON, 1980]

☞ Uses addressable latches.

☞ Provides random access to FFs via multiplexing—address selection.
☞ Used by Fujitsu, Amdahl, & TI (developed by Fujitsu [Ando, 1980]).

✯ Advantages:
✩ Fast; minimal impact on normal path.
✩ Fast for testing—random access.
✩ Ability to ‘watch’ a node in normal operation mode (impossible with
LSSD).

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-12

DI
CK1
x C/L z
SI . +L
C
SI
CK2
L L L L Addr
addr SO
decoder
SO (C = CK1 & CK2)

✯ Disadvantages:
✩ Address decoder—and thus h/w overhead—is large.
✩ More pins added (* parallel address).
✩ No asynchronous circuits.

For all scan techniques:

 Test patterns are costly to compute.

 Test patterns must be stored externally.
 Responses must be stored and evaluated () large (non-portable) test fixture
and high cost).
 Therefore, there is a growing interest in built-in self-test (BIST).

Scan Cell Design

A complex scan/storage cell:

SO Z1
0 Mux D Q Q2 . D Q Q1 0 Mux . Z2
SI 1 S 1 S
T2 C2 C1 T1

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-13

☞ For use in sequential circuits that are time sensitive, such as asynchronous
circuits.

A typical scan cell:

C B
DI Q
DI Latch Q SO
MUX or SI
SI FF SO A

Functional Test for PLAs [Ostapko/Hong, TC 9/79; Smith, TC 11/79; Bose/Abraham,

DAC-82]

✯ Stuck-at & bridging faults can occur on decoder lines, bit lines, product lines,
and output lines.
✯ A functional-level fault model: in addition to stuck & bridging faults, we
should also consider crosspoint (contact) faults.
✯ For a PLA with i input lines, p product lines, and o output lines, there are
(2i + o)p possible single crosspoint faults, and 2(2i+o)p 1 possible multiple
crosspoint faults.

Crosspoint Faults:

① Growth fault—a product term can grow (cover more minterms) due to a miss-
ing contact in the AND array.
② Shrinkage fault—a product term can shrink due to an extra contact in the
AND array.
③ Disappearance fault—a product term can disappear from a function due to a
missing contact in the OR array.
④ Appearance fault—a product term from one function can spuriously appear
in another function due to an extra contact in the OR array.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-14

☞ Missing crosspoints are equivalent to some stuck-at faults, but extra contacts
cannot be modeled by stuck faults.
☞ To test whether a product term has grown, for example, minters which would
be covered by the growth of the term and which are not covered by any other
product term are chosen as test vectors.
☞ A complete xpt fault detection inherently covers most single stuck faults in
input decoders and output lines, as well as many shorts and a large proportion
of multiple faults [Cha 1978; Ostapko & Hong 1979; Smith 1979].
☞ Any complete single xpt fault test set covers 98% of all multiple xpt faults of
size 8 or less [Agarwal 1980].
☞ Any stuck-at fault or AND bridging fault is equivalent to a multiple xpt fault
[Min 1983].
☞ In general PLAs are not efficiently tested by random vectors due primarily to
the large number of xpts used in the AND array, i.e., the large fanins of the
AND gates, which are frequently 10 or larger. Let the fanin be n, then the
probability of detecting a missing xpt with a random pattern is no better than
2 n.

Semirandom Test Generation for PLAs (PLA/TG) [Eichelberger & Lindbloom,

IBM J. Res. and Dev., 1/1980]

✯ Direct matrix representation of the PLA without expansion into equivalent

logic.

. . . .
. . . .
. . .
. . . .
x1 x1 x2 x2 x3 x3 x4 x4 y1 y2

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-15

✯ Reduced fault assumptions where one stuck condition is modeled at each

personalized crosspoint in the AND and OR arrays (i.e., xpt stuck fault).
✯ Primitive patterns combined to produce a nearly optimum test set.
✯ Elimination of the need for conventional fault simulation.

Embryonic Tests:

① Test Type 1 (T1): All used xpts on a given product line are set to logic 1.
② Test Type 2 (T2): One selected used xpt on a given product line is set to 0;
the rest of the used xpts are set to 1.

☞ These 2 test types are the familiar embryonic patterns for detecting all stuck
faults of the AND gates.
☞ For these tests to be successful there must also exist a sensitized test path
through the OR array.

Path Sensitization:

Path sensitization normally is done in a deterministic manner that re-

sults in decision trees which can have relatively long program run time.
PLA/TG randomly assigns a set of PI values and then makes a check to
determine whether a path has been sensitized. If not, the process is re-
peated until all tests have been established or a max number of iterations
has been reached.

☞ The characteristic that the AND gates have large fanins renders the procedure
of combining random patterns with T1 and T2 tests effective for sensitizing
test paths through OR gates.
☞ A T1 test will test the input to at least one OR gate s-a-0, so it is necessary
to ensure that all OR gates fed by the same AND gate be sensitized for some
T1 test.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-16

☞ A T2 test will test the input to the AND gate s-a-1, so it is sufficient to sensi-
tize the path through any OR gate fed by the AND gate.

Combining Embryonic Tests:

➀ Specify and assign each T1 test to a unique test pattern.

➁ Specify each T2 test, one at a time, and try to combine it with one of the
test patterns. It will combine if no specific bit value is different from the
corresponding specified bit value in the test. If it will not combine with any
existing test pattern, then assign it to a new test pattern.

✯ Two or more T1 tests should not be combined, since they might both feed the
same OR gate and combining them would prevent the testing of their inputs
to this common OR gate.
✯ Combining a T2 test with a T1 test is acceptable, since the T2 test will usually
help sensitize the T1 test path, and the associated product term of the T2 test
will have a high probability of feeding at least one OR gate not fed by the T1
product term.
✯ Two or more T2 tests can usually be combined without causing any path
sensitization problem.

☞ The heuristic procedure may not work well for a small percentage of PLAs.
For example, if all AND gates have only one input and the OR gate has p
inputs, where p equals to the number of product lines. This PLA will not be
susceptible to random test path sensitization.

Special Closing Routine:

For the residual untested faults, select each of the related product terms
whose output is not 0 and set one of its unspecified inputs to 0.

☞ Since setting one product term to 0 can result in another being forced to
1, the closing algorithm must also iterate n times, using random selection
techniques, where n is a user-specified variable.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-17

☞ Empirical data show that defect coverage is high. If, however, experience
dictated the need, extra xpt faults can be accommodated by PLA/TG.

 Easily Testable PLA Design [Fujiwara]

Assumption: nMOS technology—the PLA is typically implemented as a NOR-

NOR array.
Goal: To design PLAs that can be tested by function-independent test patterns.
Method: Augment a given PLA by adding extra logic—a shift register, 2 cascades
of XOR gates, 2 columns between the i/p decoder and the AND array, and a col-
umn and a row to AND and OR arrays, respectively. The extra product line is
arranged so that each row of the AND array has an odd number of connections.
The extra row of the OR array is arranged likewise.

① The shift register is used to select an arbitrary product line by setting 0 to the
selected line and 1 to all others (* NOR logic is assumed).
② The control array is used to select any row of the AND array, i.e., to sensitize
any output line of the decoder. To select Q2i 1 , set Xi to 0, all other Xj s to
1, C1 to 0, and C2 to 1. To select Q2i , set Xi to 1, all other Xj s to 0, C1 to 1,
and C2 to 0.
③ The cascade of XOR gates below the OR array is used as a parity checker.
④ The cascade of XOR gates to the left of the OR array also is used as a parity
checker.

✯ Result: A universal test set can be derived to detect all

❶ stuck faults in the shift register,
❷ single stuck faults on the lines of the control, AND, and OR arrays,
❸ single xpt faults in the AND and OR arrays, and
❹ multiple stuck faults on the external i/o lines of the XOR gates.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-18

C1 C2
Sin S1 . ... Sm . Sm+1 . Sout xi Q2i 1

C1 C2 Q2i
x1 . . ... . . Q1
. ... Q2
... ... Pi
extra Si
column
xn . ... . Q2n 1
. ... Q2n
... . . F1
... ... ...
extra ... . . Fk
row
. ... . .
 ...    .. 
Z1 Z2

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-19

A Universal Test Set:

X1


Xi


Xn C C S


Sj
1 2 1


Sm
+1 Z1 Z2
I 1
0








0 1 0 1








1 0 0
Ij2 0








0 1 0 1


0


1 1 1
Ij3 1








1 0 1 1


0


1 1 1
Ii4 1


0


1 0 1 0








0 m x
Ii5 0


1


0 1 0 0








0 m x
j = 1; : : : ; m + 1; i = 1; : : : ; n;
n=# i/p lines; m=# product lines;
m = 0(1) if m is even (odd).

➀ The SR function is verified by I 1 Ij2 by observing the response from Sout .

➁ Both Ij2 and Ij3 can detect any xpt fault on the j th column and any row stuck
fault of the OR array by observing Z2 .
➂ Both Ij2 and Ij3 can detect a s/0 on the j th column, s/1 on others, and s/1 on
the rows of the AND array by observing Z1 .
➃ Ii4 and Ii5 can detect any xpt fault and s/0 fault on the rows of the AND array
by observing Z1 .
➄ The extra-device fault at the xpt of C1 (C2 ) with Q2i (Q2i 1 ) is detected by
Ii5 (Ii4).
➅ The missing-device fault at the xpt of C1 (C2) with Q2i (Q2i 1 ) is detected by
some of Ij2 (Ij3 ).
➆ The s/0 on C1 and the s/1 on C2 are detected by some of Ij2 .
➇ The s/1 on C1 and the s/0 on C2 are detected by some of Ij3 .
➈ I 1 and Ij2 are sufficient to detect all multiple stuck faults in the 1st XOR
cascade [Fujiwara, pp. 198-199].
➉ I 1 and Ij2 can detect most multiple stuck faults in the 2nd XOR cascade [Fu-
jiwara, pp. 198-199].

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
7. Design for Testability 7-20

References

[1] J. Savir, “Syndrome-testable design of combinational circuits”, IEEE Trans.

Computers, vol. 29, no. 6, pp. 442–451, June 1980.
[2] Z. Barzilai, J. Savir, G. Markowsky, and M. G. Smith, “The weighted syn-
drome sums approach to VLSI testing”, IEEE Trans. Computers, vol. 30, no.
12, pp. 996–1000, Dec. 1981.
[3] M. I. Y. Williams and J. B. Angell, “Enhancing testability of large-scale in-
tegrated circuits via testpoints and additional logic”, IEEE Trans. Computers,
vol. 21, pp. 46–60, 1973.
[4] S. Funatsu, N. Wakatsuki, and T. Arima, “Test generation systems in Japan”,
in Proc. 12th Design Automation Symp., June 1975, pp. 114–122.
[5] S. Funatsu, N. Wakatsuki, and A. Yamada, “Designing digital circuits with
easily testable consideration”, in Proc. Int. Test Conf. (ITC), Sept. 1978, pp.
98–102.
[6] E. B. Eichelberger and T. W. Williams, “A logic design structure for LSI test-
ing”, in Proc. IEEE/ACM Design Automation Conf. (DAC), June 1977, pp.
462–468.
[7] E. B. Eichelberger and T. W. Williams, “A logic design structure for LSI testa-
bility”, J. Design Automation and Fault-Tolerant Computing, vol. 2, pp. 165–
178, May 1978.
[8] H. Ando, “Testing VLSI with random access scan”, in Proc. IEEE COMP-
CON, 1980, pp. 50–52.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002