Scribd
Upload
13 views

1 Create - Clock

Uploaded by

Ashok Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
13 views

1 Create - Clock

Uploaded by

Ashok Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

Specifying Clocks SECTION 7.

7.2 Specifying Clocks


To define a clock, we need to provide the following information:

i. Clock source: it can be a port of the design, or be a pin of a cell in-


side the design (typically that is part of a clock generation logic).
ii. Period: the time period of the clock.
iii. Duty cycle: the high duration (positive phase) and the low dura-
tion (negative phase).
iv. Edge times: the times for the rising edge and the falling edge.

Figure 7-2 shows the basic definitions. By defining the clocks, all the inter-
nal timing paths (all flip-flop to flip-flop paths) are constrained; this im-
plies that all internal paths can be analyzed with just the clock
specifications. The clock specification specifies that a flip-flop to flip-flop
path must take one cycle. We shall later describe how this requirement (of
one cycle timing) can be relaxed.

High
duration
Low duration

SYSCLK
0 5 20 25

Period

Figure 7-2 A clock definition.

181
C HAPTER 7 Configuring the STA Environment

Here is a basic clock specification1.

create_clock \
-name SYSCLK \
-period 20 \
-waveform {0 5} \
[get_ports2 SCLK]

The name of the clock is SYSCLK and is defined at the port SCLK. The peri-
od of SYSCLK is specified as 20 units - the default time unit is nanoseconds
if none has been specified. (In general, the time unit is specified as part of
the technology library.) The first argument in the waveform specifies the
time at which rising edge occurs and the second argument specifies the
time at which the falling edge occurs.

There can be any number of edges specified in a waveform option. Howev-


er all the edges must be within one period. The edge times alternate start-
ing from the first rising edge after time zero, then a falling edge, then a
rising edge, and so on. This implies that all time values in the edge list
must be monotonically increasing.

-waveform {time_rise time_fall time_rise time_fall ...}

In addition, there must be an even number of edges specified. The wave-


form option specifies the waveform within one clock period, which then re-
peats itself.

If no waveform option is specified, the default is:

-waveform {0, period/2}

1. The specification and constraint are used as synonyms to each other. These are all part
of the SDC specifications.
2. See appendix on SDC regarding scenarios when object access commands, such as
get_ports and get_clocks, should be used.

182
Specifying Clocks SECTION 7.2

Here is an example of a clock specification with no waveform specification


(see Figure 7-3).

create_clock -period 5 [get_ports SCAN_CLK]

In this specification, since no -name option is specified, the name of the


clock is the same as the name of the port, which is SCAN_CLK.

SCAN_CLK
0 2.5 5.0 7.5

Figure 7-3 Clock specification example.

Here is another example of a clock specification in which the edges of the


waveform are in the middle of a period (see Figure 7-4).

BDYCLK

0 5 12 15 20 27

One period

Figure 7-4 Clock specification with arbitrary edges.

create_clock -name BDYCLK -period 15 \


-waveform {5 12} [get_ports GBLCLK]

The name of the clock is BDYCLK and it is defined at the port GBLCLK. In
practice, it is a good idea to keep the clock name the same as the port name.

183
C HAPTER 7 Configuring the STA Environment

Here are some more clock specifications.

# See Figure 7-5(a):


create_clock -period 10 -waveform {5 10} [get_ports FCLK]
# Creates a clock with the rising edge at 5ns and the
# falling edge at 10ns.

# See Figure 7-5(b):


create_clock -period 125 \
-waveform {100 150} [get_ports ARMCLK]
# Since the first edge has to be rising edge,
# the edge at 100ns is specified first and then the
# falling edge at 150ns is specified. The falling edge
# at 25ns is automatically inferred.

FCLK

0 5 10 15

Period
(a)

ARMCLK
0 25 100 125 150
Period
(b)

Figure 7-5 Example clock waveforms.

# See Figure 7-6(a):


create_clock -period 1.0 -waveform {0.5 1.375} MAIN_CLK
# The first rising edge and the next falling edge

184
Specifying Clocks SECTION 7.2

# is specified. Falling edge at 0.375ns is inferred


# automatically.

# See Figure 7-6(b):


create_clock -period 1.2 -waveform {0.3 0.4 0.8 1.0} JTAG_CLK
# Indicates a rising edge at 300ps, a falling edge at 400ps,
# a rising edge at 800ps and a falling edge at 1ns, and this
# pattern is repeated every 1.2ns.

create_clock -period 1.27 \


-waveform {0 0.635} [get_ports clk_core]

MAIN_CLK

0 0.375 0.500 1.000 1.375 1.500

Period
(a)

JTAG_CLK

0 0.3 0.4 0.8 1.0 1.2 1.5 1.6

Period
(b)

Figure 7-6 Example with general clock waveforms.

create_clock -name TEST_CLK -period 17 \


-waveform {0 8.5} -add [get_ports {ip_io_clk[0]}]
# The -add option allows more than one clock
# specification to be defined at a port.

185

You might also like