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Preparation UCIE Guide

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42 views12 pages

Preparation UCIE Guide

Uploaded by

shivraj.thakare
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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UCIE Consortium

 Open industry consortium


 12 board members
 180 members
 Adopter members gets only final spec
 Contributor members gets access to all Spec including intermediate specs
Progress (2 years for spec 2.0):
 Started March 2022
 Spec 1.0 spec June 2022
 Spec 1.1 Spec Aug 2023 (Backward compatible to 1.0)
 First proof of interoperability between Intel testchip (on Intel 3nm node), and
Synopsys UCIE Phy (on TSMC process node) in 2023
 Spec 2.0 Aug 2024

UCIE Specification consists of following specifications:


Electrical, Protocol , physical , systems and software, and manageability
UCIE10 UCIE1.1 Overview (Advantage and Usage)

Why UCIE (Three advantages)


 More performance 
bigger Die  hitting reticle
limit (Eg: muti-cpre CPU,
GPU etc)
 Yield Challenges at higher
die size (Yield)
 UCIE can facilitate On
Package Memory
(Performance)
 Able to use the older
process node IP (Cost)
 Time to market due to
reuse of older process
node IP(s)
Other things
(+) Neef 2D, 25D, and 3D package
Package is a new system
UCIE 1.0/1.1 Spec Overview

UCIE 1.0 and 1.1 specs


 Layered approach (Physical layer, Adapter level, and protocol layer)
 Design of these layers can come from any design house
 Specs at the boundary of each later, and hence entire stacks functional
behaviour is ensured through specs
 Well defined specs (Form factor, management, compliance, interop, )
UCIE 1.0/1.1 PKG Requirement (2D and 2.5D)
Planer package Technologies (2D and 2.5D)
2D Package technology (without silicon bridge)
 Uses package substrate
 Lower cost
 Longer Distance
 Higher power than 2.5D
 No Silicon Bridge
2.5 D Package technology (with silicon bridge)
 Uses package substrate and silicon bridge
 Example of silicon bridge (Intel EMIB, TSMC CoWos)
 Advance bump map (25 micron to 55 micron)
 Lower Power
 Higher Cost
 Idea is construct a due using ant process node, and use any package and
asymbly house

UCIE Usage Model


Entire system on package
 Accelerator (advance or older mode or mixed)
 Memory and IO controller die (older process)
 Covers entire compute platforms )Handlend, client, server

UCIE 2.0 vertical connectivity (3D package)
Advantages of 3D package (Goes with UCIE 2.0)
 Hybrid bonding is successful in memory (eg: HBM memory)
 Evolving technology
Advantages of 3D package
 Reduce parasitic  lower power  Simple circuits
 Increased bump density (eg: Bump pitch reducetion from 25
micron to 1 micron increases bump density by 625X)
 Can be operated at lower circuits but with high BW due to
bump density
 Bumps can be anywhere (not just shoreline)
Limitations on constructions
 Bump pitch needs to match between two UCIE
communicating
 Analog CKT needs to be simpler so that design is always
bump limited
 Analog CKT gets 29-30% more bumps due to Power/GND
bumps

BEST Power Bandwidth and Latency!!!!!


Simplification of Circuit for UCIE 2.0 3D

Simplicity of Phy for UCIE 3D (compared to UCIE_S (1.0), and


UCIE_A(1.1))
 No complex TX, RX, Clocking
 No expensive and fat ESD structure
 Insertion loss is zero
 Simple inverter based CKT would do
 No need of Die to Die adapter (NOC can directly talk to Phy)
 Circuit becomes similer from UCIE_S to UCIE_A to USIE_1.0
(3D)

Impact of lower bump pitches in UCIE 2.0 on Repair mechanism
 More than 1 pin can go bad
 The fault can occure on multiple pins in one cluster or
multiple pins of multiple clusture
 Repair needs to be at the clusture level or not at pin level.
 Large muz based repair mechanism can be in a cluster
DFX challenges and improvements in UCIE_2.0
 DFX coverage in UCIE1.0/1.1  Margin, interop, loopback,
compliance, side band, fault reporting. (interconnect level)
 Challenges exists at chiplet and package level. Addressed in
2.0
 More solution as and when problems are uncovered
 Objective is to make UCIE plug-and-play
 Test and repair is designed at all level, Die (sort), package
(bond)=, and so on.
 In-field test and repair needs to be solved holistically.
 Dedicated ports for testability and debug
UCIE 2.0 improvements

KPI Comparison (UCIE 2.0, UCIE 1.1, UCIE 1.0)

UCIE KPI
 Multiple data rates in planer UCIE_S, UCIE_A upto 32G
 UCIE_3D would be same as SOC freq (nominal BW limit 4G)
 Even at lower data rate, for same area UCIE_3D gives
exppnentially higher BW due to higher bump count
 Due to simplicity the UCIE_3D power is exponentially smaller
compared to UCIE_A and UCIE_S
 Power efficiency of UCIE 3D is 25 times better than UCIE_A
and 50 times better than UCIE_S
 Low power entry exit latencies is almost zero for UCIE_3D
compared to 0.5ns to 1ns for planer UCIE
Summary
 Normally standards are multi decade and multi genetation
long
 Rapid innovation fueled by demands from industry.
 www.UCIExpress.com
Adoption in the world
Several companies have announced products with UCIE IP
Several IP and VIPs companies have announced silicon success
Intel Synopsys announced interoperability between Intel (intel3
process node), and Synopsys (manufactured on TSMS 3E).. this
happened 1.5 years after announcement of concertium
Sevel silicon demo announced by Cadence, Alphawave, and lot more

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