APB Slave Specification

Table of Contents
APB Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Test Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APB Specification
The APB (Advanced Peripheral Bus) slave module is designed to interface with an AMBA-compliant
bus system. It handles read and write transactions, manages memory operations, and provides
necessary control signals. The module is optimized for low power and low bandwidth applications.

Signal List
Signal Name Direction Description

PCLK Input Clock signal for synchronizing operations.

PRESETn Input Active LOW reset signal.

PADDR Input Address bus for selecting memory locations.

PSEL Input Slave select signal indicating a transaction.

PENABLE Input Indicates the second cycle of a transaction.

PWRITE Input HIGH indicates a write operation; LOW indicates

a read operation.

PWDATA Input Write data bus driven during write cycles.

PRDATA Output Read data bus driven by the slave during read
cycles.

PREADY Output Indicates when the slave is ready for the next
operation.

PSLVERR Output Indicates an error in the transaction (not used in

this implementation).

Test Cases
Test Case No. Objective Input Expected Output

Test Case 1 Reset Test * Assert rst_n (active low) * prdata = 0

* Check prdata and pready * pready = 0

1
Test Case No. Objective Input Expected Output

Test Case 2 Write Operation * Set psel = 1, pwrite = 1, penable = 1, * After one clock
Test paddr = 8’h01, pwdata = 32’hA5A5A5A5 cycle:

* mem[8’h01] =
32’hA5A5A5A5

* pready asserted

Test Case 3 Read Operation * First perform Test Case 2 write * After one clock
Test operation* cycle:

* Then set psel = 1, pwrite = 0, * prdata =

penable = 1, paddr = 8’h01 32’hA5A5A5A5

* pready asserted

Test Case 4 Invalid Address * Set psel = 1, pwrite = 1, penable = 1, * No changes to

Handling Test paddr = 8’hFF (invalid address) valid memory
locations

* No errors
generated

Test Case 5 Multiple Write * Write paddr = 8’h02, pwdata = * mem[8’h02] =

Operations Test 32’hDEADBEEF 32’hDEADBEEF

* Write paddr = 8’h03, pwdata = * mem[8’h03] =

32’hFEEDFACE 32’hFEEDFACE

Test Case 6 Multiple Read * Perform writes from Test Case 5 * Read paddr =
Operations Test 8’h02 returns
* Read paddr = 8’h02, then paddr = 32’hDEADBEEF
8’h03
* Read paddr =
8’h03 returns
32’hFEEDFACE

Test Case 7 PREADY Signal * Perform a write operation * pready asserted

Assertion Test after the write
* Observe pready operation
completes

Test Case 8 Simultaneous * Set psel = 1, penable = 1, pwrite = 1 * Module

Read/Write prioritizes write
Attempt Test operation

Test Case 9 Idle State * Perform a write or read operation * Module returns
Verification Test to IDLE state
* Then set psel = 0, penable = 0

2
Test Case No. Objective Input Expected Output

Test Case 10 Reset During * Start a write or read operation * Module resets
Operation Test
* Assert rst_n = 0 mid-operation * prdata = 0

* pready = 0

Test Case 11 Write with PSEL * Start a write operation * Write operation
Low During should not
Transaction * Deassert psel = 0 mid-transaction complete

* Memory location
remains
unchanged

Test Case 12 Read with PSEL * Start a read operation * Read operation
Low During does not complete
Transaction * Deassert psel = 0 mid-transaction
* prdata remains
undefined or at
the previous value

Test Case 13 Check Memory * Perform writes to all valid addresses * All memory
Boundary (0 to 255) locations should
Conditions be correctly
written to and
readable