Logic block architecture:

Outline

• FPGA logic cells

• Timing models
• Power dissipation
• I/O block architecture: Input and
Output cell characteristics
• Clock input,
• Timing
• Power dissipation
A configurable logic block (CLB) is the basic repeating logic resource on an
FPGA. When linked together by routing resources, the components in CLBs
execute complex logic functions, implement memory functions, and
synchronize code on the FPGA.

CLBs contain smaller components, including flip-flops, look-up tables

(LUTs), and multiplexers.

•Flip-Flop—A circuit capable of two stable states that represents a single

bit. A flip-flop is the smallest storage resource on the FPGA. Each flip-flop
in a CLB is a binary register used to save logic states between clock cycles
on an FPGA circuit.
•Look-up Table (LUT)—A collection of gates hardwired on the FPGA. An
LUT stores a predefined list of outputs for every combination of inputs.
LUTs provide a fast way to retrieve the output of a logic operation because
possible results are stored and then referenced rather than calculated. The
LUTs in a CLB can also implement FIFOs and memory items in LabVIEW.
•Multiplexer—A circuit that selects between two or more inputs and then
returns the selected input.
Power Dissipation
• FPGA (Field-Programmable Gate Array) power dissipation, also known as power
consumption, is a critical consideration when designing and using FPGAs. Power
dissipation refers to the amount of electrical power that an FPGA device consumes
during its operation. It is an essential parameter to understand because excessive
power dissipation can lead to overheating, reduced reliability, and increased operating
costs. Here are some key points to consider regarding FPGA power dissipation:
1. Dynamic Power Dissipation: This is the power consumed by the FPGA when it is
actively processing data and performing tasks. It mainly depends on the switching
activity of the logic gates and interconnections within the FPGA. Higher clock
frequencies and increased logic activity result in higher dynamic power dissipation.
2. Static Power Dissipation: This is the power consumed by the FPGA even when it is
not actively performing any computation. It is primarily due to leakage currents in
transistors and other components. Static power consumption is a function of the
FPGA's process technology, temperature, and voltage. Newer FPGA technologies
tend to have lower static power dissipation.
3. Power Supply Voltage (Vcc): Lowering the supply voltage reduces power
dissipation. However, this must be done within the FPGA's specified operating range
to ensure reliable operation. Reducing Vcc also affects the FPGA's performance.
I/O block architecture:
Input/Output Block (IOB)
• The Input/Output Block (IOB) provides a programmable,
unidirectional or bidirectional interface between a package
pin and the FPGA’s internal logic, supporting a wide
variety of standard interfaces.
• The robust feature set includes programmable control of
output strength and slew rate, registered or computational
inputs and outputs with dedicated double data rate (DDR)
registers, programmable input delays, on-chip termination,
and hot-swap capability.
• There are three main signal paths within the IOB: output
path, input path, and 3-state path.
 Input/Output Block (IOB)
Each path has its own pair of storage elements that can act as either registers or
latches.
• The input path carries data from the pad, which is bonded to a package pin,
through an optional programmable delay element directly to the I line. After
the delay element, there are alternate routes through a pair of storage elements
to the IQ1 and IQ2 lines. The IOB outputs I, IQ1, and IQ2 lead to the FPGA’s
internal logic. The delay element can be set to ensure a hold time of zero.
• The output path, starting with the O1 and O2 lines, carries data from the
FPGA’s internal logic through a multiplexer and then a three-state driver to the
IOB pad. In addition to this direct path, the multiplexer provides the option to
insert a pair of storage elements.
• The 3-state path determines when the output driver is high impedance. The
T1 and T2 lines carry data from the FPGA’s internal logic through a
multiplexer to the output driver. In addition to this direct path, the multiplexer
provides the option to insert a pair of storage elements. All signal paths
entering the IOB, including those associated with the storage elements, have
an inverter option. Any inverter placed on these paths is automatically
absorbed into the IOB.
Input and Output cell characteristics :
Key characteristics of FPGA input and output cells:
FPGA Input Cells:
1.I/O Standards: FPGAs support a variety of I/O standards, such as LVCMOS (Low Voltage
Complementary Metal-Oxide-Semiconductor), LVTTL (Low Voltage Transistor-Transistor Logic),
LVDS (Low Voltage Differential Signaling), and others. The input cells are designed to be
compatible with these standards.
2.Voltage Levels: FPGA input cells are designed to accept signals at specific voltage levels based
on the selected I/O standard. For example, LVCMOS typically operates at 3.3V or 1.8V, while
LVDS operates with differential signaling.
3.Sensitivity: Input cells are designed to be sensitive to voltage transitions and can detect both
rising and falling edges of a signal.
4.Schmitt Trigger: Many FPGA input cells include a Schmitt trigger option, which helps to clean
up noisy or slow input signals by providing hysteresis.
5.Termination: Some FPGA input cells offer termination options, such as on-chip resistors or
termination voltage settings, to match the impedance of the external signal source.
6.I/O Bank Assignment: FPGAs are divided into I/O banks, and input cells can be assigned to
specific banks, allowing the user to control the electrical characteristics and voltage levels of a
group of I/O pins.
7.Pull-Up/Pull-Down Resistors: Some FPGA input cells can be configured to have internal pull-
up or pull-down resistors to set the default state of the input when no external signal is applied.
Input and Output cell characteristics :
Key characteristics of FPGA input and output cells:
FPGA Output Cells:
1.I/O Standards: Similar to input cells, FPGA output cells also support various I/O standards.
They are designed to generate signals that adhere to these standards.
2.Voltage Levels: Output cells produce signals at specific voltage levels based on the selected I/O
standard, similar to input cells.
3.Drive Strength: FPGA output cells often allow users to adjust the drive strength of the output
signal to match the requirements of the connected device or trace impedance.
4.Slew Rate Control: Some FPGA output cells offer slew rate control to adjust the rate of voltage
transition in the output signal, which can help reduce signal integrity issues in high-speed
applications.
5.TriState/Bidirectional: In some cases, FPGA output cells can be configured as tristate or
bidirectional to allow for dynamic control of the output signal and to facilitate bus sharing.
6.Clock Outputs: FPGAs often have dedicated output cells for clock signals, which may have
special characteristics such as low jitter and controlled skew.
7.I/O Delay: FPGA output cells may offer options for configuring output delay, which is crucial
for aligning signals in synchronous designs.
8.Output Enable/Disable: Output cells may have an option to enable or disable the output signal
under software control.
FPGA Clock input
• FPGAs employ the use of several blocks or flip flops that work in
parallel in different interconnecting paths that can be operated in
different frequencies. Clocks are what make it possible for the various
flip flops inside a single FPGA to transition to a new state at the clock
speed, allowing FPGA to make high speed calculation or bit
manipulation in high speed.
• Clock in FPGA
• A clock is a signal inside any digital circuit the determines how fast a
flip flop (or a group of flip flops) runs. The clock signal is connected
to all flip flops and RAM blocks and activates them according to the
clock frequency. The faster the clock, the faster the design will run
and therefore a higher clock speed FPGA will perform any desired
function quicker than a slow clock speed FPGA. A typical FPGA
consists of several clock signals and thus allows different areas across
the FPGA to operate in different speed.
FPGA Clock Domains
• FPGA systems contain internal phase locked loops of PLLs that help
generate various frequencies of signal waves. A clock in an FPGA
system is responsible for driving the FPGA design and determines how
fast it can run and process data, with numbers reaching a maximum of
upwards of 1GHz. it produces a fifty percent duty cycle of square
waves that are half on off time and half on time. A faster clock
translates into a faster data processing, but a fast clock is not what is
always needed.
• A single FPGA system will employ the use of at least one clock that
will generate a wave at a certain frequency which will then be
distributed across the FPGA to produce a synchronized response
from all the flip flops involved in the design.
• An external oscillator placed on the circuit board is what generates
the square wave or clock signal with a certain frequency and enters
the FPGA system through a single physical connecting pin. The
clock signals are distributed along interconnected lined or wires
called global routing or global lines so that the signal is distributed
and received at the same time by each flip flop. If the signal reaches
the different flip flops at different times, the time difference between
the reception of the clock pulse is called skew and can interfere with
the performance of the system. Therefore, employing the use of a
clock with dedicated routing helps avoid skew or minimize it to the
maximum possible degree.
Each clock domain will have its own dedicated routing and
clock pin, with the entire system termed as a single block with
extremities that extending all the way to all of the flip flops,
almost like a tree branching out.
You may think about using multiple clocks if you are using an
external device such as an SDRAM, Sensors, Camera, or any other
special external components that need another signal at a different
frequency in order to run directly in association with your FPGA.
but you have to consider the fact that managing multiple clock
domains in a single FPGA is really complicated and should
generally be avoided when possible, which is the case in this
situation.
Crossing Clock Domain in FPGA
• If you have to transfer data across multiple clock domains, then you
must look into crossing them using the likes of synchronizers or
FIFOs. Two completely different clocks cannot use each other’s
signals if they are not related at all as it would induce an element of
metastability. Splitting and crossing the clock domains in your FPGA
can end up producing unwanted glitches bugs that can end up being
extremely difficult to understand and remove. Not only that but using
logic in order to create multiple clocks can introduce skew into your
designs as you will be using routing fabrics instead of dedicated clock
routing lines, with the former having a greater number of interconnects
which cause the signals to become lethargic and variable. At the end of
it all, this system can end up being extremely inefficient as well as
highly power consuming if you are not aware of how to properly cross
the clocks or manage them.
FPGA Timing
• Timing is a term used in digital circuits to refer to the time
it takes a signal to propagate from one flip-flop, through
some combinational logic, to the next flip-flop.
• It is very important to understand that combinational logic is not
instantaneous. It takes time for the signal to propagate. The reason
for this is that digital circuits actually look like a bunch of RC
circuits. MOSFETs, a type of transistor, are the transistors of
choice for digital circuits. The gate (switch part) of a MOSFET
acts much like a capacitor and takes a small amount of time to
charge and discharge (turn on and off the transistor). The more
transistors you need to turn on and off, the longer it takes.
• It's not important to understand exactly why it takes a certain
amount of time for a signal to propagate through combination
logic, just that it does and the more logic you have the longer it
will take.
• Since each flip-flop will copy the value of D to Q at the rising edge
of each clock, that means that we have a single clock cycle for the
output of the first flip-flop to propagate through our combinational
logic and make it to the input of the second flip-flop.
Normally flip-flops require their inputs to be stable for a certain amount of time
before and after the rising edge of the clock. These times are known
as the setup and hold times respectively. These parameters constrain our circuit
even more because now we have to ensure that the delay of our combinational
logic is short enough that the signal will get there in a clock period minus the
setup time. However, it can't be too fast that it violates the hold time!
The last flip-flop parameter we'll be concerned about here is the clock-to-
Q propagation delay.
• we have assumed that the moment the rising edge of the clock
happens, the value of D showed up at Q. However, like all things,
there is a slight delay. The clock-to-Q propagation delay specifies
the amount of time after the rising edge of the clock that Q outputs
the new value. This delay cuts into the time we have for the
combinational logic since the input to the combinational logic is
delayed!
• To summarize, the time it take for the signal to propagate through
the combinational logic must be shorter than the clock period
minus the clock-to-Q propagation delay minus the setup time. The
combinational logic delay must also be greater than the hold time
minus the clock-to-Q propagation delay.
• If we let the combinational logic delay = CLD, clock period
= CLK, setup time = ST, hold time = HT, clock-to-Q propagation
delay = CQ, then the following formula shows our constraints.
• HT - CQ < CLD < CLK - CQ - ST
Micro Controller Vs FPGA
• Microcontrollers and FPGAs (Field-Programmable Gate Arrays) are both types of integrated circuits used in
electronic systems, but they serve different purposes and have distinct characteristics. Here are the key
differences between microcontrollers and FPGAs:
1. Function and Purpose:
1. Microcontroller:
1. A microcontroller is a compact, single-chip computer designed for controlling specific tasks or
applications.
2. It typically includes a CPU (Central Processing Unit), memory (RAM and ROM), input/output
peripherals, timers, and sometimes analog components.
3. Microcontrollers are commonly used in embedded systems, such as in consumer electronics (e.g.,
washing machines, microwave ovens), automotive control systems, and various IoT devices.
2. FPGA:
1. An FPGA is a reprogrammable digital logic device that allows you to implement and customize
digital circuits and logic functions.
2. It consists of an array of configurable logic blocks and programmable interconnections.
3. FPGAs are often used for applications that require high-speed parallel processing, digital signal
processing (DSP), and hardware acceleration, such as in telecommunications, aerospace, and
scientific computing.
2. Programming:
1. Microcontroller:
1. Microcontrollers are typically programmed using high-level languages (e.g., C, C++) or
assembly language.
2. The software is compiled into machine code and loaded onto the microcontroller's
memory.
2. FPGA:
1. FPGAs are programmed using hardware description languages (HDLs) like VHDL or
Verilog.
2. The design is synthesized into a configuration bitstream, which is loaded onto the FPGA
to define its functionality.
3. Flexibility and Customization:
1. Microcontroller:
1. Microcontrollers have fixed hardware components, limiting their ability to be customized
or reconfigured for different tasks.
2. They are well-suited for tasks that require specific control functions but are less flexible in
terms of hardware modifications.
2. FPGA:
1. FPGAs are highly flexible and can be reprogrammed to perform different tasks and
implement various digital circuits.
2. This reconfigurability makes them ideal for rapid prototyping and applications where
hardware customization is crucial.
4. Performance:
1. Microcontroller:
1. Microcontrollers are generally slower in terms of raw processing power compared to
FPGAs.
2. They are optimized for low power consumption and cost-effectiveness.
2. FPGA:
1. FPGAs can offer significantly higher performance for specific tasks due to their parallel
processing capabilities.
2. They are often used when real-time processing and high-speed data manipulation are
required.
5. Cost:
1. Microcontroller:
1. Microcontrollers are usually cost-effective for mass-produced consumer products and
small-scale embedded systems.
2. FPGA:
1. FPGAs tend to be more expensive than microcontrollers, making them more suitable for
applications where their flexibility and performance advantages justify the cost.

In summary, microcontrollers are best suited for control-oriented applications with limited
processing needs, while FPGAs are ideal for tasks that require high-speed, customizable,
and parallel processing capabilities.
Programmable Logic Devices
• A programmable logic device is defined as an integrated circuit that contains
an array of logic elements and interconnections that can be programmed by the
user to implement a desired logic function. The logic elements are usually
simple combinational or sequential circuits, such as AND, OR, NOT, and XOR
gates, or registers. The interconnections are usually programmable switches or
multiplexers that can connect the inputs and outputs of the logic elements in
different ways.

Programmable logic devices can be divided into three distinct architectural groups.
• Simple Programmable Logic Devices – SPLDs
• Complex Programmable Logic Devices – CPLDs
• Field Programmable Gate Arrays – FPGAs
SPLD
• SPLDs are the simplest, smallest, and least-expensive type of programmable logic
device. These devices typically have logic gates laid out in arrays where the
interconnection between these arrays is configurable by the user.
The term SPLD covers several types of devices:
PROM
PAL
PLA
CPLD vs FPGA