IntroCtrlSys - Final Exam - 2nd Semester - 2122 - Solution
IntroCtrlSys - Final Exam - 2nd Semester - 2122 - Solution
1.1 Calculate steady state error to unit step input and unit ramp input.
1.2 Calculate the POT and ts (2% criterion) of the closed-loop system.
Design the controller GC(s) such that the system after compensation has a pair of complex poles
with =0.8 and n=8.
Design the controller GC(s) such that the system after compensation has steady-state error to unit
ramp input ess* 0.05 and * 600 .
1 1
ess 0.1379
1 K P 1 6.25
Steady state error to unit step input:
100
KV lim sG ( s ) lim s 0
s 0 s 0 ( s 4) 2
1 1
ess
KV 0
The controller to be designed is a phase lead compensator because the objective is to improve
transient response of the closed-loop sysem
s 1 / T
Gc ( s ) K c
s 1/ T
*
The desired dominant poles: s1,2 0.8 8 j8 1 0.82 6.4 4.8 j
Determine KC : K C 0.1565 1
K C 6.39
s 4.86
GC s 6.39
s 13.18
Problem 3: (3 points)
Ts 1
GC ( s ) KC
Ts 1
8( s 10)e0.04 s
KV lim sG ( s ) lim sG ( s ) 4
s 0 s 0 s( s 20)
1 1
KV* *
20
ess 0.05
KV* 20
KC 5 (0.5p)
KV 4
40( s 10)e0.04 s
Denote: G1 ( s) KC G ( s )
s( s 20)
The Bode diagram of G1 ( s ) :
Bode Diagram
30
20
System: G1
10 Frequency (rad/s): 36.2
Magnitude (dB): 0.0193
0
-10
0
System: G1
Frequency (rad/s): 36.2
-90
Phase (deg): -160
-180
-270
-360
10 0 10 1 10 2
Frequency (rad/s)
1 (C ) 1600
Calculate T:
1 1
T 0.0044 (0.25p)
*
C 95 5.83
0.0257 s 1
Conclusion: The TF of the compensator is: GC ( s) 5 (0.25p)
0.0044s 1
2 1
C B AB
1 10
det(sI A BK ) 0
1 0 0 1 2
det s k1 k2 0
0 1 3 4 1
s 2k1 1 2k2
det 0
3 k1 s 4 k2
( s 3 j3)(s 3 j3) 0
s 2 6s 18 0 (2) (0.25p)
2k1 k2 4 6
9k1 6k2 3 18
k1 1.2857
(0.5p)
k2 0.5714