Static Timing Analysis in a nutshell

Frank de Bont
Trainer / Consultant

© Copyright 2019 Xilinx

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How does static timing analysis work ?

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► Every device path in a design must be analyzed with respect to timing

specifications / requirements
► Catch timing-related errors faster and easier than gate-level simulation & board testing

► Designer must enter timing requirements & exceptions

► Used to guide the FPGA tools during placement and routing
► Used to compare against actual results (post-place and route)

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Clocks
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► Clocks are periodic signals

► Clocks have certain attributes

► Period
► Duty cycle
► Jitter
► Phase

► create_clock –name CLK –period 10 –waveform {2.0 7.0} [get_ports CLK]

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Clock Pessimism
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► Often, the same components are on both the source clock path and the
destination clock path
► Source clock path is timed at [slow_max]
► Destination clock path is timed at [slow_min]

► But a given cell cannot have two different delays at the same time
► Results in pessimism due to the re-convergence of the clock path

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108090**slide

Synchronous Input Interfaces

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► Most interfaces to an FPGA use synchronous communication

► The FPGA and the device driving the FPGA have some shared timing reference
► This is usually a common clock or a related clock

► Complete static timing path through an input

► Starts at a clocked element in the driving device
► Referenced to a clock provided to the driving device
► Ends at a clocked element in the FPGA
► Referenced to the clock that propagates to the destination clocked element in the FPGA
► Propagates through the elements between them
► CLK -> Q of the external device
► Board propagation time
► Port of the FPGA
► Combinatorial elements in the FPGA before the destination clocked element

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 Minimum and Maximum Delays
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► By default, each input port can have one maximum delay and one
minimum delay
► The maximum delay is used for the setup check
► The minimum delay is used for the hold check
► Without the –max or –min option, the value supplied is used for both
► create_clock –name SysClk –period 10
► set_input_delay –clock SysClk 4 –max [get_ports DataIn]
► set_input_delay –clock SysClk 2 –min [get_ports DataIn]

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 Input Timing Overview (1)
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►Both setup and hold at the FPGA input register are analyzed for timing
►Source and destination clocks need to be defined
► Create_clock (FPGA system clock and virtual upstream device clock)
► System (common) clock or forwarded clock

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 Input Timing Overview (2)
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►Upstream device delay and board trace delay need to be specified

► Maximum delay for setup analysis: set_input_delay -max
► Minimum delay for hold analysis: set_input_delay -min
► Referenced to the launch clock edge

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 Input Timing Analysis
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Input Static Timing Path with External Buffer

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► create_clock –name SysClk –period 10 [get_ports Clkin]

► create_clock –name VirtClk –period 10
► set_clock_latency –source 1 [get_clocks VirtClk]
► set_input_delay –clock VirtClk 4 –max [get_ports DataIn]
► set_input_delay –clock VirtClk 2 –min [get_ports DataIn]

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Completing the Static Timing Output Path

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► To complete the static timing path, you need to describe the external
elements for the static timing engine
► What clock is used by the external device?
► Delay between the output port of the FPGA and the external device’s clock
► Includes the required time of the external device and the board delay

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Output Timing Overview (1)

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► Setup and hold at the downstream device input pins are analyzed for timing

► Source and destination clocks need to be defined, from which the tool
derives the source and destination clock edges to consider

► create_clock (actual FPGA clock and virtual downstream device clock)

► system (common) clock or forwarded clock
► create_generated_clock for forwarded output clocks

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 Output Timing Overview (2)
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► Downstream device setup and hold requirements need to be specified

► Downstream setup requirement:
► set_output_delay –clock DstClk 4 –max [get_ports DataOut]
► Downstream hold requirement:
► set_output_delay –clock DstClk 2 –min [get_ports DataOut]
► Board trace delays should be included
► Referenced to the destination capture clock edge

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 Output Timing Analysis
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 Combinational Delays
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► Combinational delays are paths that enter and exit the FPGA
without being captured by any sequential elements

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 Multicycle Paths
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► Multicycle paths occur when registers are not updated on consecutive

clock cycles
► Always at least N clock cycles between the time the source flip-flops update and
the destination flip-flops capture the result
► Typically, the registers are controlled by a clock enable

► Example shows one form of an N-cycle, multicycle path

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 Modifying the Setup and Hold Capture Edge
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► The setup capture edge can be modified by specifying a multiplier value N

command:
► set_multicycle_path –from $from_list to $to_list –setup <N>
► The new setup capture edge will be <N> edges after the setup launch edge
► The hold capture edge usually needs to be modified with the –hold
command:
► set_ multicycle_path –from $from_list –to $to_list –hold <N-1>
► Returns the hold capture edge to the correct edge

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Setup Checks on Paths with Different Clocks
► When the static timing path starts and ends on different clocks, the
setup check requirement is more complex
► All possible combinations of the source clock and destination clock
are examined
► From each edge on the source clock to the first edge of the destination clock
that is later in time
► The pair with the tightest requirement is used as the launch and capture edge
► Once the launch and capture edge is determined, the setup check is
performed

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 Hold Checks on Paths with Different Clocks
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► There are two possible hold checks for each possible setup check
► From the setup launch edge to the edge before the setup capture edge
► From the edge after the setup launch edge to the setup capture edge
► The launch and capture edges with the tightest requirement are used for
the hold check

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 Example of Multicycle Path (1)
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► Same clock domain or between synchronous clock domains

with same period and no phase-shift

► set_multicycle_path N –setup -from CLK1 –to CLK2

► set_multicycle_path N-1 –hold -from CLK1 –to CLK2

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 Example of Multicycle Path (2)
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► Between SLOW-FAST synchronous clock domains

dummy text

► set_multicycle_path N –setup -from CLK1 –to CLK2

► set_multicycle_path N-1 –hold –end -from CLK1 –to CLK2

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 Example of Multicycle Path (3)
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► Between FAST-SLOW synchronous clock domains

dummy text

► set_multicycle_path N –setup –start -from CLK1 –to CLK2

► set_multicycle_path N-1 –hold -from CLK1 –to CLK2

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 Constraining Metastability Flip-Flops
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► When a flip-flop (REGB0) ► The Vivado timing engine sees the REGB0 →
samples an asynchronous input, REGB1 path as a normal static timing path,
the flip-flop can go metastable subject to a normal setup check
► The metastability will probabilistically ► Allows one clock period of CLKB for the
resolve after some time propagation, including routing
► Back to back flip-flops allow one clock
period for the metastability to resolve before ► To leave time for metastability resolution, the
the second flip-flop samples it (REGB1) requirement on this path should be changed

► set_max_delay –from [get_cells REGB0] –to [get_cells REGB1] 2 121337

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112540**sldi e

Paths Between Different Clock Domains

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► When crossing asynchronously between different clock domains a clock crossing circuit is required
► Many approaches exist ► All of these approaches have implicit
► Use Gray code assumptions
► Use an enable to determine a stable point ► Generally, the skew between different bits of the
► Use a FIFO bus to be crossed cannot exceed one clock
period
► It is not possible to constrain skew, but it is possible to
constrain the maximum delay on all bits of the bus

► In these cases, the clock propagation analysis is irrelevant and should be overridden with
the –datapath_only option

► set_max_delay –from [get_cells REGA] –to [get_cells REGB0] 5 –datapath_only 121337

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