0% found this document useful (0 votes)
43 views27 pages

Lecture 7 Timers

Uploaded by

Craig Peri
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
43 views27 pages

Lecture 7 Timers

Uploaded by

Craig Peri
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 27

Timers on the PIC

16F877

RGM 2020 1
Timer Operation
xxxx
TMR1

2
Timer Operation
TMR1 FFFA
11 1 1 1 1 1 1 1 1 1 1 1 01 0
1. Load counter with preset value

3
Timer Operation
TMR1 FFFA
11 1 1 1 1 1 1 1 1 1 1 1 01 0
1. Load counter with preset value
2. Start counter

4
Timing pulse 1
Timer Operation
TMR1 FFFB
11 1 1 1 1 1 1 1 1 1 1 1 01 1
1. Load counter with preset value
2. Start counter

5
Timing pulse 2
Timer Operation
FFFC
TMR1
11 1 1 1 1 1 1 1 1 1 1 1 10 0
1. Load counter with preset value
2. Start counter

6
Timing pulse 3
Timer Operation
FFFD
TMR1
11 1 1 1 1 1 1 1 1 1 1 1 10 1
1. Load counter with preset value
2. Start counter

7
Timing pulse 4
Timer Operation
FFFE
TMR1
11 1 1 1 1 1 1 1 1 1 1 1 11 0
1. Load counter with preset value
2. Start counter

8
Timing pulse 5
Timer Operation
FFFF
TMR1
11 1 1 1 1 1 1 1 1 1 1 1 11 1
1. Load counter with preset value
2. Start counter

9
Timing pulse 6
Timer Operation
0000
TMR1
00 0 0 0 0 0 0 0 0 0 0 0 00 0
1. Load counter with preset value
2. Start counter
3. On overflow: Overflow flag is set
Interrupt generated

10
Source of Pulses

OSCILLATOR 4:1
Timer
Value of source 0
select bit
1
Counter

Counter input pin 11


Prescalers and Postscalers
• A prescaler divides the signal frequency before it is input
into the counter.

• A postscaler divides the signal frequency after output


from the timer.

Prescaler Postscaler
TIMER
1:4 1:8
12
Timers on the PIC16F877

•Timer 0

•Timer 1

•Timer 2

13
Timer 0
• Timer 0 is an 8-bit timer/counter module.
• Overflow of the counter from FFh to 00h

• In counter mode, the source of the pulses is pin


RA4/T0CKI.

• In counter mode, is selectable to count on either a


rising or a falling edge.

• Shares a prescaler with the watchdog timer.

14
Timer 0 Associated SFRs
TMR0 (01h and 101h)
• Used to hold the count value of the timer.

OPTION_REG (81h and 181h)


• Contains bits that control operation of Timer 0

INTCON (0Bh, 8Bh, 10Bh and 18Bh)


• Contains Timer 0 interrupt enable bit and interrupt
flag.

15
Timer 0 Associated SFRs
OPTION_REG (81h and 181h)

/RBPU INTEDGE T0CS T0SE PSA PS2 PS1 PS0

TIMER/COUNTER Prescale
selection assignment
Counter Prescale
edge bits
selection
16
Timer 1
• Timer 1 is a 16-bit timer/counter module.
• Overflow of the counter from FFFFh to 0000h

• In counter mode, the source of the pulses is pin


RC0/T1OSO/T1CKI.

• Counts only on the rising edge.

• It can be turned on or off.

• Has a dedicated prescaler.


17
Timer 1 Associated SFRs
TMR1L (0Eh) and TMR1H (0Fh)
• Hold the count value of the timer.

T1CON (10h)
• Contains bits that control operation of Timer 1

PIE1 (8Ch)
• Contains Timer 1 interrupt enable bit

PIR1 (8Ch)
• Contains Timer 1 interrupt flag. 18
Timer 1 Associated SFRs
T1CON (81h and 181h)

- - T1CKPS1 T1CKPS0 T1OSCEN /T1SYNC TMR1CS TMR1ON

Timer
enable bit
Prescale bits
TIMER/COUNTER
selection
Oscillator Synchronization
enable bit enable bit
19
Timer 2
• Timer 2 is an 8-bit period timer – operates only as
timer.
• Has associated period register.

• Counts up until count value matches value in period


register.
• i.e. overflows on matching
• Timer resets to 00h on the next cycle.

• It can be turned on or off.

• Has dedicated prescaler and postscaler.


20
Timer 2 Associated SFRs
TMR2 (11h)
• Holds the count value of the timer.

PR2 (92h)
• Holds the period value.

T2CON (12h)
• Contains bits that control operation of Timer 2

PIE1 (8Ch)
• Contains Timer 2 interrupt enable bit

PIR1 (8Ch)
• Contains Timer 2 interrupt flag.
21
Timer 2 Associated SFRs
T2CON (12h)

- TOUTPS3 TOUTPS2 TOUTPS0 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

Prescale bits
Postscale bits Timer
enable bit

22
Interrupt Bits
INTCON
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF

Timer 0
interrupt
Global enable bit TMR0 interrupt
Interrupt
flag
Enable bits
23
Interrupt Bits
PIE1 (8Ch)

PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

Timer related bits


PIR1 (0Ch)

PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

24
Running the Timers
1. Select the clock source (Timer 0 and Timer 1)
2. Select clock edge in counter mode (Timer 0)
3. Set prescale and postscale values and assignments
4. Set synchronisation and oscillator enable (Timer 1)
5. Set the period value (Timer 2)
6. Load the starting value into timer register(s).
7. Enable interrupts if required
8. Put on the timer (Timer 1 and Timer 2).
9. Wait for overflow/match interrupt or poll timer
flag.
25
Tutorial 6
Exercise 4 Q 2

Develop Mikro C program routines to configure and


start the following timers running:
a) Timer 0 as a counter starting at 56h
b) Timer 1 as a timer that overflows after 200
milliseconds for a 10MHz clock frequency
c) Timer 2 to produce a period of 800 counts

26
Laboratory 7
Truck speedometer

•Design Circuit and enter on Proteus


•Develop Program and enter on Mikro C
•Simulate the system
•Build actual circuit
•Download into a PIC and test

27

You might also like