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Power Dissipation Examples

This document summarizes two examples of power dissipation in a digital system. The first example estimates the static power consumption, which is approximately 38mW. If low-leakage devices were unavailable, the static power would increase dramatically to 749mW. The second example estimates the dynamic power consumption per MHz of the system to be 8.64mW. The document provides details on the transistor counts, leakage currents, activity factors, and capacitances used to calculate the static and dynamic power estimates.

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Ehab Zaghlool
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267 views4 pages

Power Dissipation Examples

This document summarizes two examples of power dissipation in a digital system. The first example estimates the static power consumption, which is approximately 38mW. If low-leakage devices were unavailable, the static power would increase dramatically to 749mW. The second example estimates the dynamic power consumption per MHz of the system to be 8.64mW. The document provides details on the transistor counts, leakage currents, activity factors, and capacitances used to calculate the static and dynamic power estimates.

Uploaded by

Ehab Zaghlool
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Power Dissipation Examples

January 12, 2012

This is an explanation of the two examples from the book (CMOS VLSI Design by Neil Weste and David Harris, 4th edition) merged together. First example is on page 189 and the second example is on page 191. The power dissipation is discussed in section 4.4 pp.186 to pp.193.

Design Problem (Static Power)


A digital system in a 1.2 V 100nm process has 200 million transistors, of which 20 million are in logic gates and the remainder in memory arrays. The average logic transistor width is 12 and the average memory transistor width is 4. The process has two threshold voltages and two oxide thicknesses to partially save power. 1. High-Leakage Process Options: (a) Low-threshold OFF devices have 20nA/m leakage current. (b) Gates with thin oxide have 3nA/m leakage current. 2. Low-Leakage Process Options: (a) High-threshold OFF devices have 0.02nA/m leakage current. (b) Gates with thick oxide have 0.002nA/m leakage current. Memories use low-leakage devices everywhere. Logic uses low-leakage devices in all but 20% of the paths that are most critical for performance. The following gure summarizes some of the givings:

Digital System 200 Million Transistors

20 Million Transistors Logic

180 Million Transistors Memory

Avg Logic Transistor width=12 80% low-leakage devices 20% high-leakage devices

Avg Memory Transistor width=4 100% low-leakage devices

Diode leakage is negligible. 1. Estimate the static power consumption. The width of the high-leakage devices (HLD) is: HLDwidth = 20 106 (logic transistors) 0.2 (the 20%) 12 (the Avg. logic transistor size) 0.05m (value which is 0.5 feature size which is 100 nm) HLDwidth = 2.4 106 m The width of the low-leakage devices (LLD) is: LLDwidth = 20 106 (logic transistors) 0.8 (the 80%) 12 (the Avg. logic transistor size) 0.05m (value which is 0.5 feature size which is 100 nm) + 180 106 (memory transistors) 4 (the Avg. memory transistor size) 0.05m (value which is 0.5 feature size which is 100 nm) LLDwidth = 45.6 106 m All devices exhibit gate leakage. On average, half the transistors are OFF and contribute subthreshold leakage. Half of the transistors are OFF because of the complimentary nature of CMOS devices. When the pull-up network is ON then the pull-down network is denitely OFF and vice versa. Since usually the number of transistors is the pull-up and pull-down networks are equal, then half of the transistors are OFF. Therefore, the total static current of high-leakage devices (HLD) is: 2

HLDleakagecurrent =

HLDleakagecurrent =

1 2.4 106 m 2 (since half transistors are OFF) (20nA/m) + 2.4 106 m (3nA/m) 31.2mA

The total static current of low-leakage devices (LLD) is: LLDleakagecurrent = 45.6 106 m 1 (since half transistors are OFF) 2 (0.02nA/m) + 45.6 106 m (0.002nA/m) LLDleakagecurrent = 0.5472mA Hence, the total static current is 31.7472mA 32mA. To get the static power, we multiply the current by the voltage; 32mA 1.2V = 38.4mW 38mW . This is likely to be small compared to the dynamic power consumption, yet large enough to limit the battery life of battery-powered systems on standby. 2. How would the power consumption change if the low-leakage devices were not available? If low-leakage devices were not available, the total static current would be: T otalStaticCurrent = (2.4 + 45.6) 106 m 20nA/m + 3nA/m = 624mA 2 Hence, the total static power=624mA 1.2V = 749mW .

Design Problem (Dynamic Power


The 20 Million logic transistors have an average activity factor of 0.1. The memory arrays are divided into banks and only the necessary bank is activated so the eective memory activity factor is 0.5. Assume transistors have a gate capacitance of about 2F F/m. Neglecting wire capacitance, estimate the dynamic power consumption per MHz of the system. Recall that the dynamic power is calculated using:
2 Pdynamic = CVDD f

The total capacitance of the logic transistors= 20 106 12 0.05m 2f F/m = 24nF The total capacitance of the memory transistors= 180 106 4 0.05m 2f F/m = 72nF

The total dynamic power is: Pdynamic = 0.1 (this is ) 24nF (1.2V )2 f + 0.05 (this is ) 72nF (1.2V )2 f Pdynamic = 8.64nW/Hz f OR Pdynamic = 8.64W/GHz f OR Pdynamic = 8.64mW/M Hz f

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