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Lab 3

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15 views9 pages

Lab 3

Uploaded by

trandinhhoangkyanh
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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LAB 3

EX 1:
IDS = f(VDS) , VGS = 1 V, VDS = 0 V -> 1.2 V
IDS = f(VGS), VDS = 1 V, VGS = 0 V -> 1.2 V

 Linear Extrapolation: Threshold voltage = 0.47 V

 Take the square root of the drain current ( sqrt (ID) ) and plot it against VGS. In the
linear region, this plot will be approximately linear.
 Perform a linear fit to the straight portion of the sqrt (ID) vs. VGS curve.
 Extrapolate the fitted line to the x-axis intercept, where sqrt (ID) = 0. The VGS value at
this intercept is the threshold voltage (Vth).

 Threshold Voltage Extraction:

 The extrapolated value of VGS at which sqrt (ID)=0 is the threshold voltage of the NMOS
transistor.
EX 2:
L = 60nm, W = 120nm, VSB = 0 V, VDS = 0V -> 1.2 V, VGS = (0.4 V, 0.6 V, 0.8
V, 1 V )

Because V threshold = 0.47 V:


 When VGS = 0.4 V -> VGS < VTH, NMOS is in cut off region.
 When VGS = 0.6 V -> VGS - VTH = 0.6 – 0.47 = 0.13 V, so when VDS < 0.13 V,
NMOS is in linear region, when VDS > 0.13 V, NMOS is in Saturation region.
 When VGS = 0.8 V -> VGS - VTH = 0.8 – 0.47 = 0.33 V, so when VDS < 0.33 V,
NMOS is in linear region, when VDS > 0.13 V, NMOS is in Saturation region.
 When VGS = 1 V -> VGS - VTH = 1 – 0.47 = 0.53 V, so when VDS < 0.53 V, NMOS is
in linear region, when VDS > 0.53 V, NMOS is in Saturation region.

L = 60nm, W = (120nm, 240nm, 360nm, 480nm) , VSB = 0 V, VDS = 0V ->


1.2 V, VGS = 1 V

Because V threshold = 0.47 V:


 When VGS = 1 V -> VGS - VTH = 1 – 0.47 = 0.53 V, so when VDS < 0.53 V, NMOS is
in linear region, when VDS > 0.53 V, NMOS is in Saturation region.
In Saturation region:

Assume IDS when W = 120nm is I0:


When W = 240nm = 2 x 120nm -> IDS = 2 x I0
When W = 360nm = 2 x 120nm -> IDS = 3 x I0
When W = 480nm = 2 x 120nm -> IDS = 4 x I0
 W increases -> IDS increases

L = (60nm, 120nm, 180nm, 240nm), W = 240nm, VSB = 0 V, VDS = 0V ->


1.2 V, VGS = 1 V

Because V threshold = 0.47 V:


 When VGS = 1 V -> VGS - VTH = 1 – 0.47 = 0.53 V, so when VDS < 0.53 V, NMOS is
in linear region, when VDS > 0.53 V, NMOS is in Saturation region.
In Saturation region:

Assume IDS when L = 60nm is I0:


When L = 120nm = 2 x 60nm -> IDS = 1/2 x I0
When L = 180nm = 3 x 60nm -> IDS = 1/3 x I0
When L = 240nm = 4 x 60nm -> IDS = 1/4 x I0
 L increases -> IDS decreases

EX 3:
L = 60nm, W = 120nm, VSB = 0 V, VDS = 1.2 V, VGS = 0V -> 1 V, VSB =
(0.15V, 0.3V, 0.45V)

- When the body is at a higher potential than the source (for NMOS), the
threshold voltage increases. This is because the increased body potential
induces a larger depletion region, requiring a greater Vgs to invert the channel.
 VSB increases -> VTH increases -> IDS decreases

EX 4:

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