Sequential circuits

Conversion of S-R Flip-Flop into T Flip-Flop

Here, we will discuss the process of conversion of S-R Flip-Flop into a T Flip-Flop using an example.
Rules for conversion:
● Step-1:
Find the characteristics table of required flip-flop and the excitation table of the existing (given)
flip-flop.
● Step-2:
Find the expression of given flip-flop in terms of required flip-flop using K-map.
● Step-3:
Find the circuit diagram of required flip-flop.
S-R Flip-Flop to T Flip-Flop:
Following is the characteristics table of T flip-flop and excitation table of S-R flip-flop.
Now, using K-map we get the expression for of S & R in terms of T.

S = TQn’ & R = TQn

Therefore, the circuit diagram for conversion of S-R flip-flop into T flip-flop is:
Conversion of S-R Flip-Flop into D Flip-Flop

1. S-R Flip-Flop :
S-R flip-flop is similar to S-R latch expect clock signal and two AND gates. The circuit responds to the positive
edge of clock pulse to the inputs S and R.
2. D Flip-Flop :
D Flip-Flop is a modified SR flip-flop which has an additional inverter. It prevents the inputs from becoming the
same value.
Conversion of S-R Flip-Flop into D Flip-Flop :
 ● Step-1:
We construct the
characteristic table of D
flip-flop and excitation
table of S-R flip-flop.

Step-2:
Using the K-map we find the
boolean expression of S and R in
terms of D.

S = D
● R = D'
Step-3:
We construct the circuit diagram of the conversion of S-R flip-flop into D
flip-flop.
Conversion of J-K Flip-Flop into D Flip-Flop
1. JK Flip-Flop:
JK Flip-Flip is basically a gated SR flip-flop which has an additional input that is clock input. It
prevents the invalid output that may be obtained when both the inputs are 1.
2. D Flip-Flop:
D Flip-Flop is a modified SR flip-flop which has an additional inverter. It prevents the inputs from
becoming the same value.
Conversion of J-K Flip-Flop into D Flip-Flop:
● Step-1:
We construct the characteristic table of D flip-flop and excitation table of JK flip-flop.
Step-2:
Using the K-map we find the boolean
expression of J and K in terms of D.
J = D
K = D'

● Step-3:
We construct the circuit
diagram of the conversion of
JK flip-flop into D flip-flop.
Conversion of J-K Flip-Flop into T Flip-Flop

1. J-K Flip-Flop: JK flip-flop shares the initials of Jack Kilby, who won a Nobel prize for his fabrication of the
world’s first integrated circuit, some people speculate that this type of flip flop was named after him because a
flip-flop was the first device that Kilby build when he was developing integrated circuits. J-K flip-flop is the
gated version of SR flip-flop with an addition of extra input i.e. clock input. It prevents invalid output conditions
when both the inputs are at the same value.
2. T Flip-Flop: T flip-flop means Toggle flip-flop. It changes the output on each clock edge and gives an output
that is half the frequency of the signal to the input.
Conversion of J-K Flip-Flop into T
Flip-Flop:

● Step-1: Construct the

characteristic table of T flip-flop
and excitation table of the J-K
flip-flop.
● Step-2: Using the K map, find
the boolean expression for J and
K in terms of T.

J = T
K = T
Step-3: Construct the circuit diagram for the conversion of the J-K
flip-flop into a T flip-flop.
Master-Slave JK Flip Flop
Race Around Condition In JK Flip-flop – For J-K flip-flop, if J=K=1, and if clk=1 for a
long period of time, then Q output will toggle as long as CLK is high, which makes the
output of the flip-flop unstable or uncertain.

This problem is called race around condition in J-K flip-flop.

This problem (Race Around Condition) can be avoided by ensuring that the clock input
is at logic “1” only for a very short time.

This introduced the concept of Master Slave JK flip flop.

Master Slave JK flip flop – The Master-Slave Flip-Flop is basically a combination of

two JK flip-flops connected together in a series configuration.
Out of these, one acts as the “master” and the other as a “slave”.

The output from the master flip flop is connected to the two inputs of the slave flip flop
whose output is fed back to inputs of the master flip flop.

In addition to these two flip-flops, the circuit also includes an inverter.

The inverter is connected to clock pulse in such a way that the inverted clock pulse is given
to the slave flip-flop.

In other words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if CP=1 for
master flip flop then it becomes 0 for slave flip flop.
Working of a master slave flip flop –
1. When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the system.
The slave flip-flop is isolated until the CP goes to 0. When the CP goes back to 0, information is passed
from the master flip-flop to the slave and output is obtained.
2. Firstly the master flip flop is positive level triggered and the slave flip flop is negative level triggered, so
the master responds before the slave.
3. If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the clock forces the
slave to reset, thus the slave copies the master.
4. If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative
transition of the clock sets the slave, copying the master.
5. If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the
negative transition of the clock.
6. If J=0 and K=0, the flip flop is disabled and Q remains unchanged.
Timing Diagram of a Master Slave flip flop –
1. When the Clock pulse is high the output of master is high and remains high till the clock
is low because the state is stored.
2. Now the output of master becomes low when the clock pulse becomes high again and
remains low until the clock becomes high again.
3. Thus toggling takes place for a clock cycle.
4. When the clock pulse is high, the master is operational but not the slave thus the output
of the slave remains low till the clock remains high.
5. When the clock is low, the slave becomes operational and remains high until the clock
again becomes low.
6. Toggling takes place during the whole process since the output is changing once in a
cycle.
 Counters in Digital Logic
● A Counter is a device which stores (and sometimes displays) the
number of times a particular event or process has occurred, often in
relationship to a clock signal.
● Counters are used in digital electronics for counting purpose, they can
count specific event happening in the circuit.
● For example, in UP counter a counter increases count for every rising
edge of clock.
● Not only counting, a counter can follow the certain sequence based on
our design like any random sequence 0,1,3,2… .
● They can also be designed with the help of flip flops. They are used as
frequency dividers where the frequency of given pulse waveform is
divided.
Counters are sequential circuit that count the number of pulses can be either in binary code or BCD form.
The main properties of a counter are timing , sequencing , and counting. Counter works in two modes
Up counter
Down counter
Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter

1. Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main clock and the clock
input of rest of the following flip flop is driven by output of previous flip flops. We can understand it by following
diagram-
It is evident from timing diagram that Q0 is changing as soon as the rising edge
of clock pulse is encountered, Q1 is changing when rising edge of Q0 is
encountered(because Q0 is like clock pulse for second flip flop) and so on.

In this way ripples are generated through Q0,Q1,Q2,Q3 hence it is also called
RIPPLE counter and serial counter.

A ripple counter is a cascaded arrangement of flip flops where the output of one
flip flop drives the clock input of the following flip flop
2. Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives each flip flop so output
changes in parallel. The one advantage of synchronous counter over asynchronous counter is, it can operate on
higher frequency than asynchronous counter as it does not have cumulative delay because of same clock is given
to each flip flop. It is also called as parallel counter.
From circuit diagram we see that Q0 bit gives response to each falling edge of clock
while Q1 is dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on
Q2,Q1 and Q0.
Modulus Counters, or simply MOD counters, are defined based on the number of states that
the counter will sequence through before returning back to its original value.

For example, a 2-bit counter that counts from 002 to 112 in binary, that is 0 to 3 in decimal, has
a modulus value of 4 ( 00 → 1 → 10 → 11, and return back to 00 ) so would therefore be called
a modulo-4, or mod-4, counter. Note also that it has taken four clock pulses to get from 00 to
11.

As in this simple example there are only two bits, ( n = 2 ) then the maximum number
of possible output states (maximum modulus) for the counter is: 2n = 22 or 4.
However, counters can be designed to count to any number of 2n states in their
sequence by cascading together multiple counting stages to produce a single
modulus or MOD-N counter.
Therefore, a “Mod-N” counter will require “N” number of flip-flops connected
together to count a single data bit while providing 2n different output states, (n is
the number of bits).
Note that N is always a whole integer value.
The we can see that MOD counters have a modulus value that is an integral
power of 2, that is, 2, 4, 8, 16 and so on to produce an n-bit counter depending
on the number of flip-flops used, and how they are connected, determining the
type and modulus of the counter.
Design asynchronous Up/Down counter

In asynchronous/ripple counter output of the first flip-flop is provided as the clock to the
second flip-flop i.e flip-flop(FF) are not clocked simultaneously.
Circuit is simpler, but speed is slow.
Asynchronous counter basics :

1 bit asynchronous/ripple counter

When -ve edge clock pulse is applied and input is given to FF logic 1 then the output state of FF
will toggle for every falling edge. The output frequency will be f/2 (If f is clock frequency). It is
known as binary or mod -2 counter or bit ripple counter.

It has 2 unique output states (0 and 1).

2 bit asynchronous Up counter.

When two FFs are connected in series and output of one FF is act as clock for 2nd FF. So the state of 2nd FF will
change only when output and 1st FF is logic 1 and falling edge occur. The output frequency of Q1 is f/4(if f is
clock frequency).

It can generate 4 different unique states. This is known as divide by 4 circuits or mod 4 ripple counter.

Here output is taken as Q1(MSB) Q0(LSB).

Design of 3 bit Asynchronous up/down counter :
It is used more than separate up or down counter.
1. In this a mode control input (say M) is used for selecting up
and down mode.
2. A combinational circuit is required between each pair of
flip-flop to decide whether to do up or do down counting.

For n = 3, i.e for 3 bit counter –

Maximum count = 2n -1 and number of states are 2n.
Steps involve in design are :
Step 1 : Decision for Mode control input –
When M = 0, then Y= Q, therefore it will perform Up counting (As discussed above).
When M = 1, then Y= Q’ therefore it will perform Down counting (As discussed above).
Combinational circuit is required for deciding mode control(i.e whether counter will perform Up counting or
Down counting).
So the all possible combinations are –
K-map for finding output Y that will be given as clock to next FF.

K map for finding Y

Step 2 : Insertion of Combinational logic between every pair of FFs –

Up/Down Counter
Timing diagram :
Initially Q3 = 0, Q2 = 0, Q1 = 0.

Timing diagram for 3 bit asynchronous up/down counter

Case 1 – When M=0, then M’ =1.
Put this in Y= M’Q + MQ’= Q So Q is acting as clock for next FFs.
Therefore, the counter will act as Up counter.
Explanation of Up counter –
● The 1st FF is connected to logic 1. Therefore, it will toggle for every falling edge.
● The 2nd FF input is connected to Q1.Therefore it changes its state when Q1= 1 and there is falling
edge of clock.
● Similarly, 3rd FF is connected to Q2. Therefore, it changes its state when Q2= 1 and there is falling
edge of clock.
● By this we can generate counting states of Up counter.
● After every 8th falling edge the counter is again reaching to state 0 0 0.
Therefore, it is also known as divide by 8 circuit or mod 8 counter.
Case 2 – When M=1, then M’ =0.
Put this in Y= M’Q + MQ’= Q’. So Q’ is acting as clock for next FFs.
Therefore, the counter will act as Down counter.
Explanation of Down counter –
● The 1st FF is connected to logic 1. Therefore, it will toggle for every falling edge.
● The 2nd FF input is connected to Q’1.Therefore it changes its state when Q’1= 1 and there is falling
edge of clock.
● Similarly, 3rd FF is connected to Q’2. Therefore, it changes its state when Q’2= 1 and there is falling
edge of clock.
● By this we can generate counting states of down counter.
● After every 8th falling edge the counter is again reaching to state 0 0 0.
Therefore, it is also known as divide by 8 circuit or mod 8 counter.
●
Ring Counter
A ring counter is a typical application of the Shift register. The ring counter is almost the same as the shift
counter. The only change is that the output of the last flip-flop is connected to the input of the first flip-flop in
the case of the ring counter but in the case of the shift register it is taken as output. Except for this, all the other
things are the same.
No. of states in Ring counter = No. of flip-flop used

So, for designing a 4-bit Ring counter we need 4 flip-flops.

In this diagram, we can see that the clock pulse (CLK) is applied to all the flip-flops
simultaneously. Therefore, it is a Synchronous Counter. Also, here we use Overriding input
(ORI) for each flip-flop. Preset (PR) and Clear (CLR) are used as ORI. When PR is 0, then
the output is 1. And when CLR is 0, then the output is 0. Both PR and CLR are active low
signal that always works in value 0.
PR = 0, Q = 1

CLR = 0, Q = 0
These two values are always fixed. They are independent of the value of input D and the
Clock pulse (CLK). Working – Here, ORI is connected to Preset (PR) in FF-0 and it is
connected to Clear (CLR) in FF-1, FF-2, and FF-3. Thus, output Q = 1 is generated at FF-0,
and the rest of the flip-flop generates output Q = 0. This output Q = 1 at FF-0 is known as
Pre-set 1 which is used to form the ring in the Ring Counter.
This Presented 1 is generated by making ORI low and that time Clock (CLK) becomes
don’t care. After that ORI is made to high and apply low clock pulse signal as the Clock
(CLK) is negative edge triggered. After that, at each clock pulse, the preseted 1 is
shifted to the next flip-flop and thus forms a Ring. From the above table, we can say
that there are 4 states in a 4-bit Ring Counter.
4 states are:
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
Types of Ring Counter: There are two types of Ring Counter:
1. Straight Ring Counter: It is also known as One hot Counter. In this counter, the output of the
last flip-flop is connected to the input of the first flip-flop. The main point of this Counter is
that it circulates a single one (or zero) bit around the ring.Here, we use Preset (PR) in the first
flip-flop and Clock (CLK) for the last three flip-flops.
Types of Ring Counter: There are two types of Ring Counter:

1. Straight Ring Counter: It is also known as One hot Counter. In this counter, the output of
the last flip-flop is connected to the input of the first flip-flop. The main point of this
Counter is that it circulates a single one (or zero) bit around the ring.Here, we use Preset
(PR) in the first flip-flop and Clock (CLK) for the last three flip-flops.
1. Twisted Ring Counter – It is also known as a switch-tail ring counter, walking
ring counter, or Johnson counter. It connects the complement of the output of
the last shift register to the input of the first register and circulates a stream of
ones followed by zeros around the ring.Here, we use Clock (CLK) for all the
flip-flops. In the Twisted Ring Counter, the number of states = 2 X the number
of flip-flops.
What is a Sequence Generator and Its Working
What is a Sequence Generator?
Definition: A sequence generator is one kind of digital logic circuit. The main function of this is to generate a

set of outputs. Every output is one of a number of binary or Q-ary logic levels or symbols. The length of the

series may be indefinite otherwise fixed. A special kind of sequence generator is a binary counter. These

generators are utilized in a wide variety of applications like coding & control.
Why Sequence Generator is Required?

The sequence generator circuit is used to generate a prescribed series of bits in synchronization

through a CLK. This kind of generator is used as a code generator, counters, random bit

generators, sequence, and prescribed period generator. The basic design diagram of this is shown

below.

Sequence Generator Structure

The N-bit shift register outputs like Q0 through QN-1 are applied like the inputs to a combinational

circuit is known as the next state decoder. Here, the output of a next state decoder ‘Y’ is given as

the serial input to the shift register. The designing of the next state decoder is done based on the

sequence required.
Sequence Generator using Counters
The sequence generator block diagram using a counter is illustrated below. Here, the combinational circuit is the next state
decoder. The input of this state decoder can be obtained from the outputs of the FFs. Similarly, the outputs of this state decoder
are given as inputs to the flip-flops. Based on the number of FFs, the required sequence like 0’s or 1’s can be given and this can
be generated like 1011011.
The number of flip flops can be decided through the given sequence like

the following.

● First, count the number of zeros and ones in the given sequence.
● Select the high number of the two. And let this number will be ‘N’.
● The no. of flip flops can be calculated as N = 2n-1
● For instance, the given sequence is 1011011, where the number
of ones is 5 and the number of zeros is two. So choose a higher
one from them that is 5. So 5 = 2n-1, so n=4 FFs will be
necessary.
Registers
A Register is a collection of flip flops. A flip flop is used to store single bit digital data. For storing a large number
of bits, the storage capacity is increased by grouping more than one flip flops. If we want to store an n-bit word,
we have to use an n-bit register containing n number of flip flops.

The register is used to perform different types of operations. For performing the operations, the CPU use these
registers. The faded inputs to the system will store into the registers. The result returned by the system will store
in the registers. There are the following operations which are performed by the registers:

Fetch:
It is used

○ To take the instructions given by the users.

○ To fetch the instruction stored into the main memory.

Decode:
The decode operation is used to interpret the instructions. In decode, the operation performed on the
instructions is identified by the CPU. In simple words, the decode operation is used to decode the instructions.

Execute:
Execute:

The execution operation is used to store the result produced by the CPU into the memory. After storing this result, it is
displayed on the user screen.

Types of Registers
There are various types of registers which are as follows:
Shift Register
A group of flip flops which is used to store multiple bits of data and the data is moved from one flip flop to
another is known as Shift Register. The bits stored in registers shifted when the clock pulse is applied
within and inside or outside the registers. To form an n-bit shift register, we have to connect n number of
flip flops. So, the number of bits of the binary number is directly proportional to the number of flip flops.
The flip flops are connected in such a way that the first flip flop's output becomes the input of the other
flip flop.

A Shift Register can shift the bits either to the left or to the right. A Shift Register, which shifts the bit to
the left, is known as "Shift left register", and it shifts the bit to the right, known as "Right left register".

○ Serial In Serial Out

○ Serial In Parallel Out
○ Parallel In Serial Out
○ Parallel In Parallel Out
Serial IN Serial OUT
In "Serial Input Serial Output", the data is shifted "IN" or "OUT" serially. In SISO, a single bit is shifted at a time in either right
or left direction under clock control.

Initially, all the flip-flops are set in "reset" condition i.e. Y 3 = Y2 = Y1 = Y0 = 0. If we pass the binary number 1111, the LSB bit of
the number is applied first to the Din bit. The D3 input of the third flip flop, i.e., FF-3, is directly connected to the serial data
input D3. The output Y3 is passed to the data input d2 of the next flip flop. This process remains the same for the remaining
flip flops. The block diagram of the "Serial IN Serial OUT" is given below.

Block Diagram:

Operation

When the clock signal application is

disabled, the outputs Y3 Y2 Y1 Y0 = 0000.
The LSB bit of the number is passed to
the data input Din, i.e., D3. We will apply
the clock, and this time the value of D3 is
1. The first flip flop, i.e., FF-3, is set, and
the word is stored in the register at the
first falling edge of the clock. Now, the
stored word is 1000.
The next bit of the binary number, i.e., 1, is passed to the data input D 2. The second flip
flop, i.e., FF-2, is set, and the word is stored when the next negative edge of the clock
hits. The stored word is changed to 1100.
The next bit of the binary number, i.e., 1, is
passed to the data input D1, and the clock
is applied. The third flip flop, i.e., FF-1, is
set, and the word is stored when the
negative edge of the clock hits again. The
stored word is changed to 1110.

Similarly, the last bit of the binary number,

i.e., 1, is passed to the data input D0, and
the clock is applied. The last flip flop, i.e.,
FF-0, is set, and the word is stored when
the clock's negative edge arrives. The
stored word is changed to 1111.
Truth Table

Waveforms
Serial IN Parallel OUT
In the "Serial IN Parallel OUT" shift register, the data is passed serially to the flip flop, and outputs are fetched in a parallel
way. The data is passed bit by bit in the register, and the output remains disabled until the data is not passed to the data
input. When the data is passed to the register, the outputs are enabled, and the flip flops contain their return value

Below is the block diagram of the 4-bit serial in the parallel-out shift register. The circuit having four D flip-flops contains a
clear and clock signal to reset these four flip flops. In SIPO, the input of the second flip flop is the output of the first flip flop,
and so on. The same clock signal is applied to each flip flop since the flip flops synchronize each other. The parallel outputs
are used for communication.
Parallel IN Serial OUT
In the "Parallel IN Serial OUT" register, the data is entered in a parallel way, and the outcome comes serially. A four-bit
"Parallel IN Serial OUT" register is designed below. The input of the flip flop is the output of the previous Flip Flop. The input
and outputs are connected through the combinational circuit. Through this combinational circuit, the binary input B 0, B1, B2,
B3 are passed. The shift mode and the load mode are the two modes in which the "PISO" circuit works.

Load mode
The bits B0, B1, B2, and B3 are passed to the corresponding flip flops when the second, fourth, and sixth "AND" gates are
active. These gates are active when the shift or load bar line set to 0. The binary inputs B0, B1, B2, and B3 will be loaded into
the respective flip-flops when the edge of the clock is low. Thus, parallel loading occurs.

Shift mode
The second, fourth, and sixth gates are inactive when the load and shift line set to 0. So, we are not able to load data in a
parallel way. At this time, the first, third, and fifth gates will be activated, and the shifting of the data will be left to the right
bit. In this way, the "Parallel IN Serial OUT" operation occurs.
Parallel IN Parallel OUT
In "Parallel IN Parallel OUT", the inputs and the outputs come in a parallel way in the register. The
inputs A0, A1, A2, and A3, are directly passed to the data inputs D0, D1, D2, and D3 of the respective
flip flop. The bits of the binary input is loaded to the flip flops when the negative clock edge is
applied. The clock pulse is required for loading all the bits. At the output side, the loaded bits
appear.

Block Diagram