Received 23 August 2024, accepted 6 October 2024, date of publication 8 October 2024, date of current version 24 October 2024.

Digital Object Identifier 10.1109/ACCESS.2024.3476409

Two Independent Single-Loop Voltage Mode

Control Method for 3-Level Buck Converter
JUNE-BONG JEONG 1, CHAN-GYU KIM1 , JEONG-IL KANG 2, AND SANG-KYOO HAN 1
1 PowerElectronics System Laboratory (POESLA), College of Creative Engineering, Kookmin University, Seoul 02707, South Korea
2 Samsung Electronics Company Ltd., Suwon, Gyeonggi 16677, South Korea

Corresponding author: Sang-Kyoo Han ([email protected])

This work was supported in part by the Korea Institute of Energy Technology Evaluation and Planning (KETEP) Grant through the
Korea Government Ministry of Trade, Industry and Energy (MOTIE) (Development of High Efficiency Power Converter Based on
Multidisciplinary Design and Optimization Platform) under Grant 20212020800020, and in part by Samsung Electronics Company Ltd.

ABSTRACT Compared to a basic buck converter, the 3-level buck converter operates with the output inductor
at twice the switching frequency. Additionally, the voltage across its flying capacitor contributes to reducing
the slope of the inductor current. These factors can result in a reduction in the maximum output current
ripple by up to four times, enabling the use of a smaller output inductor. Moreover, the voltage stress on the
switches is only half of the input voltage. Therefore, the 3-level buck converter is advantageous for achieving
high efficiency and high power density. To maintain these advantages, the voltage across the flying capacitor
must be kept at half of the input voltage. Conventionally, this condition is usually ensured by using peak or
valley current mode control methods. However, these methods have complex control circuits or algorithms
and are vulnerable to noise interference because their operation is based on instantaneous peak or valley
current sensing. Additionally, different control configurations must be employed for M < 0.5 and M >
0.5, where M is the input-to-output voltage conversion ratio. In this paper, we propose a two independent
single-loop voltage mode control method that can guarantee the flying capacitor voltage remains at half of
the input voltage. The proposed control method is simple to implement and does not require current sensing
or complex control algorithms, allowing the use of simple and low-cost digital or analog controllers. The
method is also robust to noise interference because it only operates based on the output and flying capacitor
voltage. Furthermore, this method ensures normal operation across all values of M without changing the
control configuration. The experimental results from a 500 W-rated prototype confirmed the validity of the
proposed control method.

INDEX TERMS 3-level buck converter, high efficiency, high power density, slim converter, voltage mode
control.

NOMENCLATURE MF : Vin to flying capacitor voltage VFly conversion

fsw : Switching frequency. ratio.
Ts : Switching period. VFly_ero : Control signal of the VFly controller.
Di : Duty cycle of the main switch QHSi (i = A, B). Vo_ero : Control signal of the Vo controller.
VSW : Left side node voltage of the output inductor Lo . ro : Equivalent series resistance of the output
iLo : Current of the output inductor Lo . capacitor.
iCFly : Current of the flying capacitor CFly . Gcf (s): Transfer function of the VFly control compen-
RLoad : Load resistance. sator.
M: Input voltage Vin to output voltage Vo conversion Gcv (s): Transfer function of the Vo control compen-
ratio. sator.
Gda (s): Transfer function of the differential amplifier.
The associate editor coordinating the review of this manuscript and Gd (s): Transfer function of the computation delay and
approving it for publication was Khaled Ahmed . zero-order holder, including modulation gain.
2024 The Authors. This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.
For more information, see https://creativecommons.org/licenses/by-nc-nd/4.0/
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Goo (s): Transfer function of the output voltage control

signal perturbation 1vo_ero to output voltage
perturbation 1vo .
Gff (s): Transfer function of the flying capacitor volt-
age control signal perturbation 1vFly_ero to the
flying capacitor voltage perturbation 1vFly .
SC: Switched Capacitor.
LS: Low Side.
2PSC: 2-Phase Series Capacitor.
P-CMC: Peak Current Mode Control.
V-CMC: Valley Current Mode Control.
PWM: Pulse Width Modulation.

I. INTRODUCTION
The current trend toward large-screen, ultra-slim TVs has
increased demand for slim and compact circuit board designs,
including display panels. However, reducing the size of power
circuits is an extremely challenging task because it involves
optimizing components such as inductors and capacitors,
which consume a substantial amount of space. Achieving
ultra-slim designs for non-isolated dc-dc converters that are
used as post-regulators for LED drivers and mainboards in
TVs is particularly challenging. This difficulty arises primar-
ily due to the essential high-current power inductors in the
power supplies [1], [2].
Among the recognized non-isolated dc-dc converters, the
3-level switched capacitor (SC) buck converter depicted in
Fig. 1(a) only comprises switches and capacitors, providing
substantial benefits for the requirement of a slim design.
Additionally, because this configuration operates based on
the charge pump of capacitors, it features high efficiency,
simple operation, and ensures that the voltage stress on all
switches remains at half the input voltage [3], [4], [5], [6]. The
output voltage is minimally influenced by the pulse width or
operating frequency and remains constant at approximately
half of the input voltage. Additionally, it cannot effectively
regulate the output voltage in response to load variations and
input voltage fluctuations.
The 3-level buck converter displayed in Fig. 1(b) features a
circuit configuration with an output inductor for a 3-level SC FIGURE 1. Conventional buck converters for achieving high efficiency and
high power density: (a) 3-level SC buck converter, (b) 3-level buck
buck converter, and its output voltage can be controlled as converter, (c) 3-level LS buck converter, and (d) 2PSC buck converter.
Vo = DVin by adjusting the duty cycle D of QHSA and QHSB .
Furthermore, because the output inductor operates at twice
the switching frequency, it can reduce the maximum inductor converter, using the CL voltage as the input and generating
current ripple and the maximum output voltage ripple by up the Co voltage as the output. Therefore, the output voltage is
to four and eight times, respectively, compared to a basic maintained at Vo = 0.5DVin , which is determined by the duty
buck converter. This renders the 3-level buck converter highly cycle D of QLSA with the input-to-output voltage conversion
advantageous for achieving high power density. Moreover, ratio (M = Vo /Vin ), which is restricted to a maximum of
since the voltage stress on the switch can be guaranteed to 0.5. The maximum inductor current ripple and output voltage
be Vin /2, this results in lower switching losses and higher ripple can be reduced by half compared to that of a basic
efficiency [7], [8], [9], [10], [11]. buck converter, resulting in smaller values for Lo and Co .
The 3-level low side (LS) buck converter displayed in Additionally, this circuit is advantageous in terms of reducing
Fig. 1(c) functions similarly to a 3-level SC buck converter switching losses by ensuring that the switch voltage stress is
(with the exception of Lo and Co ) and maintains the voltage Vin /2 [12], [13].
across CL at approximately Vin /2. Moreover, the circuit, com- The 2-phase series capacitor (2PSC) buck converter dis-
posed of QLSA , QLSB , and Lo , functions as a synchronous buck played in Fig. 1(d) requires two inductors operating with a

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TABLE 1. Comparison of conventional buck converters.

FIGURE 2. Comparison of normalized output current ripple for each buck

converter.
a 3-level buck converter. Additionally, the 2PSC buck con-
verter’s maximum voltage conversion ratio is limited to 0.25,
whereas the 3-level buck converter is superior in terms of
securing a wide input-to-output operating range. Conversely,
the 3-level buck converter requires an additional means of
control for the flying capacitor voltage. This is because,
it only achieves optimum performance (in terms of output
current and voltage ripple) when the flying capacitor voltage
is maintained at half of the input voltage. Failure to maintain
this condition can result in increased current and voltage
ripple, as well as circuit losses.
Conventional control methods, such as peak and valley
current mode control (CMC), have been proposed to ensure
a balanced inductor current and maintain the flying capacitor
voltage at half of the input voltage. However, as detailed in the
FIGURE 3. Comparison of normalized output voltage ripple for each buck manuscript, these methods have complex control circuits (or
converter. algorithms) and are vulnerable to noise interference because
their operation is based on instantaneous peak or valley
180◦ phase difference. The output voltage is equivalent to that current sensing. Additionally, due to current subharmonic
of a 3-level LS buck converter and is determined by Vo = oscillations, these methods require slope compensation as an
0.5DVin using the duty cycle D of QHSA and QHSB . However, additional means of ensuring normal operation in all input
for correct operation, it is crucial to maintain the duty cycle and output voltage operating ranges [18], [19], [20]. Further-
below 0.5, which restricts the voltage conversion ratio M to more, different control configurations must be employed for
a maximum of 0.25. The maximum inductor current ripple M < 0.5 and M > 0.5, where M is the input-to-output voltage
can be reduced by up to two times compared to a basic buck conversion ratio.
converter. Additionally, its interleaved operation can reduce To overcome these limitations of the conventional CMC
the maximum output current ripple by up to four times com- methods, we propose a two independent single-loop voltage
pared to a basic buck converter. The maximum output voltage mode control method in this paper that guarantees the flying
ripple can also be reduced by up to eight times, equivalent to capacitor voltage remains at half of the input voltage across
that of a 3-level buck converter. This converter maintains the all M values, while simultaneously controlling the output
switch voltage stress at Vin /2, which is advantageous in terms voltage. The proposed control method is simple to implement
of reducing switching losses [14], [15], [16], [17]. and does not require current sensing or complex control algo-
Fig. 2 and Fig. 3 display comparisons of the normalized rithms. It is also robust to noise interference because it only
output current ripple and voltage ripple for each con- operates based on the output and flying capacitor voltage.
verter, respectively, including a basic buck converter and an Furthermore, the proposed control method ensures normal
interleaved buck converter. Table 1 outlines the main charac- operation across all M values without changing the control
teristics of conventional buck converters, where the 3-level configuration. This paper builds on our previous work [21] by
and 2PSC buck converters exhibit the best performance in providing a more detailed explanation. In Section II, we dis-
terms of output current and voltage ripple. However, it should cuss the voltage of the flying capacitor and the current of the
be noted that the 2PSC buck converter requires two inductors, inductor based on the operating principle of the 3-level buck
each with a maximum current ripple that is twice that of converter, addressing these aspects in greater detail compared

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inductor current is (Vin – VFly – Vo )/Lo , as depicted in Fig. 4(a)

and (b). During this period, the flying capacitor is charged by
the inductor current.
Mode 2: In Fig. 5(b), QLSA and QLSB are on, resulting in
VSW = 0 V. The voltages across QHSA and QHSB are Vin – VFly
and VFly , respectively, and the voltage across the inductor is
–Vo . Therefore, the slope of the inductor current is –Vo /Lo ,
as depicted in Fig. 4(a).
Mode 3: In Fig. 5(c), QHSB and QLSA are on, resulting in
VSW = VFly . The voltages across QHSA and QLSB are Vin –
VFly and VFly , respectively, and the voltage across the inductor
is VFly – Vo . Therefore, the slope of the inductor current is
(VFly – Vo )/Lo , as depicted in Fig. 4(a) and (b). During this
FIGURE 4. Key operation waveforms of a 3-level buck converter: (a) M < period, the flying capacitor is discharged by the inductor
0.5, (b) M > 0.5. current.
Mode 4: In Fig. 5(d), QHSA and QHSB are on, resulting in
VSW = Vin . The voltages across QLSA and QLSB are Vin – VFly
and VFly , respectively, and the voltage across the inductor is
Vin – Vo . Therefore, the slope of the inductor current is (Vin –
Vo )/Lo , as depicted in Fig. 4(b).
In the low-gain region, as depicted in Fig. 4(a), the con-
verter operates in the sequence mode 1 → mode 2 → mode 3
→ mode 2, while it operates in the sequence mode 1 →
mode 4 → mode 3 → mode 4 in the high-gain region,
as depicted in Fig. 4(b).

B. INDUCTOR CURRENT BALANCING CONDITION

In the low-gain region, the falling slope of the inductor current
is determined by Vo , as depicted in mode 2. In contrast, the
rising slope is determined by Vin – VFly – Vo or VFly – Vo ,
FIGURE 5. Four operating modes of a 3-level buck converter: (a) Mode 1, as depicted in modes 1 and 3. Similarly, the rising slope of
(b) Mode 2, (c) Mode 3, and (d) Mode 4.
the inductor current is determined by Vin – Vo in the high-gain
region, as depicted in mode 4. In contrast, the falling slope is
to [21]. Section III covers the conventional and proposed con- determined by −Vin + VFly + Vo or −VFly + Vo , as displayed
trol methods for ensuring the voltage of the flying capacitor in modes 1 and 3. Therefore, to ensure the current balance
remains at half of the input voltage, including a more detailed of the inductor for every switching half-cycle, the slope of
analysis and modeling of the proposed control method. The the inductor current should remain the same in the operating
experimental results from a 500 W-rated prototype to validate modes displayed in modes 1 and 3. Specifically, in the low-
the proposed control method are presented in Section IV, and gain region, Vin – VFly – Vo should equal VFly – Vo , whereas
the paper is concluded in Section V. −Vin + VFly + Vo should equal −VFly + Vo in the high-
gain region. Therefore, maintaining VFly at Vin /2 ensures the
II. 3-LEVEL BUCK CONVERTER current balance of the inductor for every switching half-cycle,
A. OPERATION PRINCIPLE as illustrated in Fig. 4. In both the low- and high gain regions,
A 3-level buck converter comprises two main switches (QHSA the volt-second balance of the inductor must be satisfied at the
and QHSB ) and two synchronous rectifiers (QLSA and QLSB ). steady state to ensure current balance in the inductor for every
QHSA and QLSA in addition to QHSB and QLSB form separate switching half- cycle. In the low-gain region, the volt-second
switching groups, each driven with a 180◦ phase difference balance of the inductor can be expressed as follows:
and operating complementarily, as depicted in Fig. 4. The



DA Vin − VFly − Vo = DB VFly − Vo
converter operates in two regions based on the voltage con-
= 0.5Vo (1-DA − DB ) . (1)
version ratio (M ): a low-gain region (M < 0.5) and a high-
gain region (M > 0.5), as depicted in Fig. 4(a) and (b). Each In the high-gain region, the volt-second balance of the induc-
region comprises four modes, as illustrated in Fig. 5. tor can be expressed as follows:
Mode 1: In Fig. 5(a), QHSA and QLSB are on, resulting
(1-DA ) Vo − VFly = (1-DB ) Vo − Vin + VFly



in VSW = Vin – VFly . The voltages across QHSB and QLSA
are VFly and Vin – VFly , respectively, and the voltage across = 0.5 (Vin − Vo ) (DA + DB − 1) .
the inductor is Vin – VFly – Vo . Therefore, the slope of the (2)

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VFly > Vin /2 than when VFly = Vin /2 (black line in Fig. 6(d)),
as indicated by the blue dotted line in Fig. 6(d).
Therefore, in the low-gain region, the inductor current
ripple 1iLo of a 3-level buck converter according to MF is
expressed as follows:
Vin
1iLo ,MF <0.5 = DA (1 − MF − M ) , (3)
Lo fsw
Vin
1iLo ,MF >0.5 = DB (MF − M ) , (4)
Lo fsw
where MF represents the Vin to VFly conversion ratio, and fsw
is the switching frequency. In the high-gain region, 1iLo of a
3-level buck converter is given by
Vin
1iLo ,MF <0.5 = (1-DA ) (M − MF ) , (5)
Lo fsw
Vin
1iLo ,MF >0.5 = (1-DB ) (M − 1 + MF ) . (6)
Lo fsw
The current-second balance of the flying capacitor CFly must
be satisfied at a steady state in both the low- and high-gain
regions. In the low-gain region, CFly is charged during the
duration DA Ts of the operation in mode 1 and discharged dur-
FIGURE 6. Relationship between VFly and inductor current: (a) M < 0.5,
ing the duration DB Ts of the operation in mode 3. Therefore,
VFly < Vin /2, (b) M > 0.5, VFly < Vin /2, (c) M < 0.5, VFly > Vin /2, and (d) M
> 0.5, VFly > Vin /2. based on Fig. 6(a) and (c), the following is satisfied:
(IA1 + IA2 ) DA Ts = (IB1 + IB2 ) DB Ts , (7)
As discussed previously, when VFly = Vin /2 is ensured from
where IA1 and IA2 are the start and end currents of the inductor
both (1) and (2), DA = DB can be satisfied. Furthermore, the
in mode 1, respectively, while IB1 and IB2 are the start and end
voltage conversion ratio M = D (where D = DA = DB ) can
currents of the inductor in mode 3. In the high-gain region,
be achieved, meaning the voltage conversion ratio of the 3-
CFly is charged during the duration (1 – DB )Ts of the operation
level buck converter is the same as that of the basic buck
in mode 1 and discharged during the duration (1 – DA )Ts of
converter. Consequently, when VFly = Vin /2 is ensured, all
the operation in mode 3. Therefore, based on Fig. 6(b) and (d),
switch voltage stresses are balanced at Vin /2, and the inductor
the following is satisfied:
current balance for every switching half-cycle is guaranteed.
(IA1 + IA2 ) (1-DB ) Ts = (IB1 + IB2 ) (1-DA ) Ts . (8)
C. RELATIONSHIP BETWEEN INDUCTOR CURRENT
Additionally, in the low-gain region, the slope of the inductor
RIPPLE AND FLYING CAPACITOR VOLTAGE
current during the duration 0.5(1 – DA – DB )Ts of the opera-
As illustrated in Fig. 6, an imbalance in the inductor current tion in mode 2 is determined by Vo . Thus, based on Fig. 6(a)
occurs if VFly is not maintained at Vin /2, resulting in increased and (c), the following is satisfied:
current stress and circuit losses due to the higher current
ripple. IA2 − IB1 = IB2 − IA1 . (9)
When VFly decreases, the slope of the inductor current in
mode 1 increases, while the slope of the inductor current in In the high-gain region, the slope of the inductor current
mode 3 decreases. Conversely, when VFly increases, the slope during the duration 0.5(DA + DB – 1)Ts of the operation in
of the inductor current in mode 1 decreases, while the slope of mode 4 is determined by Vin – Vo . Thus, based on Fig. 6(b)
the inductor current in mode 3 increases. Accordingly, in the and (d), the following is satisfied:
low-gain region, the inductor current ripple in mode 1 is larger IA1 − IB2 = IB1 − IA2 . (10)
when VFly < Vin /2 than when VFly = Vin /2 (black line in
Fig. 6(a)), as indicated by the red dotted line in Fig. 6(a). From (9) and (10), IA1 + IA2 = IB1 + IB2 is satisfied. There-
Similarly, the inductor current ripple in mode 3 is larger when fore, from (7) and (8), the following can be obtained:
VFly > Vin /2 than when VFly = Vin /2 (black line in Fig. 6(c)), DA = DB . (11)
as indicated by the blue dotted line in Fig. 6(c). In the high-
gain region, the inductor current ripple in mode 3 is larger Therefore, the duty cycles DA and DB are the same regard-
when VFly < Vin /2 than when VFly = Vin /2 (black line in less of VFly . In both the low- and high-gain regions, the
Fig. 6(b)), as indicated by the red dotted line in Fig. 6(b). volt-second balance of the inductor must be satisfied at the
Similarly, the inductor current ripple in mode 1 is larger when steady state for every switching cycle. In the low-gain region,

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FIGURE 7. Normalized inductor current ripple of the 3-level buck

converter according to flying capacitor voltage and output voltage.

where D = DA = DB , the volt-second balance of the inductor

can be expressed as follows:
D Vin − VFly − Vo + D VFly − Vo = (1 − 2D) Vo . (12)

In the high-gain region, where D = DA = DB , the volt-second

balance of the inductor can be expressed as follows:
(1-D) Vo − VFly + (1-D) Vo − Vin + VFly

= (2D − 1) (Vin − Vo ) . (13)

From (12) and (13), the voltage conversion ratio M = D
can be satisfied. Thus, from (3)–(6), the normalized 1iLo
according to M and MF is illustrated in Fig. 7. As discussed
previously, the inductor current ripple is the smallest at MF
= 0.5 and increases if MF becomes larger or smaller than
0.5, as displayed in Fig. 7. Consequently, if VFly is not guar-
anteed to be Vin /2, the voltage stress on the switch will not
be maintained at Vin /2 and there will be an imbalance in
inductor current. This will result in increased current stress
and circuit losses due to the higher current ripple, which is
disadvantageous in terms of reducing the size of the reactive
components. In the next section, we introduce the conven-
tional current mode control method and the proposed control
method to ensure MF = 0.5.

III. CONTROL METHOD

A. CONVENTIONAL CURRENT MODE CONTROL METHOD
Conventional control methods, such as peak and valley cur-
rent mode control (CMC), have been proposed to ensure a
balanced inductor current and maintain the flying capacitor
voltage at half of the input voltage, as depicted in Fig. 8. FIGURE 8. Block diagram of conventional CMC method: (a) 3-level buck
converter circuit diagram with CMC method applied, (b) block diagram of
Among these methods, Peak-CMC (P-CMC) turns on the P-CMC, and (c) block diagram of V-CMC.
main switch according to a clock signal (CLK) that operates
at twice the switching frequency. Moreover, it detects the
peak current of the inductor on a cycle-by-cycle basis to turn The outputs DQ and DQ’ of the D Flip Flop then generate the
off the main switch according to the High Limit signal gener- main gate signals PWM1 and PWM2 through AND or NAND
ated by comparing the output voltage control signal (Ve ) with logic gates with DCLK , respectively. This control mechanism
the inductor current, as depicted in Fig. 8(b). Specifically, maintains the peak current of the inductor at a constant level
a clock signal (DCLK ) of the D Flip Flop is generated by the and ensures that the voltage across the flying capacitor is
SR Flip Flop according to the CLK and High Limit signals. Vin /2. As depicted in Fig. 8(b), trailing-edge P-CMC can only

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be applied in the low-gain region. If P-CMC is to be imple-

mented in the high-gain region, the controller configuration
must be changed to leading-edge P-CMC. This is because
the turn-off signal of the main switch in the low-gain region
should occur after the turn-on signal. In contrast, the turn-off
signal of the main switch in the high-gain region should occur
before the turn-on signal.
In Valley-CMC (V-CMC), the main switch is turned off
according to a clock signal (CLK) that operates at twice the
switching frequency. Here, the valley current of the inductor
is detected instead of the peak current on a cycle-by-cycle
basis to turn on the main switch according to the Low Limit
signal generated by comparing the output voltage control
signal (Ve ) with the inductor current, as depicted in Fig. 8(c).
Specifically, a clock signal (DCLK ) of the D Flip Flop is
generated by the SR Flip Flop according to the CLK and
Low Limit signals. The outputs DQ and DQ’ of the D Flip
Flop then generate the main gate signals PWM1 and PWM2
through AND or NAND logic gates with DCLK , respectively.
This control mechanism maintains the valley current of the
inductor at a constant level and ensures that the voltage across
the flying capacitor is Vin /2. As depicted in Fig. 8(c), leading-
edge V-CMC can only be applied in the low-gain region.
If V-CMC is to be implemented in the high-gain region, the
controller configuration must be changed to trailing-edge V-
CMC. This is because the turn-on signal of the main switch
in the low-gain region should occur before the turn-off signal.
In contrast, the turn-on signal of the main switch in the
high-gain region should occur after the turn-off signal [7].
Additionally, due to current subharmonic oscillations, both
P-CMC and V-CMC require slope compensation to ensure
normal operation in all input and output voltage operating
ranges [18], [19], [20]. Moreover, as mentioned previously,
CMC methods have complex control circuits (or algorithms)
and are vulnerable to noise interference because they operate FIGURE 9. Block diagram of proposed two independent single-loop
based on instantaneous peak or valley current sensing. voltage mode control method: (a) 3-level buck converter circuit diagram,
(b) simplified block diagram of proposed control method, and
(c) proposed control method implemented using simple analog
B. PROPOSED TWO INDEPENDENT SINGLE-LOOP controllers.
VOLTAGE MODE CONTROL METHOD
The fundamental concept of the proposed control method
is as follows: As discussed in Section II, in the low-gain employed to regulate VFly and Vo , respectively. Accordingly,
region, when the duration DA Ts of operation in mode 1 is the proposed control method can be implemented with two
longer than the duration DB Ts of operation in mode 3, the independent single-loop voltage mode controllers for VFly
charging energy of CFly increases, resulting in a higher fly- and Vo , as depicted in Fig. 9. As displayed in the simplified
ing capacitor voltage VFly . Furthermore, as the durations of block diagram of the proposed control method in Fig. 9(b),
DA Ts and DB Ts in modes 1 and 3 increase, the transferred Vo control is achieved through the pulse width modulation
energy to the output side also increases, resulting in a higher (PWM) gate signal. This is generated by comparing the con-
output voltage Vo . Similarly, in the high-gain region, when trol signal Vo_ero , which is generated after compensating for
the duration (1 – DB )Ts of operation in mode 1 is longer than the error between sensed Vo and the control command Vref ,
the duration (1 – DA )Ts of operation in mode 3, the charging with the carrier signal VcarB . Independent from Vo control,
energy of CFly increases, resulting in a higher flying capacitor VFly control is achieved through the PWM gate signal. This
voltage VFly . Moreover, if the duration 0.5(DA + DB – 1)Ts is generated by comparing the control signal VFly_ero , which
of operation in mode 4 increases, the energy transferred to is generated after compensating for the error between sensed
the output side also increases, resulting in a higher output VFly and the control command Vin /2, with the carrier signal
voltage Vo . In summary, VFly is proportional to DA and Vo is VcarA , having a 180◦ phase difference with VcarB . Therefore,
proportional to both DA and DB . Therefore, DA and DB can be since the proposed control method is simple in terms of its

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FIGURE 10. Differences in CFly charging and discharging currents

according to the carrier signal during control operation (in the case of FIGURE 11. Differences in CFly charging and discharging currents
VFly < Vin /2, M < 0.5): (a) sawtooth wave carrier signal, (b) triangular according to the carrier signal during control operation (in the case of
wave carrier signal. VFly < Vin /2, M > 0.5): (a) sawtooth wave carrier signal, (b) triangular
wave carrier signal.

algorithm, it can be implemented with cost-effective and sim-

ple analog controllers, as depicted in Fig. 9(c). Moreover, the
method is robust against noise because it only operates based
on the output and flying capacitor voltages, without requiring
information on the peak or valley currents. Additionally,
since VFly and Vo are independently controlled, concerns
about noise are mitigated, even if the sensing positions for
VFly and Vo are spatially distant from each other, allow-
ing for flexibility in component placement in PCB design.
Furthermore, unlike conventional CMC methods, it ensures
normal operation across all input-to-output voltage conver- FIGURE 12. The 3-level buck converter with ESR of the output capacitor.

sion ratios without changing the control configuration. The

proposed control method exhibits different control dynamics control operation based on the carrier signal is the opposite
depending on the waveform of the carrier signal. Specifically, to that in Fig. 10 and 11.
compared to a sawtooth waveform, a triangular waveform
can secure a larger charging and discharging current of CFly C. MODELING OF THE 3-LEVEL BUCK CONVERTER WITH
during transient states, resulting in faster and superior control THE PROPOSED CONTROL METHOD
dynamics. In the following section, we provide an exam- When modeling the 3-level buck converter, the traditional
ple illustrating the transient characteristics according to the circuit-averaging method was adopted. Additionally, as illus-
waveform of the carrier signal. trated in Fig. 12, the equivalent series resistance (ESR) ro of
Fig. 10 and 11 illustrate examples of control operations the output capacitor is considered, influencing the dynamic
depending on the carrier signal during transient states when characteristics. The 3-level buck converter has four operating
VFly is lower than Vin /2 for M < 0.5 and M > 0.5, respec- modes, as displayed in Fig. 5. Next, we describe the voltage
tively. When VFly < Vin /2, the inductor current increases as and current relationships for the output inductor, flying capac-
DA increases due to the increase in VFly_ero_S to VFly_ero_T itor, and output capacitor in each operating mode.
caused by the flying capacitor voltage controller. In the low- In mode 1, where QHSA and QLSB switches turn on, the
gain region, the discharge current iCFly of the flying capacitor voltages and currents for each component are expressed as
remains constant, regardless of the carrier signal. In contrast, follows:
the charging current is larger when a triangular waveform  di
L
carrier signal is applied. In the high-gain region, the charging

 Lo o = Vin − vFly − vo

 dt
current iCFly remains constant regardless of the carrier signal.
 dvFly
CFly = iLo (14)
In contrast, the discharge current is smaller when a triangular  dt
 dvCo
 vo vr vo − vCo
waveform carrier signal is applied. Therefore, using the trian-  Co = iLo − = o = .

gular waveform instead of the sawtooth waveform (even with dt Rload ro ro
the same duty cycle) results in a faster dynamic response and In mode 2, where QLSA and QLSB switches turn on, the
improved transient characteristics. When VFly > Vin /2, the voltages and currents for each component are expressed as

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 J.-B. Jeong et al.: Two Independent Single-Loop Voltage Mode Control Method

follows:
 di
L

 Lo o = −vo

 dt
 dvFly
CFly =0 (15)
 dt
 Co dvCo = iL − vo = vro = vo − vCo .



o
dt Rload ro ro
In mode 3, where QLSA and QHSB switches turn on, the
voltages and currents for each component are expressed as
follows:
 di
L

 Lo o = vFly − vo

 dt
 dvFly
CFly = −iLo (16)
 dt
 dvCo
 vo vr vo − vCo
 Co = iLo − = o = .

dt Rload ro ro FIGURE 13. Control block diagram of the 3-level buck converter with
In mode 4, where QHSA and QHSB switches turn on, the proposed control method: (a) original system, (b) simplified system.

voltages and currents for each component are expressed as

follows: component, as follows: < iLo > = ILo + 1iLo , < vFly >=
 di
L
VFly + 1vFly , < vo > = Vo + 1vo , < vCo > = VCo +

 Lo o = Vin − vo 1vCo , < vro > = Vro + 1vro . Substituting (19), (20), and the

 dt
 dvFly average state variable into (18) and extracting the first-order
CFly =0 (17)
 dt small-signal components, the following can be derived:
 dv v
 Co Co = iL − o = ro = o

 v v − vCo  d1i
Lo
 Lo dt = 0.5Vin 1vFly_ero + 1vo_ero − 1vo
o


dt Rload ro ro 


In the low-gain region, the average variables for each com-
 d1vFly
= ILo 1vFly_ero − 1vo_ero


CFly
ponent’s voltage and current over one switching cycle, dt
 Co d1vCo = 1iL − 1vo = 1vro = 1vo − 1vCo


according to Fig. 4(a) and (14)–(16), can be expressed as


o
follows: dt Rload ro ro
 (21)
d iLo
= dA Vin + (dB − dA ) vFly − ⟨vo ⟩


 Lo
dt The 3-level buck converter with the proposed control method



d vFly

CFly = (dA − dB ) iLo is a system that comprises two input perturbations (1vFly_ero

 dt and 1vo_ero ) and two output perturbations (1vFly and 1vo ).
 d vCo

 ⟨vo ⟩ vr ⟨vo ⟩ − vCo By transforming (21) into the Laplace domain, the input
 Co
 = iLo − = o = ,
dt Rload ro ro and output perturbation relationship can be derived as
(18) follows:
where < · > represents the average variable. 1vo = Go (s) 1vFly_ero + 1vo_ero ,


(22)
According to Fig. 4(b), in the high-gain region, the average 1vFly = Gf (s) 1vFly_ero − 1vo_ero ,


(23)
variables for each component’s voltage and current over one
switching cycle can be expressed as derived from (14), (16), where Go (s) and Gf (s) are given by
and (17), and are given by (18). Additionally, when the peak- Vin ro

1

to-peak amplitude of the carrier signal is 1, the variables dA 2Lo s + ro Co
and dB correspond to the control signals vFly_ero and vo_ero , Go (s) =     , (24)
ro r
1 + Rload s2 + Loo + Rload1 Co s + 1
Lo Co
respectively. In this case, considering small signal perturba-
tions, both control signals can be expressed as follows: ILo
Gf (s) = . (25)
sCFly
vFly_ero = VFly_ero + 1vFly_ero , (19)
vo_ero = Vo_ero + 1vo_ero , (20) Accordingly, the overall system control block diagram
in Fig. 9 can be equivalently represented as depicted in
where VFly_ero and Vo_ero are dc values of the two control sig- Fig. 13(a). Here, Gcf (s) and Gcv (s) are the transfer functions
nals, and 1vFly_ero and 1vo_ero denote the forced small-signal of the flying capacitor voltage control compensator and the
perturbation components of the two control signals. Further- output voltage control compensator, respectively. Gda (s) is
more, considering small-signal perturbations, the average the transfer function of the differential amplifier for flying
state variable of the voltage and current for each component capacitor voltage sensing, as displayed in Fig. 9. If a micro-
can be expressed as the sum of a dc value and a small-signal controller is employed for PWM implementation (rather than

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J.-B. Jeong et al.: Two Independent Single-Loop Voltage Mode Control Method

FIGURE 14. Bode plots: (a) output voltage control loop, (b) flying
capacitor voltage control loop.
FIGURE 15. 500 W-rated prototype of a 3-level buck converter.

an analog PWM), the control loop should incorporate the

transfer function Gd (s), which represents the computation TABLE 2. Applied parameters in the experiment.

delay, zero-order holder, and modulation gain, as depicted in

Fig. 13. However, because the two control loops presented in
Fig. 13(a) influence each other, designing the controllers can
be complex.
Therefore, to facilitate controller design, the circuit model
of the 3-level buck converter and the two control loops have
been modeled together. This process is outlined as follows:
Considering small-signal perturbations, the perturbed
input and output signal relationship of the 3-level buck con-
verter in Fig. 13(a) can be expressed as follows:
1vo = Go (s) Gd (s) 1vFly_ero + 1vo_ero , (26)

1vFly = Gf (s) Gd (s) 1vFly_ero − 1vo_ero ,

(27)
1vFly_ero = −Gda (s) Gcf (s) 1vFly , (28)
and a gain margin of 8.6 dB. The crossover frequency for the
1vo_ero = −Gcv (s) 1vo . (29)
flying capacitor voltage control loop was selected as 1 kHz
From (26)–(29), the transfer function Goo (s) for the output with a phase margin of 46◦ and a gain margin of 20.8 dB.
voltage control signal 1vo_ero to the output voltage 1vo and
Gff (s) for the flying capacitor voltage control signal 1vFly_ero IV. EXPERIMENTAL RESULTS
to the flying capacitor voltage 1vFly are as follows: To validate the feasibility of the proposed control method,
we present experimental results obtained from a 500 W-
1 + 2Gda (s) Gcf (s) Gd (s) Gf (s)
 
Goo (s) = Go (s) Gd (s) rated prototype of the 3-level buck converter depicted in
1 + Gda (s) Gcf (s) Gd (s) Gf (s) Fig. 15. The proposed control method was implemented
= Gof (s) Go (s) Gd (s) , (30) with simple analog controllers and incorporated digital PWM
1 + 2Gcv (s) Gd (s) Go (s) imple-mented on the dsPIC33FJ09GS302, as displayed in
 
Gff (s) = Gf (s) Gd (s) Fig. 9(c). The specifications and main component informa-
1 + Gcv (s) Gd (s) Go (s)
= Gfo (s) Gf (s) Gd (s) . (31) tion for the experiment are detailed in Table 2. Given that
VFly was appro-ximately 0 V during the startup transients,
Accordingly, the overall system control block diagram in Vin was applied to QHSA and QLSA following the operation
Fig. 13(a) can be simplified as depicted in Fig. 13(b), with the in modes 1 and 3. Therefore, we needed to consider the max-
flying capacitor voltage control loop and the output voltage imum voltage stresses on QHSA and QLSA given the maximum
control loop displayed as independent configurations. input voltage of 70 V. For QHSB and QLSB , we considered a
With specifications of Vin = 66 V, Vo = 32 V, Rload = maximum steady-state operating voltage of 35 V because VFly
2.048 , fsw = 100 kHz, Lo = 1.36 uH, CFly = 20 uF, Co = was applied. Hence, we selected switches with different rated
500 uF, and ro = 13 m, the Bode plots for the output voltage voltages for each. By using an output inductor with a thick-
control loop and the flying capacitor voltage control loop are ness of 3.5 mm, we achieved an overall prototype thickness
displayed in Fig. 14(a) and (b), respectively. In the prototype of 6 mm, which was suitable for ultra-slim applications.
design, the crossover frequency for the output voltage control Fig. 16 displays the experimental steady-state waveforms
loop was selected as 12.9 kHz with a phase margin of 46.8◦ according to the input voltage Vin at full load, including

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 J.-B. Jeong et al.: Two Independent Single-Loop Voltage Mode Control Method

FIGURE 17. Experimental transient response waveform according to Vin

as the load changes from 25% to 75%, and vice versa: (a) Vin = 48 V,
(b) Vin = 66 V, and (c) Vin = 70 V.

FIGURE 16. Experimental steady-state waveforms according to Vin at full

load: (a) Vin = 48 V, (b) Vin = 66 V, and (c) Vin = 70 V.

the flying capacitor voltage VFly , the output inductor cur-

rent iLo , the output voltage Vo , and the gate signal of QHSB
(Vgs_HSB ). Fig. 16(a) and (c) display the cases when Vin is
at the minimum value of 48 V (M > 0.5) and the maximum
value of 70 V (M < 0.5), respectively. We achieved inductor
current balance for the switching half-cycle by maintaining
the average VFly at Vin /2, which is 24 V in Fig. 16(a) and 35 V
in Fig. 16(c). Accordingly, by maintaining the average VFly at
Vin /2 over the entire input voltage range, we achieved induc-
tor current balance for the switching half-cycle and controlled FIGURE 18. Measured efficiencies of a 3-level buck converter.
Vo at 32 V in a steady state, validating the feasibility of
the proposed control method. When Vin was at the nominal
value of 66 V (M ≈ 0.5), the inductor current ripple ideally resulting in practical inductor current ripple. Additionally, the
became zero, as illustrated in Fig. 2. However, as depicted in current ripple increased slightly due to a small current imbal-
Fig. 16(b), the inductor current followed a resonant waveform ance, although it remained sufficiently small to be considered
due to the resonance between CFly and Lo in modes 1 and 3, negligible.

151392 VOLUME 12, 2024

J.-B. Jeong et al.: Two Independent Single-Loop Voltage Mode Control Method

Fig. 19 displays the thermal performances of key com-

ponents according to Vin at full load, with measurements
taken at an ambient temperature of 28 ◦ C. The left and right
images depict the thermal performances of the inductor and
main switch, respectively, highlighting the components with
the highest recorded temperatures. Overall, the prototype
maintained a respectable temperature in the 60 ◦ C range, even
without a heatsink. The inductor’s heat generation was high-
est at 66.7 ◦ C when Vin = 48 V, where the inductor current
ripple was largest. In contrast, the inductor’s heat generation
was lowest at 48.2 ◦ C when Vin = 66 V, where the inductor
current ripple was smallest. These results indicated that the
efficiency measurements presented in Fig. 18 are reliable.

V. CONCLUSION
In this paper, we discussed the 3-level buck converter, which
offers significant advantages in terms of reducing the size of
reactive components that occupy a large volume. To ensure
the current balance of Lo for every switching half cycle, VFly
of the 3-level buck converter must be maintained at Vin /2.
To achieve current balance by maintaining VFly at Vin /2 across
all input-to-output voltage operating ranges while simul-
taneously controlling Vo , we proposed a two independent
single-loop voltage mode control method. This method con-
sisted of one controller to maintain VFly at Vin /2 and another
to regulate Vo .
Conventional CMC methods rely on instantaneous peak or
FIGURE 19. Thermal performances of key components according to Vin at valley current sensing, are susceptible to noise interference,
full load (ambient temperature: 28 ◦ C). Left images: inductor, right and have complex control circuits or algorithms. Further-
images: main switch with the highest recorded temperatures. (a) Vin =
48 V, (b) Vin = 66 V, and (c) Vin = 70 V. more, when both P-CMC and V-CMC are needed for M <
0.5 and M > 0.5, different control configurations must be
employed based on M (a leading-edge current control scheme
and a trailing-edge current control scheme), as depicted in
Fig. 17 displays the experimental transient response Fig. 8.
wave-form according to Vin as the load changed from 25% In contrast, the proposed control method is robust to noise
to 75%, and vice versa. The output voltage was effectively interference because it operates solely based on VFly and Vo .
regulated within a 3% range across the entire input voltage Moreover, it can also be implemented simply using low-cost
range during the load variations. At the minimum input volt- digital or analog controllers without the need for current
age of 48 V in Fig. 17(a), the output voltage variation was sensing. Additionally, the proposed approach ensures normal
the greatest, with an overshoot of 871 mV and an undershoot operation across all M values without changing the control
of 889 mV. The average flying capacitor voltage was suc- configuration.
cessfully maintained at Vin /2. These results confirmed that An experimental validation of the proposed control method
the proposed control method could effectively regulate both was conducted using a 500 W-rated prototype, where a high
the output voltage and the flying capacitor voltage, indicating efficiency of 97.35% was achieved at an input voltage of 66 V.
good load transient performance. Moreover, the 3-level buck converter significantly reduced
Fig. 18 displays the measured efficiencies for various loads the output inductor current ripple compared to conventional
according to the input voltage. As the voltage conversion ratio buck converters. This reduction allowed the use of very small
M became larger or smaller than 0.5, the inductor current inductors with a thickness of 3.5 mm, ultimately resulting in
ripple increased, as illustrated in Fig. 2, resulting in higher an ultra-slim design for the entire prototype, with a thickness
conduction losses. As displayed in Fig. 16, the inductor cur- of 6 mm.
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