PROGRAMMING

A microprocessor can conveniently be considered as a device, which reads binary coded information from its
input ports, manipulates this information according to a program stored within its memory, and subsequently
produces output ports.
The instructions, which make up the program are those selected by the programmer from the instruction set of
the microprocessor in order to perform the required task.
Before a programmer is able to either write or interpret the meaning of a program, it is necessary for him/her to
become familiar with the different types of machine instructions, which a typical microprocessor executes, and
to investigate their effect on the total system.

MICROPROCESSOR REGISTERS

The majority of machine instruction available with a microprocessor operates on or affects the state of various
internal registers, which make up the microprocessor. Before a program can be written for a particular
microprocessor, therefore, it is necessary to acquire knowledge of those processor registers, which are
accessible or are affected by the machine instructions.

B C

D E

H L

F IM
Figure p-01
Stack pointer SP

Program Counter PC

A is an 8-bit arithmetic register (accumulator).

B, C, D, E, are four 8-bit general-purpose registers.
F is an 8-bit flags register (modified by ALU operations)
IM is an 8-bit interrupt control register.
HL are two 8-bit registers, which are normally used to form a 16-bit memory pointer.
SP is the stack pointer register this contains a 16-bit memory address, which display/points to the top of a
system stack.
PC is the program counter register, which contains a 16-bit memory, addresses which points to the next
instruction to be executed.

ASSEBLY LANGUAGE.

It is extremely tedious and time consuming to represent each machine instruction in its binary coded form. A
convenient representation of an instruction is symbolic assembly language equivalent.
When each instruction is represented in this form, programs are far more readable (and hence understandable)
but, since there is one-for-one correspondence between an assembly language instruction and a machine code
instruction, it is also very straightforward to convert between one form and the other. Writing of programs in the
form that the machine can directly execute is referred to as machine language programming.
A typical assembly language instruction has the following format:

LABEL: OPERATION MNEMONIC, OPERANDS, COMMENTS

The LABEL is an optional symbolic address for the instruction, which is particularly useful for branching type
instructions.
Each machine instruction is assigned a corresponding OPERATION MNEMONIC, which effectively tells the
programmer the specific operation to be performed by the instructions or the functions of registers. Examples of
mnemonics are ADD for Add operation, SUB for subtraction operation, LD for load operation, JMP for jump
operation, A for Accumulator and X for Index register.
OPERAND (S) is either a value on which this operation is to be carried out or the memory location(s) where
the value(s) can be found.

The COMMENTS field is for optional comments and is simply to facilitate understanding and enhance the
readability of the complete program and does not influence the machine code resulting from the assembly
instruction. Intel 8085 is an 8-bit microprocessor, since it handles 8-bit data at a time. A memory location for
Intel 8085 microprocessor is designed to accommodate 8-bit data. If 16-bit data are to be stored, they are stored
in consecutive memory locations. The address of a memory location is of 16 bits.

The various ways to specify data in the instructions are:

 8-bit or 16-bit data may be directly given in the instructions.
 The address of the memory location, I/O port or I/O device may be given.
 In some instructions only one register is specified. The content of the specified register is one of the
operands. It is understood that the other operand is in the accumulator.
NB
1 Some instructions specify two or more registers. The contents of the registers are the required data.
2 In some instructions data is implied. The most instructions of this type operate on the content of the
accumulator.

Due to different ways of specifying data in the instruction, the machine codes of all instructions are not of the
same length. There are three types of Intel 8085 instructions as described below:
 Single-byte instruction
 Two-byte instruction
 Three-byte instruction.
When instructions are written in machine code form they are in one-byte, two-byte or three-bytes. In a single
byte instruction only opcode is there. For example:
Single byte Instruction
MOV A, B Move the content of register B to register A.
78 is the opcode for MOV A, B
For this instruction the operand is in the general purpose registers. Besides the operation to be performed, the
opcode also specifies the register, which contain operands.
Two - byte Instruction
In a two-byte instruction, the 1st byte of the instruction is its opcode while the 2nd byte is either data or address.
For example:
i) MVI B, 0A MOVes 0A to register B
06,0A represents MVI B, 0A in the code form.
The 1 byte 06 is the opcode for MVI B and the 2nd byte 0A is the data, which is to be moved to register B.
st

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ii) IN 21 Reads data at port A.
DB, 21 represents IN 21 in the code form. DB is the opcode for the instruction IN and 21 is the
address of a port (the port A of Intel 8155).

Three- byte Instruction

In three-byte instructions the 1st byte of the instruction is in its opcode and the 2nd and 3rd bytes are either 16-
bit data or 16-bit address. For example:

i) LXI H, 2500H Loads H-L pair with 2500H

21, 00, 25 represents LXI H, 2500 in the code form. The 1st 21 is the opcode for the instruction LXI H.
the 2 byte 00 is 8-LSBs of the data (2500 H), which is loaded into register L. The 3rd byte 25 is 8 MSBs of the
nd

data (2500 H), which is loaded into register H.

ii) LDA 2015 H. Get the content of the memory 2015 H into accumulator.
3A, 15, 20 LDA 2015 H in the code form. The 1st byte 3A is the opcode for the instruction LDA.
The 2 byte 15 is 8 LSBs of the address of the memory location 205 H. the 3rd byte 20 is 8 MSBs of the address
nd

of the memory location 2015 H.

ADDRESSING MODES

Each instruction requires certain data on which it has to operate. There are various techniques to specify the
address of the data. These techniques are called addressing modes. Intel 8085 uses the following addressing
modes:

1. DIRECT ADDRESSING
In this mode of addressing the address of the operand (data) is given in the instruction itself. For example;

i) STA 3450 H Stores contents of the accumulator in the memory location 3450 H
32, 50, 34 is the STA 3450 H instruction in the code form. In this instruction the 2nd and 3rd bytes
specify the address of the memory location where data is to be placed. Here, it means that the source for the
data is the accumulator.

ii) IN 22H read data from the Port B.

DB, 22 represents IN 22H in code form. In this instruction 22 is the address for the port B of Intel
8155 I/O port from where the data is to be read. Here, it is implied that the destination is the accumulator.
The 2nd byte of the instruction specifies the address of the port.

2. REGISTER ADDRESSING
In register addressing mode the operands are in the general purpose registers. The opcode
specifies the address of the registers in addition to the operation to be performed. For
example: -

i) MOV A, B MOVes the content of register B to register A.

78 Is the instruction in the code form.

ii) ADD B adds the content of register B to the content of register A.

80 The instruction in the code form. In (i) the opcode for MOV A, B is 78H. Besides the
operation to be performed the Opcode also specifies the registers, which contain data.

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In (ii) the opcode for ADD B is 80H. In this instruction one of the operands is register B (its content is one of
the data), which is indicated in the instruction itself. In these types of instructions (Arithmetic or Data
Manipulation group), it is assumed that the other operand is in the accumulator.

3. REGISTER INDIRECT ADDRESSING

In this mode of addressing the address of the operand are specified by a register pair, for
Example: -
i) LXI H, 2540H Loads H-L pair with 2540H.
MOV A, M Moves the content of the memory location, whose address is in H-L
pair (i.e. 2540 H) to the accumulator.
HLT Halt.

In this program the instruction MOV A, M is an example of register indirect addressing. For this instruction
the operand is in the memory. The address of the memory is not directly given in the instruction. The address
of the memory resides in H-L pair and this has already been specified by an earlier instruction in the program
i.e. LXI H, 2540H.

ii) LXI H, 2540 H Load H-L pair with 2540 H

ADD M Add the content of the memory location, whose address is in H-L
pair (i.e. 2540 H), to the content of the accumulator.
HLT Halt.
In this program the instruction ADD M is an example of register indirect addressing.

4. IMMEDIATE ADDRESS
In immediate addressing mode the operand is specified within the instruction itself. For example,
i) MVI A, 0A H Move 0A in register A
3E, 0A The instruction in the code forms.

ii) ADI 0F H Add 0F to the content of the accumulator.

C6, 0F The instruction in the code forms.

In these instructions the 2nd byte specifies data.

5. IMPLICIT ADDRESSING
These are certain instructions, which operate on the content of the accumulator. Such instructions do not require
the address of the operand. For example, CMA, RAL, RAR etc.

Intel 8085 INSTRUCTIONS

An instruction is a command to the computer to perform a specific task on a given data. Instruction set is the
collection of instructions that a computer recognizes. The programmer writes a program in assembly language
using these instructions.
The instructions are classified into the following groups:
 Data Transfer Group
 Data Arithmetic (or Manipulation) Group
 Transfer of Control Group

1. Data Transfer Group

Instructions, which are used to transfer data from one register to another register, from memory to register or
register to memory, come under this group. Examples include:
i) MOV r1, r2 Move data: Move contents of one register to another.
[r1] [r2]
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The contents of register r2 are moved to register r1. For example the instruction MOV A, B moves the content of
register B to register A. The MOV B, A moves the content of register A to register B. No flag is affected.

ii) MOV r, M Move the content of memory to register.

[r] [[H-L]]

The content of the memory location, whose address is in H-L pair, is moved to register r.
LXI H, 2001H Load H-L pair by 2001H.
MOV B, M Move the content of the memory location 2001 H to register B.
HLT Halt.

In this example the instruction LXI H, 2001 H loads H-L pair with 2001 H which is the address of a memory
location. Now the instruction MOV B, M will move the content of the memory location 2001 H to register B.

iii) MOV M, r Move the content of register to memory.

[[H-L]] [r]

The content of register is moved to the memory location addressed by H-L pair. For example: MOV M, C
moves the content of register C to the memory location whose address is in H-L pair.

iv) MVI r, data Move immediate data to register.

[r] data.

The 1st byte of the instruction is its opcode. The 2nd byte of the instruction is the data, which is moved to register
r. For example,
MVI A, 06 moves 06 to register A. In the code form it is written as 3E, 06. The op-code for MVI A is 3E
and 06 is the data, which is to be moved to the register A.

v) MVI M, data Move immediate data to memory.

[[H-L]] data.

The data is moved to the memory location whose address is in H-L pair. For example,
LXI H, 2600 H Load H-L pair with 2600 H
MVI M, 1A H Move 1A to the memory location 2600 H.
HLT Halt.

In this example, the instruction LXI H, 2600 H loads H-L pair with 2600 H, which is the address of a
memory location. Now the instruction MVI M, 1A will move1A to memory location 2600 H.
In code form it is written as 36, 1A. The opcode for MVI M is 36 and 1A is the data, which is to be, moved to
the memory location 2600 H.

vi) LXI rp, data 16 Load register pair immediate.

[[H-L]] data bits, [rh] 8MSBs of data
[rl] 8LSBs of data
This instruction loads 16-bit immediate data into register pair rp. This instruction is for register pair; only high-
order register is mentioned after the instruction. For example, H in the instruction LXI H stands for H-L pair.
Similarly, LXI B is for B-C pair. LXI H, 2500 H loads 2500 H into H-L pair. H with 2500 H denotes that the
data 2500 is in hexadecimal. In the code form it is written as 21,00,25. The 1st byte of the instruction, 21 is the

5
opcode for LXI H. The 2nd byte 00 is the 8 LSBs of the data and it is loaded into register L. The 3rd byte 25 is
the 8 MSBs of the data and it is loaded into register H.

vii) LDA addr. Load accumulator direct.

[A] [addr]

The content of the memory location, whose address is specified by the 2nd and 3rd bytes of the instruction, is
loaded into the accumulator.
The instruction LDA 2601 H will load the content of the memory location 2601 H into the accumulator. In the
code form it is written as 3A, 01, 26.
The 1st byte 3A is the opcode of the instruction. The 2nd byte 01 is the 8 LSBs of the memory address. The 3rd
byte 24 is the 8 MSBs of the memory address.

viii) STA addr Store accumulator direct.

[Addr] [A]

The content of the accumulator is stored in the memory location whose address is specified by the 2nd and 3rd
bytes of the instruction. STA 3000H will store the contents the accumulator in the memory location 2000 H.

ix) LHLD addr Load H-L pair direct.

[L] [addr], [H] [addr +1]

This instruction will load the HL register pair with two successive bytes starting with the specified address. The
low byte from the specified address goes into the L register, the high byte from the next address goes into the H
register. The content of the memory location, whose address is specified by the 2nd and 3rd bytes of the
instruction, is loaded into register L. The content of the next memory location is loaded into register H. For
example,

LHLD 2550 H
Will load the content of the memory location 2550 H into register L. The content of the memory location 2551
H is loaded into register H. If
M2550 H = 39 H and M2551 H = 4B H
Then an LHLD 2550 H produces
HL = 4B39 H

39 H 2550 H
4B H 2551 H

Figure p-02

x) SHLD addr Store H-L pair direct.

[Addr] [L], [addr + 1] [H]

This is similar to LHLD except that the two bytes in the HL register pair are stored at the specified address and
the next higher address. The content of register L is stored in the memory location whose address is specified by
the 2nd and 3rd bytes of the instruction. For example,

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SHLD 2650 H will store the content of register L in the memory location 2650 H. The content of register H is
stored in the memory location 2651 H. If HL = 1A2B
An SHLD 2650 H results in
M2650 H = 2B H and M2651H = 1A H.

2B H 2650 H
1A H
2651 H

Figure p-03

xi) STAX Store accumulator indirect

[[rp]] [A]

The content of the accumulator is stored in memory location whose address is in the register pair rp. STAX
instruction has two forms:
STAX B
STAX D
Where B stands for BC and, D for DE. This indirect instruction loads the contents of the accumulator into the
memory location addressed by the specified register pair. In other words, the BC register pair or the DE register
pair act like a pointer. For example,

if A = DD H
BC = 3000 H
Execution of an STAX B will produce
M3000 H = DD H
In this case the BE register pair acts like a pointer as shown in the diagram.

BC

3000 H DD H

Figure p-04

xii) LDAX rp Load accumulator indirect.

[A] [[rp]]
LDAX is similar to STAX, except that the addressed contents of the memory are loaded into the accumulator.
Either LDAX B or LDAX D may be used. The content of the memory location, whose address is in the register
pair rp, is loaded into the accumulator. For example, LDAX B will load the content of the memory location,

7
whose address is in B-C pair, into the accumulator. This instruction is used only for B-C and D-E register pairs.
If
DE = 4900 H
M = FD H
Then execution of LDAX D results in
A = FD H
DE
4900 H
FD H

Figure p-05

This time the DE register acts like a pointer as shown in the figure.

xiii) XCHG Exchange the contents of H-L with DE register pairs.

[H-L] [D-E]
This instruction will exchange the contents of the HL and DE register pairs. The contents the H-L pair are
exchanged with contents of D-E pair. For example, if
DE = 3456 H
HL = 789A H
Then execution of an XCHG results in
DE = 789A H
HL = 3456 H

xiv) SPHL Load the contents of HL pair to Stack pointer.

[SP] [HL]
The SPHL instruction loads the contents of the HL register pair into the stack pointer. Given
SP = 2322H and HL = 7502 H
Execution of SPHL produces
SP = 7502 H.
xv) XTHL exchange the contents of HL pair with the two bytes at the top of the stack)
[SP 2 bytes of stacktop] [HL]
Suppose the stack pointer is at 2103H as shown in the figure below, the two bytes at the top of the stack are FD
H (low byte) and AE H (high byte). If
HL = 3059 H
then execution of an XTHL will result in
HL = AEFD H
And the top of the stack will contain 30 H and 59 H, as shown in the figure.

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 59 H
2100 H
2100 H FD H
AE H 30 H
79 H
79 H 58 H
58 H
BC H
BF H
0A H 0A H

Figure p-06a Figure p-06a

The XTHL preserves the contents of the stack pointer; from the figure the stack pointer contains 2100 H after
the XTHL is executed.

xvi) PCHL Load program counter with contents of register pair H-L
[PC] [HL]
This is an unconditional jump instruction. When this is instruction is executed, the contents of the HL register
pair are loaded into the program counter. For example, if
PC = 3000 H and HL = 299A H
A PCHL results in
PC = 299A H.
Therefore, the next instruction cycle will fetch the instruction at address 299A H.

2. Arithmetic (Manipulation) Group

Since the accumulator is only 8 bits wide, its contents can represent unsigned numbers from 0 to 255 or
unsigned 2’s complement numbers from –128 to +127. Whether signed or unsigned binary numbers are used,
the programmer needs to detect overflows, sums or differences that lie outside the normal range of the
accumulator. This is where the carry flag comes in. There are two instructions used to control the carry flag.

i) The STC instruction will set the CS flag if it is not already set. (STC stands for set carry.) so, if
CS = 0
The execution of a STC instruction produces
CS = 1.

ii) The other carry-flag instruction is the CMC, which stands for complement the carry. When executed, a
CMC complements the value of CS. If CS = 1, CMC produces a CS of 0. On the other hand, if CS = 0, CMC
results in a CS = 1.
If one wants to reset the carry flag and its current status is unknown, one should set it, then complement it. That
is, execution of
STC followed by CMC guarantees that the final value of CS will be 0 if the initial value of CS is unknown.

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iii) ADD Instructions
The format of the ADD instruction is
ADD r.
[A] [A] + [r]
Where r = A, B, C, D, E, H, or L. This instruction adds the contents of the specified register to the accumulator
contents. The sum is stored in the accumulator and the carry flag is set or reset, depending on whether there is a
final carry or not.
For example, if A = 1111 0001 and C = 0000 1001

The instruction ADD C produces the binary addition

1111 0001
+0000 1001
1111 1010 there is no final carry; therefore, at the end of the instruction cycle,
CS = 0 and A = 1111 1010.
Suppose A = 1111 1111 and H = 1000 0000. Then execution of ADD H
1111 1111
+1000 0000
10111 1111 At the end of the instruction cycle
CS = 1 and A = 0111 1111

iv) ADC Instruction

The ADC instruction (add with carry) is formatted like:
ADC r
[A] [A] +[r] + [CS]
where r = A, B, C, D, E, H, or L. This instruction adds the contents of the specified register plus the carry flag
to the contents of the accumulator. Because it includes the CS flag, the ADC instruction allows the programmer
to add numbers outside the unsigned 0 to 255 range or the signed –128 to +127 range. For example, suppose
A = 1000 0011
B = 0001 0010
And CS = 1
Then execution of ADC B
Produces the following addition:
1000 0011
0001 0010
+ 1
1001 0110 Therefore, the new accumulator and carry flag contents are CS = 0 A = 1001 0110

v) ADD M
[A] [A] + [[H-L]]

The contents of the memory location addressed by the H-L pair are added to the content of the accumulator. The
sum is placed in the accumulator.
vi) ADI data
[A] [A] + data

The immediate data is added to the content of the accumulator. The 1st byte of the instruction is its opcode. The
2nd byte of the instruction is data, and it is added to the content of the accumulator. The sum is placed in the
accumulator. For example the instruction,
ADI 0A H
Will add 0A H to the content of the accumulator and place the result in the accumulator. In code form the
instruction is written as C6, 0A.
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vii) ACI data (Add with carry immediate data to accumulator).
[A] [A] + data + [CS].
The 2nd byte of the instruction (which is data) and the carry status are added to the content of the accumulator.
The sum is placed in the accumulator.

DAD rp. (Add register pair to H-L pair).

[H-L] [H-L] + [rp]

The contents of register pair rp are added to the contents of H-L pair and the result is placed in H-L pair. The
contents of the source register pair are not altered. If the result is larger than sixteen bits the CY flag is set. No
other flags are affected.
DAD stands for double-add. This instruction has three forms:
DAD B
DAD D
DAD H
Where B stands for BC
D stands for DE
H stands for HL
The DAD instruction adds the contents of the specified register pair to the contents of the HL register pair; the
result is then stored in the HL register pair. For instance, given
BC = F631H
HL = 0005H

The execution of a DAD B produces HL = F636H

F631H and 0003H are added to get F636H. The result is stored in the HL register pair.
DAD instruction affects the CY flag. If there is a carry out of the HL register pair, the CY flag is set; otherwise
it is reset. E.g. if
DE = 0002H
HL = FFFFH
A DAD D will result in
HL = 000FH
CY = 1
Incidentally, a DAD H has the effect of adding the data in the HL register pair to itself. i.e. a DAD H will result
in HL doubles the value of HL. If HL = 1235H ,
a DAD H results in
HL = 246AH
Example: Assume register pair HL contains 0242H. Multiply the contents by 2.
Instruction: DAD H
Before instruction After instruction
H L DAD operation H L
02 42 0242 04 84
+ 0242
0484
Assume register pair HL is cleared. Transfer the stack pointer (register) that points to memory location 2099 H
to the HL register pair.

Subtraction in binary has four basic rules to be followed:

0 – 0 = 0, 1 – 1 = 0, 1 – 0 = 1 and 102 – 1 = 1

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When subtracting numbers, one has to sometimes borrow from the next higher column. A borrow is required in
binary only when trying to subtract a 1 from a 0. In this case, when a 1 is borrowed from the next higher
column, a 102 is created in the column being subtracted, and the last of the four basic rules must be applied.
For example;
1 12 310
a) - 0 12 -110
1 02 210

b) 1 12 310
1 02 - 210
0 12 110
No borrows were required in this example. 012 is the same 12.
c) 1 0 12 510
0 1 12 - 310
0 1 02 210

When a 1 is borrowed
A 0 is left (0 – 0 = 0)
Borrow 1 from next column making a 10 in this column.
1 10 1 (10 – 1 = 1)
0 11 (1 – 1 = 0)
0 1 0

1’s and 2’s Complement

The 1’s complement of a binary number is found by simply changing all 1’s to 0’s and all 0’s to 1’s.
Binary Number 1’s complement
10101 01010
10111 01000
111100 000011
11011011 00100100
1’s complement subtraction.

Subtraction of binary numbers can be accomplished by the direct method or by using the 1’s complement
method, which allows us to subtract using only addition. To subtract a smaller number from a larger number,
the 1’s complement method is as follows:
 Determine the 1’s complement of the smaller number.
 Add the 1’s complement to the larger number.
 Remove the carry and add it to the result. This is called end-around carry.
Example:
Subtract 100112 from 110012 using the 1’s complement method. Show direct subtraction for comparison.

Solution.
Direct subtraction 1’complement Method
100112 11001
100112 01100 1’s complement of 10011
001102 100101
+1 Add end-around carry
00110 Final answer.
To subtract a larger number from a smaller one, the 1’s complement method is as follows:
 Determine the 1’s complement of the larger number.
 Add the 1’s complement to the same number.
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 The answer has an opposite sign and is the 1’s complement of the result. There is no carry.
Example
Subtract 1101 from 1001 using the 1’s complement method. Show direct subtraction for comparison.
Solution
Direct subtraction 1’s complement
1001 1001
- 1101 + 0010 1’s complement of 1101
- 0100 1011 Answer in 1’s complement
form and opposite in sign.
-0100 Final result
The 1’s complement method is particularly useful in arithmetic logic circuits because subtraction can be
accomplished with an adder. Also, the 1’s complement of a number is easily obtained by inverting each bit in
the number.

2’s complement

Adding 1 to the 1’s complement finds the 2’s complement of a binary number. For example
Binary number 2’s complement
110 001 1’s complement
+ 1 Add 1
010 2’s complement of 110

10101 01010 1’s complement

+ 1 Add 1
01011 2’s complement.
An alternative method of obtaining the 2’s complement is as shown for the binary number 1101011101000.
1. Start at the right and write the bits as they are up to and including the first 1.
2. Take the 1’s complement of the remaining bits.
First 1 going right to left.
001010001 1000

1’s complement These bits remain as they were

of original bits.

2’s Complement Subtraction

To subtract a smaller number from a larger one, the 2’s complement method is applied as follows:
 Determine the 2’s complement of the smaller number.
 Add the 2’s complement to the larger number.
 Discard the carry (there is always a carry in this case).
Example: Subtract 10112 from 11002 using 2’s complement method. Show direct subtraction for comparison.

Solution: direct method 2’s complement method

1100 1100
-1 0 1 1 + 0 1 0 1 2’s complement of 1011
0001 10001
Final answer
0001
To subtract a larger number from a smaller one, the 2’s complement method is applied as follows:
 Determine the 2’s complement of the larger number.
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 Add the 2’s complement to the smaller number.
 There is no carry. The result is in 2’s complement form and is negative.
 To get an answer in the true form, take the 2’s complement and change the sign.

Example:
Subtract 111002 from 100112 using the 2’s complement method.

Solution:
Direct subtraction 2’s complement method
10011 10011
-1 1 1 0 0 + 0 0 1 0 0 2’s complement of 11100
-0 1 0 0 1 1 0 1 1 1 no carry; 2’s complement
of answer
-01001
Final answer.
Example:
Subtract 10112 from 11002 using the 2’s complement method. Show direct subtraction for comparison.

Solution
Direct subtraction. 2’s complement method
1100 1100
-1011 +0101
0001 10001
SUB r (Subtract register from accumulator). 0001
[A] [A] – [r]. Final answer
The content of the register r is subtracted from the content of the accumulator, and the result is placed in the
accumulator. The SUB instruction is formatted as
SUB reg.
Where reg. = A, B, C, D, E, H, or L. This instruction will subtract the contents of the specified register from the
accumulator contents; the result is stored in the accumulator. If a final borrow occurs, the CY flag is set. If there
is no borrow, the CY flag is reset. In other words, during subtraction the CY flag functions as a borrow flag.
For example, if

A = 0000 1111 and C = 0000 0001 then,

SUB C results in
0000 1111
-0000 0001
0000 1110
Notice that there is no final borrow. In terms of 2’s complement addition, the foregoing subtraction appears like
this:
0000 1111
+ 1111 1111
10000 1110
The final CARRY is 1, but this is complemented during subtraction to get a CY of 0. This is why the execution
of SUB C produces

CY = 0 A = 0000 1110
For example
If A = 0000 1100 and C = 0001 0010

14
Then a SUB C produces
0000 1100
-0001 0010
11111 1010
Notice the final borrow. This borrow occurs because the contents of the C register (decimal 18) are greater than
the contents of the accumulator (decimal 12). In terms of 2’s complement arithmetic, the foregoing looks as

0000 1100
-1110 1110
01111 1010
In this case CARRY is 0 and CY is 1. the final register and flag contents are

CY = 1 and A = 1111 1010

Example .
Assume the contents of the accumulator are 37H and the contents of register C are 40H. Subtract the contents
of register C from the accumulator.

Instruction: SUB C
(C): 40H = 0100 0000
2’s complement (C): = 1100 0000
(A) 37H = 0011 0111
0/ 1111 0111
Complement Carry: 1/ 1111 0111 = F7H
Flags: S = 1, Z = 0, AC = 0, P = 0 CY = 1
The result, as a negative number, will be in 2’s complement and thus the Carry (Borrow) flag is set.

SUI data (Subtract Immediate From Accumulator)

[A] [A] – data.

The 2nd byte of the instruction is data. It is subtracted from the content of the accumulator. The result is placed
in the accumulator. E.g. the instruction SUI 05H will subtract 05H from the content of the accumulator and
place the result in the accumulator. In the code form the above instruction is written as D6,05H.

Example: Assume the accumulator contains 40H. Subtract 37H from the accumulator.
Instruction: SUI 37H
Subtraend :37H = 0011 0111
2’s complement of 37 H = 1100 1001
+
(A) :40H = 0100 0000
1/0000 1001
Complement Carry: 0/0000 1001 = 09H
Flags: S = 0, Z = 0, AC = 0, P = 1, CY = 0.

SBI data (Subtract immediate data from accumulator with borrow)

[A] [A] – data – [CS]

The data and the carry status are subtracted from the content of the accumulator. The result is placed in the
accumulator.

Example: Assume the accumulator contains 37H and the borrow flag is set.
15
 Subtract 25H with borrow from the accumulator.
Instruction SBI 25H
(Data) : 25H
+ (Borrow) : 1H
Subtrahend : 26 H = 0010 0110
2’s complement (26H) = 1101 1010
(A) 37H = 0011 0111

1/0001 0001 = 11H

Complement carry: 0/0001 0001 = 11H
Flags: S = 0, Z = 0, AC = 1, P = 1, CY = 0.

SUB M (subtract memory from accumulator)

[A] [A] – [[H-L]]

The content of the memory location addressed by H-L pair is subtracted from the content of the accumulator.
The result is placed in the accumulator. The contents of the source are not altered. All flags are affected to
reflect the result of the subtraction.

SBB instruction

SBB stands for subtract with borrow. This instruction goes one step further than the SUB. It subtracts the
contents of a specified register and the CY flag from the accumulator contents. If

A = 1111 1111
E = 0000 0010
and CY = 1

the instruction SBB E starts by combining E and CY to get 0000 0011 and then subtracts this from the
accumulator as follows:

1111 1111
-0000 0011
1111 1100
The final contents are
CY = 0 and A = 1111 1100
INR r. (Increment register content)
[r] [r] + 1

The contents of the designated register are incremented by 1 and the results are stored in the same register.

INR M (Increment memory content)

[[H-L] [[H-L]] +1
the contents of the memory location addressed by the H-L pair is incremented by one.

INX rp (Increment Register Pair)

[rp] [rp] +1

The content of the register pair rp is incremented by one. The instruction views the contents of the two registers
as a 16-bit number.

16
 Example: Register pair HL contains 9FFFH. Specify the contents of the entire register if it is
incremented by 1.
Instruction: INX H
After adding 1 to the contents of the HL pair the answer is

H A0 00 L

DCR r (decrement register contents)

[r] [r] –1

The contents of the designated register is decremented by 1 and the results are stored in the same register.
Example: Decrement B, which is cleared, and specify its contents after the decrement.

Instruction: DCR B.
Before the instruction B = 00 H. Decrement Operation
(B) = 0000 0000
-01 = 0000 0001
Subtraction is performed in 2’s complement
(B) = 0000 0000
+
2’s complement of 1 = 1111 1111
(B) = 1111 1111
After the execution of the DCR instruction register B will contain FF H.

DCR M (Decrement Memory content)

[[H-L]] [[H-L]] –1

The content of the memory location addressed by H-L pair is decremented by 1.

Example:
Decrement the contents of memory location 2085, which presently holds A0 H. Assume the HL register
contains 2085H.

Instruction: DCR M Memory

Before instruction
H L 2084
20 85 2085 A0
2086

Figure p-07

After instruction Memory

H L
20 85 2084
2085 9FH
2086

Figure p-08
DCX rp (Decrement register pair)
[rp] [rp] –1
17
The content of the register pair rp is decremented by one. This instruction views the contents of the two
registers as a 16-bit number. The registers involved are;
B-C, D-E, H-L and SP.

Example:
Register pair DE contains 2000H. Specify the contents of the entire register if it is decremented by 1.

Instruction: DCX D After subtracting 1 from the DE register pair the answer is

D 1F FF E

DAA (Decimal adjust accumulator)

The instruction DAA is used in the program after ADD or ADC instruction. After the execution of ADD or
ADC instruction the result is in hexadecimal and it is placed in the accumulator. The DAA instruction operates
on this result and gives the final result in decimal system. It uses carry and auxiliary carry for decimal
adjustment. 6 is added to 4 LSBs of the content in the accumulator is their value lies in between A and F or the
AC flag is set to 1. Similarly, 6 is also to 4 MSBs of the content of the accumulator if their values lies in
between A and F or the CS flag is set to 1.When DAA is used data should be in decimal numbers.
The contents of the accumulator are changed from a binary value to two 4-bit binary coded decimal (BCD)
digits. This is the only instruction that uses the auxiliary flag (internally) to perform the binary to BCD
conversion, and the conversion procedure is as follows:
1. If the value of the low-order 4-bits (D3-D0) in the accumulator is greater than 9 or if AC flag is set, the
instruction adds 6 (06) to the low-order four bits.
2. If the value of the high-order 4-bits (D7-D4) in the accumulator is greater than 9 or if the carry flag set, the
instruction adds 6 (06) to the high-order four bits.
Add decimal 12BCD to the accumulator, which contains 39BCD.
(A) = 39BCD = 0011 1001
+ 12BCD = 0001 0010
51BCD 0100 1011
4 B
The binary sum is 4B H. The value of the low-order four bits is larger than 9. Add 06 to the low-order four bits.
4B = 0100 1011
+ 06 = 0000 0110
51 = 0101 0001
Example:
Add decimal 68BCD to the accumulator, which contains 85BCD.
(A) = 85BCD = 1000 0101
+ 68BCD = 0110 1000

153BCD = 1110 1101

The binary sum is EDH. The values of both, low-order and high-order, four bits are higher than 9. Add 6 to
both.
EDH = 1110 1101
+ 66 = 0110 0110

[1]53 = [1]0110 0011

CY CY

18
The accumulator contains 53 and the carry flag is set to indicate that the sum is larger than eight bits (153). The
program should keep track of the carry; otherwise it may be altered by the subsequent instructions.

LOGIC INSTRUCTIONS
The instructions of this group performs AND, OR, EXCLUSIVE OR operations; compare, rotate or take
complement of data in register or memory. These perform non-numeric data operations.

1. STC: Set Carry. The Carry flag is set to 1. No other flags are affected.

2. ANA Logical AND with Accumulator

The contents of the accumulator are logically ANDed with the contents of the operand (register or memory),
and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the
contents of HL registers. Flags S, Z, P are modified to reflect the result of the operation. CY is reset.
Eg.
ANA B, ANA C, ANA D, ANA E, ANA H, ANA L, ANA M and ANA A.

Question.
The contents of the accumulator and the register D are 54 H and 82 H respectively. Logically AND the contents
of register D with the contents of the accumulator. Show the flags and the contents of each register after
ANDing.

Instruction ANA D
54 H = 0 1 0 1 0 1 0 0
AND
82 H = 1 0 0 0 0 0 1 0
00000000
S = 0, Z =1, P= 1 CY = 0

3. ANI AND immediate with Accumulator

The contents of the accumulator are logically ANDed with the 8-bit data (operand) and the results are placed in
the accumulator. Flags S, Z, P are modified to reflect the results of the operation. CY is reset.

Example:
AND data byte 97 H with the contents of the accumulator, which contains A3 H.

Solution:
Instruction is ANI 97H
Logical AND
(A) : A3 H = 1010 0011
AND
(data) 97 H =1001 0111
1000 0001
S =1, Z = 0, P = 0, CY = 0.

4. XRA: Exclusive OR with Accumulator.

XRA Reg.
Mem.

19
The contents of the operand (register or memory) are Exclusive ORed with the contents of the accumulator, and
the results are placed in the accumulator. The contents of the operand are not altered. Flags Z, S, P are altered
to reflect the results of the operation. CY and AC are reset.

Example:
Assume the contents of the accumulator are 77H and of register D are 56 H. exclusive OR the contents with the
accumulator.

Instruction XRA D
[A]: 77 H = 0 1 1 1 0 1 1 1
EX-OR
[D]: 56 H = 0 1 0 1 0 1 1 0
00100001
Flags: S = 0, Z = 0, P = 1, CY= 0

4. XRI (Exclusive OR Immediate with Accumulator)

XRI 8-bit data
The 8-bit data (operand) is Exclusive ORed with the contents of the accumulator and the results are placed in
the accumulator. Flags Z, S, P are altered to reflect the results of the operation. CY and AC flags are reset.

Example:
Assume the contents of the accumulator are 8F H. Exclusive OR the contents of the accumulator with A2 H.

Solution:
Instruction XRI A2 H
(8F H) = 1 0 0 0 1 1 1 1
data (A2 H) =1 0 1 0 0 0 1 0
Exclusive OR: 0 0 1 0 1 1 0 1

Flags S = 0, Z = 0, P = 0, CY = 0. AC = 0

5. ORA logically OR with accumulator

The contents of the accumulator are logically ORed with the contents of the operand (register or memory), and
the results are placed in the accumulator. If the operand is a memory location, its address is specified by the
contents of H-L register pair. Flags Z, S, P are modified to reflect the results of the operation. CY and AC are
reset.

Example:
Assume the accumulator has data byte 03 H and register C holds byte 81 H. Combine the register C with the
accumulator bits.

Instruction: ORA C

03 H = 0 0 0 0 0 0 1 1
81 H = 1 0 0 0 0 0 0 1
10000011 S = 1, Z = 0, P = 0, CY = 0, AC = 0
The instruction is commonly used to:
 Reset the CY flag by ORing the contents of the accumulator with itself.
 Set the zero flag when 0 is loaded into the accumulator by ORing the contents of the accumulator with itself.
 Combine bits from different registers.
20
6. ORI; Logically OR Immediate

The contents of the accumulator are logically ORed with the 8-bit data in the operand and the results are placed
in the accumulator. Flags: S, Z, P are modified to reflect the results of the operation. CY and AC are reset.

7. CMP r compare with accumulator

The contents of the operand (register or memory) are compared with the contents of the accumulator. Both
contents are preserved and the comparison is shown by setting the flags as follows:

 If (A) < (Reg/Mem) ; Carry flag is set

 If (A) = (Reg/Mem) ; Zero flag is set
 If (A) > (Reg/Mem) ; Carry and zero flags are reset.

The comparison of two bytes is performed by subtracting the contents of the operand from the contents of the
accumulator; however, neither contents are modified. Flags S, P, AC are also modified in addition to Z and C
to reflect the results of the operation.

Example:
Register B contains data byte 62 H and the accumulator contains data byte 57 H. Compare the contents register
B with that of the accumulator.

Solution
Instruction: CMP B
(A) = 57 H = 0 1 0 1 0 1 1 1
(B) = 62 H = 0 1 1 0 0 0 1 0
- 1/1 1 1 1 0 1 0 1 S = 1, Z = 0, AC = 0, P = 0, CY = 1.
Results after executing the instruction
 No contents are changed.
 Carry flag is set because (A) < (B).
 S, Z, P, AC flags will also be modified as listed above.

RRC: Rotate Right With Carry

Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of D7 as well
as in the Carry flag.

Flag: CY is modified according to bit D0. S, Z, P, AC are not affected.

Question.
Rotate the contents of the accumulator right, assuming it contains A7 H and the carry flag is reset to 0.

Instruction RRC

The contents of bit D0 are placed in bit D7, and the carry flag is modified accordingly. However, the contents of
the Carry are not placed in bit D7, as in the instruction RAR.
RAL: Rotate Accumulator Left Through Carry.

Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7 is placed in the
least significant position D0.
Flag. CY is modified according to bit D7. S, Z, AC, P are not affected.
21
Example.
Rotate the contents of the accumulator through Carry, assuming the accumulator has A7 H and the Carry flag is
reset.
Instruction: RAL
This instruction effectively provides a 9-bit accumulator. The original contents of the accumulator can be
restored by using instruction RAR (Rotate Accumulator Right Through Carry). However; the contents will be
modified if the instruction RRC (Rotate Accumulator Right) is used to restore the contents.
RAR: Rotate Accumulator Right Through Carry
Each bit of the accumulator is rotated right by one position through the Carry flag. Bit D0 is placed in the most
significant position, D7.
Flags: CY is modified according to bit D0. S, Z, P, AC are not affected.
Example.
Rotate the contents of the accumulator assuming it contains A7 H and the carry flag is reset 0.

TRANSFER OF CONTROL
These are instructions that change program sequence. Instead of fetching the next instruction in usual way, the
computer may jump or branch to another part of the program.
JMP: Jump Unconditionally
The program sequence is transferred to the memory location specified by the 16-bit address. This is a 3-byte
instruction, the second byte specifies the low-order byte and the third byte specifies the high-order byte. This
instruction tells the computer to get the next instruction from the designated memory location. Every JMP
instruction includes an address that is loaded into the program counter. For instance,
JMP 3000 H
Tells the computer to get the next instruction from memory location 3000 H.

2000 H 2000 H

2005 H JMP 3000 H 2005 H JM 3000 H

2006 H 2006 H

• -
• -
• -
3000 H 3000 H

Figure p-09a Unconditional jump Figure p-09b Conditional jump.

Suppose JMP 3000 H is stored at 2005 H as shown in figure (a). At the end of the fetch cycle, the program
counter contains PC = 2006 H
During the execution cycle, the JMP 3000 H loads the program counter with the designated address:
PC = 3000 H
22
Example.
Write the instruction at location 2000 H to transfer the program sequence to memory location 2050 H.

Solution
Instruction is JMP 2050 H

Memory
address Code Mnemonics

2000 H C3 JMP 2050 H

2001 H 50
2002 H 20

The 16-bit address of the operand is entered in memory in reverse order, the low-order byte first followed by the
high-order byte.

JUMP CONDITIONALLY
Operand: 16-bit Address

OP Flag
Code Description Status
JC Jump on Carry CY = 1
JNC Jump on No Carry CY = 0
JP Jump on Positive S = 0
JM Jump on minus S = 1
JPE Jump on Parity Even P = 0
JPO Jump on Parity Odd P = 1
JZ Jump on Zero Z =1
JNZ Jump on No Zero Z =0

Table 01
Flags: No flags are affected.

JC addr
Means to jump to the specified address if the carry flag is set. In short, JC stands for jump if carry. Similarly,

JNC addr
Means to jump to the specified address if the carry flag is not set. That is, jump if no carry.
For example,
Label Instruction Comment
MVI A, FEH
REPEAT: ADI 01H
JNC REPEAT
MVI A, C4H
JC ESCAPE
.
.
ESCAPE MOV L, A
The MVI loads the accumulator with FEH. The ADI adds 1 to get FFH. Since no carry takes place, the JNC
takes the program back to the REPEAT point, where a second ADI is executed. This time the accumulator
overflows to get contents of 00H with a carry. Since the CY flag is set, the program falls through the JNC. The
23
accumulator is loaded with C4H. Then the JC produces a jump to the ESCAPE point, where the C4H is loaded
into the L register.

JPE and JPO

Besides the sign, zero, and carry flag, there is a parity flag designated P. During the execution of certain
instructions (like ADD, INR, etc.), the ALU result is checked for parity. If the result has an even number of 1s,
the parity flag is reset; if an odd number of 1s, the flag is set.

JPE addr
Produces a jump to the specified address when the parity flag is reset (even parity). On the other hand,

JPO addr
Results in a jump when the parity flag is set (odd parity). For instance, given these flags, S = 1 Z = 0 CY = 0
P = 1 The program would jump if it encountered; but it would fall through a JPO instruction.

Example:
Explain what the following program segment does.

Label Instruction Comment

MVI E, 00H ; Initialize counter
LOOP: INR E ; Increment counter
MOV A, E ; Load A with E
CPI FFH ; Compare to 255
JNC LOOP ; Go back if not 255

The E register is being used as a counter. It starts at 0. The first time the INR and MOV are executed, A = 01 H
After executing the CPI, the zero flag is 0 because 01H and FFH are unequal. The JNZ then forces the program
to return the LOOP point. The looping will continue until the INR and MOV have been executed 255 times to
get
A = FFH.
On this pass through the loop, the CPI sets the zero flag because the accumulator byte and the immediate byte
are equal. With the zero flag set for the first time, the program falls through the JNZ instruction. The computer
will loop 255 times before it falls through the JNZ.

NOTE
One use of this program segment is set to up a time delay. It is also used to insert additional
instruction inside the loop as follows:

Label Instruction Comment

MVI E, 00 H
LOOP: .
.
.
INR E
MOV A, E
CPI FFH
JNZ LOOP
The instructions at the beginning of the loop (symbolized by dots) will be executed 255 times. If you want to
change the number of passes through the loop, modify the CPI instruction as required.

24
PCHL: Load Program Counter With HL Contents.

The contents of the registers H and L are copied into the program counter. The contents of H are placed as a
high-order byte and of L as a low-order byte.

Flags: No flags are affected.

This instruction is equivalent to a 1-byte unconditional Jump instruction. A program sequence can be changed
to any location by simply loading the H and L registers with the appropriate address and by using this
instruction.

Restart Instructions
The 8085 has eight restart instructions as RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 and RST 7.
These instructions represent efficient ways to call frequently used Subroutines.

Opcode/ Binary Hex Code RST Effect Vector

Operand Address (H) Location
RST 0 11000111 C7 CALL 0 0 0 0H 0 0 0 0H
RST 1 11001111 CF CALL 0 0 0 8H 0 0 0 8H
RST 2 11010111 D7 CALL 0 0 1 0H 0 0 1 0H
RST 3 11011111 DF CALL 0 0 1 8H 0 0 1 8H
RST 4 11100111 E7 CALL 0 0 2 0H 0 0 2 0H
RST 5 11101111 EF CALL 0 0 2 8H 0 0 2 8H
RST 6 11110111 F7 CALL 0 0 3 0H 0 0 3 0H
RST 7 11111111 FF CALL 0 0 3 8H 0 0 3 8H

Table 02
The RST instructions are equivalent to 1-byte call instructions to one of the eight memory locations on page 0.
The instructions are generally used in conjunction with interrupts and inserted using external hardware.
However, these can be used as software instructions in a program to transfer program execution to one of the
eight locations.
Flags: No flags are affected.

What An RST Performs:

An RST has the same effect as the CALL. For example, execution of RST 0 will begin pushing the contents of
the program counter onto the stack. Then the program branches to address 0000H. The subroutine located
between 0000H and 0007H is carried out with the RET returning the processing to the main program.

25
 Figure p-10 Restarts are calls to vector locations

If an RST 1 is encountered, the contents of the program counter are again pushed onto the stack, the program
branches to 0008H and then returns to the main program.

Note
• A Restart instruction is a special kind of call because it branches to a predetermined address.
• Only 1-byte is required to code a restart instruction, unlike a standard call which uses 3-bytes.
• Each RST occupies a total of 8 bytes i.e. from 0000H to 0007H; there are 8 bytes. It is also true for 0008H
to 000AH, 0010H to 0017H etc.

Vectored Calls

The word vector implies direction. The RST instructions are like vectors because they point to specific locations
in memory. The starting address of each restart subroutine is called a vector location. RST 0 points to vector
location 0000H, RST 1 to vector location 0008H etc. Each vector location has only 8 bytes. Useful subroutines
require more than 8 bytes. Therefore, the vector locations are used for the starting address of longer subroutines.
The Intel 8085 has four additional interrupts and these interrupts generate RST instructions internally and thus
do not require any external hardware. These instructions and their Restart addresses are as follows:

Interrupts RST Address

TRAP 24 H
RST 5.5 2C H
RST 6.5 34 H
RST 7.5 3C H

Table 03

CALL: Unconditional Subroutine Call.

The program sequence is transferred to the address specified by the operand. Before the transfer, the address of
the next instruction to CALL (the contents of the program counter) is pushed on the stack.
Flags: No flags are affected.

Example

26
Write CALL instruction at memory location 2010 H to call a subroutine located at 2050 H. Explain the
sequence of events when the stack pointer is at 2099 H.

Memory
Address Hex Code Mnemonics

2010 H CD CALL 2050H

2011 H 50
2012 H 20

In the code, the low-order byte (50) is entered first then the high-order byte (20) is entered. However, in
mnemonics the address is shown in the proper sequence. If an assembler is used to obtain the codes, it will
automatically reverse the sequence of the mnemonics.

Execution of CALL.

The address in the program counter (2013 H) is placed on the stack as follows.
Stack pointer is decremented to 2098 H
MSB is stored
Stack pointer is again decremented SP 2099
LSB is stored
Call address (2050 H) is temporarily stored in internal registers
and placed on the bus for the fetch cycle.

The CALL instruction should be accompanied by one of the return (RET or conditional return) instructions in
the subroutine.
Conditional Call to Subroutine. Operand - 16-bit
Address
Op Code Description Flag Hex
status Code

CC Call on Carry CY = 1 DC 3 M If condition is not true

11 T
CNC Call with No Carry CY = 0 D4 5 M If condition is true.
17 T.
CP Call on positive S =0 F4 2 M If condition is not true.
9T
CM Call on minus S =1 FC 5 M If condition is true.
18 T.
CPE Call on Parity Even P =0 EC NB: If condition is not true it continues
the sequence, and thus requires fewer
CPO Call on Parity Odd P =1 E4 T-states.
CZ Call on Zero Z =1 CC If condition is true it calls the subroutine,
thus requires more T-states.
CNZ Call on No Zero Z =0 C4

Flags: No flags are affected.

RET: Return From Subroutine Unconditionally.

27
The program sequence is transferred from the subroutine to the calling program. The two bytes from the top of
the stack are copied into the program counter and the program execution begins at the new address. The
instruction is equivalent to POP Program Counter.

Flags: No flags are affected.

Assuming the stack pointer is pointing to location 2095H. Explain the effect of the RET instruction if the
contents of the stack locations are as follows:

2095 50
20
2096

Figure p-11

After instruction RET, the program execution is transferred to location 2050H and the stack pointer is shifted to
location 2097H. This instruction is used in conjunction with the CALL or conditional call instructions. The
main purpose of the stack is to save return addresses automatically when using CALLs. When a CALL addr is
executed, the contents of the program counter are pushed onto the stack. Then the starting address of the
subroutine is loaded into the program counter. In this way, the next instruction fetched is the first instruction of
the subroutine. On completion of the subroutine, a RET instruction pops the return address off the stack into the
program counter.

Address Instruction

2000H LXI SP, 2100H

2001H
2002H
2003H CALL 8050H
2004H
2005H
2006H MVI A, 0EH
. .
. .
20FFH HLT
. .
. .
8050H .
. .
. .
8059H RET
The instruction begins with, LXI and CALL instructions take 3 bytes each when assembled: 1 byte for the op
code and 2 bytes for the data. The is why the LXI instruction occupies 2000H to 2002H and the CALL occupies
2003H to 2005H.
The LXI loads the stack pointer with 2100H. During the execution of CALL 8050H, the address of the next
instruction is saved in the stack. This address (2006H) is pushed onto the stack in the usual way; the stack
pointer is decremented and the high byte 20H is stored; the stack pointer is decremented again, and the low byte
06H is stored. The program counter is then loaded with 8050H, the starting address of the subroutine.

28
When the subroutine is completed, the RET instruction takes the computer back to the main program as follows.
First, the low byte is popped from the stack into the lower half of the program counter; then the high byte is
popped from the stack into the upper half of the program counter.

SP
20FEH
06H 06H
20H
20H
2100H

Figure p-12a Figure p-12b

After the second increment, the stack pointer is back at 2100H,as shown in the figure. The stack operation is
automatic during CALL and RET instructions. All that is done is to initialize the setting of the stack pointer;
this is the purpose of the LXI SP, instruction. It sets the upper boundary of the stack. Then a CALL
automatically pushes the return address onto the stack, and a RET automatically pops this return address off the
stack.

Stack Instructions
A CALL instruction sends the program to a subroutine. Before the jump takes place, the program counter is
incremented and the address is saved at address reserved for the stack. These addresses are set aside for the
purpose of saving the return address. At the completion of a subroutine, the RET instruction loads the program
counter with the return address, which allows the computer to get back to the main program.
The stack is a portion of the memory set aside primarily for saving return addresses. The programmer decides
where to locate the stack and how large to make it. For example the figure a) below, shows a stack between
addresses 20E0H and 20FFH. This stack contains 32 memory locations for saving return addresses.
Programmers can locate the stack anywhere they want in memory, but once they have set up the stack, they no
longer use that portion of memory for program and data. Instead, the stack becomes a special space in memory,
used for storing the return addresses of subroutines calls.

20E0H

SP
Stack | 32 locations MSP
|
| 20FFH

a) b)
Figure p-13a Figure p-13b

Stack Pointer
The instructions that read and write into the stack are called stack instructions; these include PUSH, POP, and
CALL. Stack instructions use indirect addressing because a 16-bit register called the stack pointer (SP) holds
the address of the desired memory location. As shown in the figure b) above, the stack pointer is similar to the
29
HL pointer because the contents of the stack pointer indicate which memory location is to be accessed. For
instance, if SP = 20FFH
The stack pointer points to memory location M20FFH (see figure (c)). Depending on the stack instruction, a byte
is then read from, or written into, this memory location. Depending on the stack instruction, a byte is then read
from or written into this memory location.

To initialize the stack pointer, the immediate

load instruction
LXI SP, dble
20FFH For example, executing LXI SP, 20FFH
M20FFH
The stack pointer is loaded with 20FFH.

Figure p-14

PUSH instructions

The contents of the accumulator and the Flags register are known as the program status word (PSW). The
format for this word is PSW = AF
where A = contents of the accumulator
F = contents of the Flag register
The accumulator contents are the high byte while the flag register content are the low byte. When calling a
subroutine, the program status word is usually saved so that the main program can resume after the subroutine is
executed. The contents of the other register may have to be saved.
PUSH instructions enables data to be saved in the stack. The PUSH instructions are:

PUSH B
PUSH D
PUSH H
PUSH PSW
Where B stands for BC
D stands for DE
H stands for HL
PSW stands for program status word.
When a PUSH instruction is executed, the following things happen:
 The stack pointer is decremented to get a new value of SP-1.
 The high byte in the specified register pair is stored in MSP-1
 The stack pointer is decremented again to get to SP-2
 The low byte in the specified register pair is stored in the MSP-2

POP instructions
The POP instructions are Where B stands for BC
POP B D stands for DE
POP D H stands for HL
POP H PSW stands for program
POP PSW status word.
When a POP is executed, the following happens:
 The low byte is read from the memory location addressed by the stack pointer. This byte is
stored in the lower half of the specified register pair.
 The stack pointer is incremented.

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  The high byte is read and stored in the upper half of the specified register pair.
 The stack pointer is incremented.
Note
Each time a POP instruction is executed, 2 bytes come off the stack.
RETURN CONDITIONALLY
Op Flag Hex
Code Description Status Code M-Cycles/T-States
RC Return on Carry CY = 1 D8
RNC Return with No Carry CY = 0 D0
RP Return on positive S=0 F0
RM Return on minus S=1 F8 1/6 If condition is not true
RPE Return on Parity Even P = 1 E8
RPO Return on Parity Odd P = 0 E0 3/12 If condition is true.
RZ Return on Zero Z=1 C8
RNZ Return on No Zero Z = 0 C0
Note: If condition is not true, it continues the sequence and thus requires
fewer T-states. If condition is true, it returns to the calling
program and thus requires more T-states.

The RNZ will return only if the zero flag is reset, the RZ returns only when the zero flag is et, the RNC
returns only if the carry flag is reset, and so on.

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