VLSI Lecture series

a
Evolution of logic

nd
Fu
complexity in Integrated

g
in
Circuit for information

er
ne
technology services
gi
En
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines

a
❖ Evolution in logic complexity in Integrated circuits

nd
❖ Evolution of size in Integrated services

Fu
❖ Prominent Information Technology services

g
in
❖ Features of Integrated circuits

er
ne
gi
En
Evolution in logic complexity in IC’s
• Medium Scale Integration

a
• Introduced in 1967

nd
MSI • Logic Block per chip 20-200

Fu
• Large Scale Integration
• Introduced in 1972
LSI

g
• Logic Block per chip 200-2000

in
er
• Very Large Scale Integration
• Introduced in 1978

ne
VLSI • Logic Block per chip 2000-20000

• Ultra Large Scale Integration gi

En
• Introduced in 1989
ULSI • Logic Block per chip 20000 >>
 Evolution of size in Integrated services

a
nd
4.0 – 4.0
Minimum feature Size in (µm)

Fu
3.5 –

3.0 –

g
2.5 –

in
er
2.0 –

ne
1.5 –

1.0 –
gi
En
0.5 –
0.1
0.0 –
1975 1980 1985 1990 1995 2000
Year

Engineering Funda
Prominent Information Technology services

a
Video on Demand

nd
Fu
Speech Processing

g
in
Wireless/Cellular Data Communication

er
ne
Data Communication Multi-media Application
gi
En
Consumer Electronics Portable Computer

Main Frame Computer Personal Computer Computer Network

1975 1980 1985 1990 1995 2000
Year
Features of Integrated circuits

a
❖ Less area/volume

nd
❖ Less power consumption

Fu
❖ Less testing requirement at system level

g
in
❖ Higher reliability, mainly due to improved on chip interconnects

er
❖ Higher speed, mainly due to reduced interconnection length

ne
❖ Significant cost savings
gi
En
VLSI Lecture series

a
nd
Fu
VLSI design

g
in
Methodologies

er
ne
gi
En
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Design Time

a
nd
❖ Performance analysis versus design time

Fu
❖ Technology window

g
in
er
ne
gi
En
Design Time of IC
❖ Design Time of IC depends on following parameters

a
nd
❑ Design complexity

Fu
❑ Performance level
❑ Acceptable cost

g
in
er
ne
gi
En
Performance analysis versus design time
Full-custom Design

a
longer design time

nd
until “maturity”

Fu
Semi-custom Design
Circuit Performance

g
in
More Opportunities

er
Less Opportunities for performance
Shorter design for performance improvement

ne
time until improvement
“maturity”

gi
En

Design Time

Engineering Funda
Technology Window

a
nd
Fu
Circuit Performance

g
in
er
ne
gi
En
Design Production Design Production

Time
Technology Window 1 Technology Window 2
VLSI Lecture series

a
nd
Fu
Semi Custom and Full

g
in
Custom design

er
ne
gi
En
By Prof. Hitesh Dholakiya
Engineering Funda
Full Custom Design Semi Custom Design
1. Complete design, layout, geometry, orientation and 1. Some commonly used design, layout, geometry and
placement of transistor is done designer placement of transistor is interfaced with given demand.

a
nd
2. Entire design is made without use of any library. 2. Design is completed with the use of multiple library.

Fu
3. Development time for design before maturity is more. 3. Development time for design before maturity is less.

g
in
er
4. It has more opportunity for performance improvement 4. It has less opportunity for performance improvement

ne
gi
En
5. Less dependency on existing technology. 5. Complete dependency on existing technology.

6. High Cost 6. Low cost

Performance analysis versus design time
Full-custom Design

a
longer design time

nd
until “maturity”

Fu
Semi-custom Design
Circuit Performance

g
in
More Opportunities

er
Less Opportunities for performance
Shorter design for performance improvement

ne
time until improvement
“maturity”

gi
En

Design Time

Engineering Funda
VLSI Lecture series

a
nd
Fu
g
in
Semi Custom

er
ne
gi
En
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Semicustom design

a
nd
❖ Classification of Semicustom design

Fu
❖ Working of Different Semicustom design

g
in
er
ne
gi
En
Basics of Semicustom design
❖ This method is used to reduce time to market.

a
nd
❖ Here, we reduce cost of designing of product.

Fu
❖ Performance of semicustom design is lower then full custom design.

g
in
❖ Here, in semicustom design, we use readily available block, design,

er
library or modules.

ne
gi
En
Classification of Semicustom design
Semicustom Design

a
nd
Fu
g
in
Standard Cell Gate array Programmable devices

er
ne
gi
En
Standard Cell
❖ Here, we use standard cell library.

a
❖ A typical library may contain a few hundred cells including inverters,

nd
NAND Gates, NOR Gates, complex AOI/OAI Gates, D-Latches, FF and

Fu
Counters.
❖ In library, there are gates, with different driving capabilities, for example,

g
in
standard size, double size and quadruple size.

er
❖ We need to use size based on current driving capabilities and speed of

ne
device.

gi
❖ Designer sends the schematic to fabricator who prepares the mask if the
En
cells are from the library. Advantages
❖ Larger the library, the larger the cost. ❑ Flexible design
❖ Standard cell guarantees that it will work. ❑ Works with analog and digital function
❑ Sophisticated system can be built easily
Disdvantages
❑ Mask Cost
Gate Array
❖ A Gate array circuit is a prefabricated circuit with no particular

a
nd
function, in which transistors and other active devices are placed at

Fu
regular predefined positions.
❖ Only masks for metallization need to be created.

g
in
er
Advantages

ne
❑ Reduces the mask cost
❑ Less time to market

gi
Disadvantages
En
❑ Size is fixed
❑ Number of transistor are fixed
❑ Metal height is fix
❑ 2 metal layer are possible
❑ Low efficiency
❑ Suitable for low production volume
Programmable Logic Devices (PLD)
❖ There are variety of IC available in the market that could be

a
nd
programmed according to specification.

Fu
❖ Some architecture are listed here
❑ SPLD – Simple Programmable logical device

g
in
❑ CPLD – Complex programmable logical device

er
❑ FPGA – Field programmable Gate Array

ne
gi
En

Engineering Funda
VLSI Lecture series

a
nd
Fu
Hierarchy, Regularity,

g
in
er
Modularity & Locality
ne
gi
En
By Prof. Hitesh Dholakiya
Engineering Funda
Hierarchy
❖ It involves dividing complex design into various modules and

a
nd
submodules.

Fu
❖ This division is done until the complexity of submodules is at an

g
understandable level of details.

in
er
ne
gi
En
Regularity
❖ Here designer divides the hierarchy into sets of similar building

a
nd
blocks.

Fu
❖ Regularity is the design of array structures consisting of identical

g
cells.

in
er
❖ Regularity can be there at many levels,

ne
❑ At transistor level

gi
❑ At identical GATE level
En
❑ At micro block
❑ At macro block
Modularity
❖ Modularity means various functional blocks has well defined

a
nd
functions and interfaces, so that, they can be implemented and

Fu
tested separately.
❖ All the blocks can be combined easily at the end of the design

g
in
process to form large system.

er
ne
gi
En
Locality
❖ Locality ensures that the internals of modules are not visible to any

a
nd
exterior interface.

Fu
❖ This enables the outside world to treat each module as a block box

g
with well defined inputs and outputs.

in
er
ne
gi
En

Engineering Funda
VLSI Lecture series

a
nd
Fu
Package Technology

g
in
er
in IC
ne
gi
En
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Through hole Package

a
nd
❖ Surface Mount Package

Fu
❖ Contactless Package

g
in
er
ne
gi
En
Through Hole Package
❖ One or more leads go through holes of PCB and are soldered

a
nd
underneath.

Fu
❖ Packages are made from either plastic or ceramic.

g
❖ In though hole package, mainly there three categories

in
er
1. SIP (Single In line Package)

ne
2. DIP (Dual In line Package)

gi
3. PGA (Pin Grid Array) En
SIP (Single In line Package)
❖ IC package having single row of leads is SIP (Single In line Package)

a
nd
❖ It has less number of leads in single raw.

Fu
g
in
er
ne
gi
En
DIP (Dual In line Package)
❖ IC package having two rows of leads is DIP (Dual In line Package)

a
nd
❖ DIP’s are mostly used in educational institutes.

Fu
g
in
er
ne
gi
En
PGA (Package Grid Array)
❖ IC package having grid arrangement of leads, is PGA

a
nd
❖ They offers more number of leads (at max 400 pins).

Fu
❖ It is better than DIP’s in terms of thermal conductivity and power

g
dissipation characteristics.

in
er
ne
gi
En
Surface Mount Package
❖ Unlike through hole package, the leads of surface mount packages are

a
mounted directly on the surface of PCB.

nd
❖ They do not go through holes or fit into a socket.

Fu
❖ Normally, leads of Surface Mount Package is bent at an angle near foot to

g
in
aid soldering to the surface of PCB.

er
❖ BGA (Ball Grid Array)

ne
❑ It has metal balls

gi
❑ It does not have solderable leads,
En
❑ By little pressure we can fix it on PCB
❑ It has many terminals (56 to 1312)
❑ It can have packaging from multiple side (one to four sides)
Contactless Package
❖ It does not have physical contact with PCB.

a
nd
❖ It does not have any leads.

Fu
❖ It provides information wirelessly.

g
in
er
ne
gi
En

Engineering Funda
VLSI Lecture series

a
nd
Fu
g
VLSI Design Flow

in
er
ne
gi
En
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of VLSI Design flow

a
nd
❖ Flow Chart of VLSI Design flow

Fu
❖ Domains of VLSI Design flow

g
in
❖ Y chart of VLSI Design flow

er
ne
gi
En
Basics of VLSI Design Flow
❖ The design flow start with a given set of specification or

a
nd
requirements.

Fu
❖ So, system should get design with respect to given specifications.

g
❖ At the end, when the desired specifications are not met, the design

in
er
has to be modified and re-checked several times until it meets the

ne
required specifications.

gi
En
Flow Chart of VLSI Design Flow
Design Specification

a
HDL Coding

nd
Architecture design

Fu
g
Simulation

in
Gate level design

er
ne
Verification

gi
Circuit level design En
Meets
No
Yes

Fabrication
Domains of VLSI Design Flow
❖ The design description for a VLSI circuit may be described in forms of

a
nd
three domains:

Fu
1. Behavioral Domain
2. Structural Domain

g
in
3. Physical Domain

er
ne
gi
En
 Y Chart of VLSI Design
Structural Behavior
Domain Domain
System Algorithm

Register Finite State

a
Machine

nd
Logic Gate Module

Fu
Description
Boolean
Transistor

g
Equation

in
er
ne
Mask

gi
En
Cell placement
Modules
placement
Chip Floor plan

Physical Domain
Engineering Funda
 VLSI Lecture series

a
nd
Fu
Importance CAD tool

g
in
er
in VLSI design
ne
gi
En
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of CAD tool in VLSI design

a
nd
❖ IC design process

Fu
❖ IC fabrication process

g
in
❖ Important feature of CAD tools in VLSI design

er
ne
gi
En
Basics of CAD tools in VLSI design flow
❖ As per Moore’s Law, complexity of IC’s is increasing over the years.

a
nd
❖ Designing of VLSI circuit with millions of transistor in single IC is

Fu
beyond humans brain.

g
❖ To design VLSI circuit, Computer is required to check layout, circuit

in
er
performance, process etc.

ne
❖ Computer are used to aid in the design and optimization process.
gi
En
❖ VLSI designers are normally given a set of design rules based on
given technology.
IC design process and IC fabrication process
Pattern file

a
nd
Design Entry

Fu
Produce mask

g
in
Design Verification, For each layer wafer

er
DRC, Simulation etc. processing, deposit,

ne
expose, develop etch

gi
En etc.

Pattern Generator
Package

Test
Feature of VLSI CAD tools
❖VLSI CAD tools have following tools to meet design features:

a
nd
1. Physical design (Layout, editor, circuit schematics)

Fu
2. Physical verification (DRC (design Rule Check), circuit extractor, plot output,
visual checking)

g
in
3. Behavioral verification.

er
ne
gi
En

Engineering Funda
 VLSI Lecture series

a
nd
Fu
Comparison of FPGA

g
in
er
and CPLD
ne
gi
En
By Prof. Hitesh Dholakiya
Engineering Funda
 Comparison of FPGA and CPLD
Parameters FPGA CPLD

a
1. Full Form 1. Field Programable Gate Array 1. Complex Programable Logic Design

nd
2. Architecture 2. Based on “Look up table” 2. Based on “Logic Function”

Fu
3. Blocks in Architecture 3. Around 100000 3. Few blocks

g
in
4. Architecture tuning 4. Fine Grain Devices 4. Course Grain Devices

er
5. Architectural Memory 5. SRAM 5. EPROM

ne
6. Complexity 6. High 6. Less

gi
7. Cost 7. High
En 7. Less
8. Time to ON 8. It takes time to load program 8. Instant ON
9. Volatility of Program 9. Program lost once power is OFF 9. Program stays in CPLD
10. Power Consumption 10. Ideal Power Consumption 10. Weaker Power Consumption
11. Timing Analysis 11. Complex to determine 11. Easier to determine
En
gi
ne
er
in
g
Fu
nd
a
VLSI Lecture series

a
nd
Fu
g
On Chip Clock Generation

in
er
and Distribution
ne
gi
En
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Clock in Digital Integrated circuits

a
nd
❖ Pierce Crystal oscillator

Fu
❖ Generation of two non overlapping clocks

g
in
❖ Y chart of VLSI Design flow

er
ne
gi
En
Basics of Clock in Digital Integrated Circuits
❖ Clock signals are the heartbeats of digital systems. So, stability of

a
nd
clock signal is highly important.

Fu
❖ Ideally, clock signal should have minimum rise time & fall time, it

g
should have specified duty cycles and zero skew.

in
er
ne
gi
En
Rise Time Fall Time

Skew
Basics of Clock in Digital Integrated Circuits
❖ Practically, there is noticeable rise time and fall time, Duty cycles can

a
nd
also vary.

Fu
❖ In fact, as much as 10% of a machine cycle time us expanded to

g
allow realistic clock skews in large computer system.

in
er
❖ On chip generated clock can be process dependent and unstable.

ne
❖ As a result, usually separate clock chip which use crystal oscillators
gi
have been used for high performance VLSI chip.
En

Engineering Funda
Pierce Crystal Oscillator
❖ In this crystal, series resonant exists.

a
nd
❖ But internal series resonant

Fu
determines the oscillation frequency.

g
❖ External load at the terminals has

in
er
considerable effect on its frequency

ne
and frequency stability.

gi
En ❖ Higher the series resistance, lower
the resonant frequency.
 Generation of two non overlapping clock
❖ Product of two non overlapping clock is zero at all times.

a
nd
Fu
g
Ck

in
Ck-1

er
ne
gi
En Ck-2
VLSI Lecture series

a
nd
Comparison of FPGA,

Fu
CPLD, PLC,

g
in
er
Microprocessor,
ne
gi
En
Microcontroller & DSP
By Prof. Hitesh Dholakiya
 Parameters FPGA CPLD PLC MP MC DSP
Field Complex
Programmable Digital Signal
1. Full Form Programmable Programmable Microprocessor Microcontroller
Logic Control Processor
Gate Array Logic Device
CPU, IO port, Von Neumann Harvard
2. Architecture Look up table Logical Blocks CPU, IO Port
Memory Mostly architecture

a
nd
Consumer
Real Time In Industries, at Real Time
Course Tuning Computer Electronics like

Fu
3. Applications Applications high power & Applications
Applications Applications Camera,
(Fine Tuning) high Temp. Automobile
(Fine Tuning)

g
in
Fast for real Optimized for Fast for real
4. Response Slow Slow Slow
time speed only time

er
ne
Needs
5. Immunity with noise Very Good Moderate Highest Low Good
additional setup

gi
Not designed for
En Not designed Not designed
6. Task Single Task Single Task Multitasking
for Multitasking for Multitasking
Multitasking

Less Time (In Less Time (In Less Time (In Less Time (In
It takes time to It takes time to
7. Turn ON time terms of mili terms of Mili terms of Micro terms of Neno
get ON get ON
Sec) Sec) Sec) Sec)

8. Cost Expensive Cheap Expensive Expensive Cheap Expensive

VLSI Lecture series

a
nd
Fu
CMOS Fabrication

g
in
er
Process
ne
gi
En
By Prof. Hitesh Dholakiya
Engineering Funda
nMOS and pMOS structure on P Type Substrate

a
nd
Fu
g
in
er
ne
gi
En
Create n well or p well ❖ For nMOS and pMOS, special region must be created in which
region and channel semiconductor type is opposite to the substrate type, these region
stop region
are called wells or tubs.
❖ p well is created in n type substrate and n well is created in p type
Grow field oxide (Thick
substrate.
Oxide) and gate oxide
❖ nMOS transistor are created in p type substrate or p well and pMOS

a
(Thin Oxide)

nd
transistor are created in n type substrate or n well.

Fu
❖ That well should be of defined boundary to have fixed channel stop
Deposit and pattern

g
region.

in
polysilicon layer
❖ Thick Oxide is grown in active region of nMOS and pMOS.

er
ne
❖ The thin gate oxide is grown on the surface through thermal
Implant source, drain

gi
region and substrate oxidation.
En
contacts ❖ As per circuit make a pattern of polysilicon layer.
❖ After that create n+ and p+ regions for source, drain and substrate.
Create contact
windows, deposit and ❖ Final metallization for metal interconnects.
pattern metal layer
nMOS and pMOS on P Type Substrate

a
nd
Fu
g
in
er
ne
gi
En
 VLSI Lecture series

a
nd
Fu
Twin Tube Fabrication

g
in
er
Process
ne
gi
En
By Prof. Hitesh Dholakiya
Engineering Funda
 Basics of Twin tube fabrication process
❖ In our previous video, I have explained nMOS and pMOS structure on P Type Substrate.
❖ In that, there can be issues regarding, mutual coupling in between nMOS and pMOS.

a
❖ There can be major issues regarding, Latch up for CMOS fabrication.

nd
❖ To avoid those issues, we should fabrication nMOS and pMOS by twin tube fabrication

Fu
process.

g
in
er
ne
gi
En
 ❖ Let us use n Type substrate.
n – Type Substrate ❖ The resistivity of substrate should be higher.
❖ Higher the resistivity lesser the current
through substrate.

a
nd
❖ Then we should grow n+ layer epitaxially.

Fu
Epitaxial Layer ❖ That is having lesser resistance compared to

g
in
substrate.
n – Type Substrate

er
ne
gi
SiO2 Layer En
❖ After that, substrate is subjected to oxidation
and we grow SiO2 layer.
Epitaxial Layer

n – Type Substrate
 SiO2 Layer

❖ SiO2 layer is etched using masking.

Epitaxial Layer ❖ Two windows are formed, One for n-well and
another for p-well.
n – Type Substrate

a
nd
Fu
P+ diffusion

g
in
er
Photoresist mask

ne
gi
SiO2 Layer
En
P well ❖ 1st window is covered by photoresist mask.
❖ Then p type impurities diffused to form p
Epitaxial Layer well.

n – Type Substrate
N+ diffusion

Photoresist mask

SiO2 Layer
❖ 2nd window is covered by photoresist mask.

a
n well p well
❖ Then n type impurities diffused to form n

nd
well.

Fu
Epitaxial Layer

g
in
n – Type Substrate

er
ne
gi
SiO2 Layer
❖ Grow Thin SiO2 layer by thermal oxidation
En
n well p well for Gate terminal
❖ Grow Polysilicon layer for photolithography
Epitaxial Layer and pattern making.
n – Type Substrate
 SiO2 Layer
n well p well
❖ Each SiO2 and Polysilicon to implant Drain
and Source.
Epitaxial Layer

a
nd
n – Type Substrate

Fu
g
p+ diffusion

in
er
Photoresist mask

ne
gi
SiO2 Layer En ❖ p well covered with photoresist mask and p+
p+ p+
n well p well diffusion is done to form source and drain
region
Epitaxial Layer

n – Type Substrate
 n+ diffusion

Photoresist mask

SiO2 Layer ❖ n well covered with photoresist mask and n+

p+ p+ n+ n+
n well p well diffusion is done to form source and drain
region

a
nd
Epitaxial Layer

Fu
n – Type Substrate

g
in
er
S G D S G D

ne
gi
SiO2 Layer En ❖ Metal diffusion is done for contact
p+ p+ n+ n+
n well p well formation.
❖ Metal etching is done.
Epitaxial Layer ❖ Contact formations for source S, Drain D and
Gate G is done
n – Type Substrate
VLSI Lecture series

a
nd
Fu
g
in
Photolithography
er
ne
gi
En

By Prof. Hitesh Dholakiya

Engineering Funda
Photolithography
❖ It is a process to produce circuit/pattern on the Si Layer.

a
nd
❖ UV light exposure is used.

Fu
❖ Two important steps are there in photolithography

g
in
1. Photographic Masking : It contains information which we want to project on

er
Si wafer.

ne
2. Photographic Etching : It contains pattern information which we wants to

gi
remove from layer. En
❑ There are two types of photographic etching
➢ Wet Etching (By Chemical)
➢ Dry Etching (By UV light exposure)
VLSI Lecture series

a
Ion Implantation

nd
Fu
and it’s Advantage

g
in
er
ne
over Diffusion
En
gi
By Prof. Hitesh Dholakiya
Engineering Funda
Ion Implantation
❖ It is alternative to diffusion process in IC fabrication.

a
nd
❖ Diffusion Process is done at high temperature, but Ion implantation

Fu
is done at low temperature.

g
❖ In Ion Implantation, high energy dopant ions are accelerated, so that

in
er
ions can easily penetrate the Si wafer.

ne
❖ The depth of penetration can be increased by increasing accelerating
gi
voltage. En
VLSI Lecture series

a
Two Terminal MOS

nd
Fu
and it’s Energy band

g
in
er
ne
En
diagram
gi
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of MOS

a
nd
❖ Two terminal MOS structure

Fu
❖ MOS substrate basic properties

g
in
❖ Energy band diagram of p type substrate

er
❖ Energy band diagram of MOS structure

ne
gi
❖ Energy Band diagram of Combined MOS structure
En
Basics of MOS
❖ Full form of MOS is ‘Metal Oxide Semiconductor’.

a
nd
❖ Compared to BJT, it occupy less space. So it is more suitable for

Fu
integrated circuits.

g
❖ At gate terminal, if voltage is applied, it creates channel for

in
er
conduction in between DRAIN and SOURCE terminal.

ne
❖ Conduction is only depends on majority carrier only.
gi
En
Two Terminal MOS structure
Gate G Terminal

a
𝑽𝑮 Gate Voltage ❖By Adding impurities like BORON

nd
(Trivalent) in pure semiconductor,
Metal

Fu
we make P type material.
Oxide SiO2

g
❖ SiO2 layer is acting like a dielectric

in
er
layer. That forms capacitor in

ne
P Type Si Substrate between gate and substrate.

gi
En ❖ Thickness is there in order of 10nm
to 50nm.
❖External voltage is applied in
Substrate Terminal
between gate and substrate
𝑽𝑩 Substrate Voltage terminal, which will justify carrier
concentration for channel.
MOS substrate basic properties
❖ At equilibrium as per Mass Action Law

a
nd
𝒏𝒑 = 𝒏𝒊 𝟐

Fu
❖ Where, n & p are electrons & holes concentration, respectively.

g
in
❖ 𝑛𝑖 is intrinsic carrier concentration, its value at room temperature

er
300K is approximately 1.45 × 1010 1/𝑐𝑚−3 .

ne
❖ Here, we have substrate of acceptor concentration 𝑁𝐴 (in order of
gi
1015 to 1016 𝑐𝑚−3 ), so holes and electrons concentration is given by,
En
𝒑 = 𝑵𝑨
𝒏𝒊 𝟐
𝒏=
𝑵𝑨
Energy Band diagram of P Type substrate
❖ The bandgap in between conduction band and valance
band is 1.1eV.
Free Space ❖ Fermi potential 𝝓𝑭 , is based on intrinsic Fermi Level 𝑬𝒊

a
nd
and Fermi level 𝑬𝑭
𝑬𝑭 − 𝑬𝒊
𝒒𝝌 𝝓𝑭 =

Fu
𝒒
❖ For p type semiconductor, Fermi potential can be

g
𝑬𝒄 Conduction

in
approximated by
𝒌𝑻 𝒏𝒊
Band

er
𝝓𝑭𝒑 = 𝐥𝐧
Band gap 1.1eV 𝒒 𝑵𝑨

ne
❖ For n type semiconductor, Fermi potential can be

gi
𝑬𝒊 Intrinsic Fermi approximated by
𝒌𝑻 𝑵𝑫
En
𝒒𝝓𝑭 Level 𝝓𝑭𝒑 = 𝐥𝐧
𝒒 𝒏𝒊
𝑬𝑭 Fermi Level ❖ Electron affinity is 𝒒𝝌, which is energy gap in between
𝑬𝒗 valance Band conduction band and Free space.
❖ Energy required to move electron from fermi level to free
space is work function 𝒒𝝓𝑺 .
𝒒𝝓𝒔 = 𝒒𝝌 + (𝑬𝑪 − 𝑬𝑭 )
Energy band diagram of MOS structure
Metal Al Oxide Semiconductor Si

a
𝒒𝝌 = 𝟎. 𝟗𝟓𝐞𝐕

nd
𝑬𝒄 Conduction Band 𝒒𝝌 = 𝟒. 𝟏𝟓𝐞𝐕

Fu
𝒒𝝓𝑴 = 𝟒. 𝟏𝒆𝑽

g
in
𝑬𝑭 Fermi Level

er
ne
Band gap 8eV

gi
En

𝑬𝒗 valance Band
Energy band Diagram of combined MOS structure
❖ When we combined the three MOS material, fermi level must lined up in
single line and Free space must be continuous.
❖ Because of work function difference in between semiconductor and metal,

a
nd
there is voltage drop across MOS and banding of bands.

Fu
Metal Al Oxide Semiconductor Si

g
in
𝑬𝒄 Conduction Band

er
ne
gi
En 𝑬𝒊 Intrinsic Level
𝑬𝑭 Fermi Level

𝑬𝑽 Valance Band
VLSI Lecture series

a
Flat Band Voltage

nd
Fu
and Example on Flat

g
in
er
ne
Band Voltage
En
gi
By Prof. Hitesh Dholakiya
Engineering Funda
Basics of Flat Band Voltage
❖ Individually there is a different work function with Metal, SiO2 and

a
nd
Substrate.

Fu
❖ When we combine three layers, Because of work function difference

g
between metal and semiconductor, voltage drop occurs across the

in
MOS structure.

er
ne
❖ Part of this voltage appears across SiO2 layer and rest across the

gi
silicon surface. En
❖ This results into banding of energy bands.
❖ So, to get energy band without any banding, voltage required is
referred as flat band voltage
Consider the MOS structure that consists of a p type doped Si substrate, a SiO2 layer and a metal (Al)
gate. The equilibrium Fermi potential of the doped Si substrate is 𝒒𝝓𝑭𝒑 = 𝟎. 𝟐𝒆𝑽. Using electron
affinity for Si & work function for Al given in figure, Calculate the built in potential difference across
MOS system.

a
❖ Work Function for Si

nd
∴ 𝒒𝝓𝒔 = 𝒒𝝌 + (𝑬𝑪 − 𝑬𝑭 )

Fu
∴ 𝒒𝝓𝒔 = 𝟒. 𝟏𝟓 + (𝟎. 𝟓𝟓 + 𝟎. 𝟐)

g
∴ 𝒒𝝓𝒔 = 𝟒. 𝟗𝒆𝑽

in
❖ So work function difference

er
in between metal and

ne
substrate is given by

gi
En ∴ 𝒒𝝓𝒎 − 𝒒𝝓𝒔 = 𝟒. 𝟏 − 𝟒. 𝟗
∴ 𝒒𝝓𝒎 − 𝒒𝝓𝒔 = −𝟎. 𝟖𝒆𝑽

❖ So if voltage corresponding to this is applied externally between gate and substrate then the banding of energy bands
can be compensated and energy bands become flat. So flat band voltage is given by
∴ 𝑽𝑭𝑩 = 𝝓𝒎 − 𝝓𝒔
VLSI Lecture series

a
nd
MOS under External

Fu
g
in
Bias
er
ne
gi
En

By Prof. Hitesh Dholakiya

Engineering Funda
Basics of External biasing to MOS
❖ Here, we apply external bias to MOS by Gate voltage 𝑉𝐺 and

a
substrate voltage 𝑉𝐵 .

nd
Fu
❖ Here we keep, 𝑉𝐵 = 0 (constant) and 𝑉𝐺 as controlling voltage.

g
❖ Depending on the polarity and magnitude of 𝑉𝐺 , MOS functions in

in
er
three different regions.

ne
❑ Accumulation

gi
❑ Depletion En
❑ Inversion
Condition 1 : 𝑽𝑮 < 𝟎 and 𝑽𝑩 = 𝟎 Accumulation
Gate G Terminal Metal Al Oxide Semiconductor Si
𝑽𝑮 < 𝟎

a
𝑽𝑮 Gate Voltage

nd
Metal

Fu
𝑬𝒄 Conduction
Oxide SiO2 Band

g
𝑬𝒐𝒙 𝑬𝒐𝒙

in
er
ne
Holes accumulated on the surface 𝑬𝒊 Intrinsic Fermi
P Type Si Substrate 𝒒𝑽𝑮 Level

gi
En 𝑬𝑭 Fermi Level
𝑬𝒗 valance Band

𝑽𝑩 = 𝟎 ❖ Here carrier concentration becomes larger on surface, this is

Substrate Terminal
𝑽𝑩 Substrate Voltage called accumulation of carrier on the surface.
❖ Here, electron concentration goes deeper inside due to negative
potential
Condition 1 : 𝑽𝑮 > 𝟎 (small) and 𝑽𝑩 = 𝟎 Depletion
Gate G Terminal Metal Al Oxide Semiconductor Si
𝑽𝑮 > 𝟎

a
𝑽𝑮 Gate Voltage

nd
Metal 𝑬𝒄 Conduction

Fu
Band
Oxide SiO2

g
𝑬𝒐𝒙 𝑬𝒐𝒙

in
er
Depletion Region 𝑬𝒊 Intrinsic Fermi

ne
Level
P Type Si Substrate
gi
En 𝑬𝑭 Fermi Level
𝒒𝑽𝑮
𝑬𝒗 valance Band

𝑽𝑩 = 𝟎 ❖ Here carrier concentration (holes) will move deeply inside P type

Substrate Terminal
𝑽𝑩 Substrate Voltage material, and that forms depletion region near to surface of oxide layer.
Condition 1 : 𝑽𝑮 > 𝟎 (Large) and 𝑽𝑩 = 𝟎 Inversion
Gate G Terminal Metal Al Oxide Semiconductor Si
𝑽𝑮 > 𝟎

a
𝑽𝑮 Gate Voltage

nd
Metal 𝑬𝒄 Conduction

Fu
Band
Oxide SiO2

g
𝑬𝒐𝒙 𝑬𝒐𝒙

in
er
Electrons 𝑬𝒊 Intrinsic Fermi

ne
Depletion Region Level
P Type Si Substrate
gi
En 𝑬𝑭 Fermi Level
𝒒𝑽𝑮
𝑬𝒗 valance Band

❖ For Large gate voltage, electrons will make layer at surface of oxide, which is
𝑽𝑩 = 𝟎
Substrate Terminal opposite to p type substrate, that is called surface inversion.
𝑽𝑩 Substrate Voltage ❖ Below electrons, there will depletion layer.
❖ After some voltage, depletion layer will not increase and electrons will
increase.
 VLSI Lecture series

a
Thickness of depletion

nd
Fu
region, Depletion region

g
in
er
charge density and Surface
ne
gi
Inversion in MOS structure
En

By Prof. Hitesh Dholakiya

Engineering Funda
 𝑽𝑮 > 𝟎 (small) and 𝑽𝑩 = 𝟎 Depletion region
❖ Here we will calculate depletion 𝝓𝑺 𝒙𝒅
𝒒𝑵𝑨 𝒙𝒅𝒙
Gate G Terminal width 𝒙𝒅 as a function of surface ∴ න 𝒅𝝓 = න
𝑽𝑮 > 𝟎 𝝓𝑭 𝟎 𝜺𝑺𝒊
𝑽𝑮 Gate Voltage potential 𝝓𝑺 .
❖ Mobile hole charge in a thin 𝒒𝑵𝑨 𝒙𝒅 𝟐

a
∴ 𝝓𝑺 − 𝝓𝑭 =
Metal

nd
horizontal layer parallel to the 𝟐𝜺𝑺𝒊
surface is

Fu
❖ So depth of depletion region is
𝑬𝒐𝒙 Oxide SiO2 𝑬𝒐𝒙 𝒅𝑸 = −𝒒𝑵𝑨 𝒅𝒙
𝟐𝜺𝑺𝒊 (𝝓𝑺 − 𝝓𝑭 )

g
❖ The change in surface potential ∴ 𝒙𝒅 =

in
Depletion Region 𝒙𝒅 required to displace thin charge 𝒒𝑵𝑨

er
dQ by distance 𝒙𝒅 can be ❖ So depletion region charge density
P Type Si Substrate
X

ne
calculated by Poisson equation. is given by

gi
𝒅𝑸 ∴ 𝑸 = −𝒒𝑵𝑨 𝒙𝒅
𝒅𝝓 = −𝒙 .
En
𝜺𝑺𝒊
∴ 𝑸 = − 𝟐𝒒𝑵𝑨 𝜺𝑺𝒊 (𝝓𝑺 − 𝝓𝑭 )
𝒒𝑵𝑨 𝒙𝒅𝒙
𝑽𝑩 = 𝟎 𝒅𝝓 = ❖ Now if we further increase the
Substrate Terminal 𝜺𝑺𝒊 gate voltage then it will start to
𝑽𝑩 Substrate Voltage ❖ In integration, dx varies from 0 to create surface inversion by
𝒙𝒅 and potential varies from attracting electrons.
Fermi potential 𝝓𝑭 to surface
potential 𝝓𝑺 .
𝑽𝑮 > 𝟎 (Large) and 𝑽𝑩 = 𝟎 Inversion Region

Gate G Terminal ❖ When surface inversion takes place, the density of

𝑽𝑮 > 𝟎 mobile electrons on the surface equals to the density

a
𝑽𝑮 Gate Voltage
of holes in the p type.

nd
❖ Condition for that is given by (𝝓𝑺 = −𝝓𝑭 )
Metal

Fu
❖ Now if we further increase gate voltage 𝑽𝑮 then
width of depletion region will not increase but it
Oxide SiO2

g
𝑬𝒐𝒙 𝑬𝒐𝒙 increase the number of electrons.

in
❖ So maximum depletion region depth can be

er
Electrons
calculated by

ne
Depletion Region
P Type Si Substrate 𝟐𝜺𝑺𝒊 (𝟐𝝓𝑭 )

gi
∴ 𝒙𝒅𝒎 =
𝒒𝑵𝑨
En
❖ So this creation of inversion layer by externally
applied gate voltage is used for channel creation in
𝑽𝑩 = 𝟎 MOSFET, Which is used for current conduction in
Substrate Terminal
between drain and source.
𝑽𝑩 Substrate Voltage
VLSI Lecture series

a
nd
MOS Transistor

Fu
g
in
MOSFET
er
ne
gi
En

By Prof. Hitesh Dholakiya

Engineering Funda
Outlines
❖ Basics of MOS Transistor

a
nd
❖ Types of MOS Transistor

Fu
❖ Structure of n channel MOSFET

g
in
❖ Working of n channel MOSFET

er
ne
gi
En
Basics of MOS Transistor
❖ It is MOSFET (Metal Oxid Semiconductor Field Effect Transistor)

a
nd
❖ It has four terminals : Gate, Substrate, Drain and Source.

Fu
❖ This device is formed using MOS structure.

g
in
❖ Structure of MOS transistor is symmetrical to drain and source

er
terminal.

ne
gi
En
Types of MOS Transistor
❖ There are two types of MOS transistor based on channel.

a
nd
❑ Enhancement type MOS Transistor : It has no conducting channel

Fu
region at zero gate bias voltage.

g
❑ Depletion type MOS Transistor : It has conducting channel region

in
er
at zero gate bias voltage.

ne
gi
En
Structure of n Channel MOSFET
Gate G

a
nd
Source S Drain D
Metal

Fu
Oxide SiO2

g
in
Source n+ Channel Length L Drain n+

er
ne
P Type Si Substrate

gi
En

Substrate
Working of n Channel MOSFET in cut off region

a
nd
𝑽𝑮𝑺 < 𝑽𝑻𝟎

Fu
g
in
er
ne
gi
En
Depletion Region
Working of n Channel MOSFET cut off region

a
nd
𝑽𝑮𝑺 > 𝑽𝑻𝟎

Fu
g
in
er
Inversion Layer (Channel)

ne
gi
En
Depletion Region
Working of n Channel MOSFET in Linear region

a
nd
𝑽𝑮𝑺 > 𝑽𝑻𝟎

Fu
𝑽𝑫 small

g
in
er
Inversion Layer (Channel)

ne
gi
En
Depletion Region
Working of n Channel MOSFET threshold of
linear region

a
nd
𝑽𝑮𝑺 > 𝑽𝑻𝟎

Fu
𝑽𝑫 = 𝑽𝑫𝑺𝑨𝑻

g
in
er
Inversion Layer (Channel)

ne
gi
En
Pinch off Point
Depletion Region
Working of n Channel MOSFET in saturation
region

a
nd
𝑽𝑮𝑺 > 𝑽𝑻𝟎

Fu
𝑽𝑫 > 𝑽𝑫𝑺𝑨𝑻

g
in
er
Inversion Layer (Channel)

ne
gi
En
Pinch off Point
Depletion Region
VLSI Lecture series

a
nd
Threshold Voltage of

Fu
g
in
MOSFET
er
ne
gi
En

By Prof. Hitesh Dholakiya

Engineering Funda
Outlines
❖ Basics of Threshold Voltage of MOSFET

a
nd
❖ Parameters of Threshold Voltage of MOSFET

Fu
❖ Derivation of Threshold Voltage of MOSFET

g
in
er
ne
gi
En
Basics of Threshold Voltage of MOSFET
❖ It is a minimum voltage 𝑉𝐺𝑆 (Gate to Source) required to form

a
nd
inversion layer (channel) in between source and drain.

Fu
❖ Threshold voltage defines operation of MOSFET.

g
❖ If 𝑉𝐺𝑆 is less than threshold voltage then MOSFET will stay in cut off

in
er
region.

ne
gi
En
Parameters of Threshold Voltage in MOSFET
❖ There are four physical parameters which effects the

a
nd
threshold voltage of MOS structure:

Fu
❑ Work function difference between gate and the channel.

g
❑ The gate voltage component to change surface potential.

in
er
❑ The gate voltage component to offset the depletion region

ne
charge.

gi
❑ The voltage component to offset the fixed charges in the gate
En
oxide and in the silicon oxide interface.
 a
nd
Fu
Derivation of Threshold Voltage in MOSFET

g
in
er
ne
gi
En
❖ Work function difference 𝝓𝑮𝑪 in between the gate and ❖ There is also fixed positive charge density 𝑸𝑶𝑿 , it is due
the channel is given by to lattice imperfections at the interface.
𝝓𝑮𝑪 = 𝝓𝑭 𝑺𝒖𝒃𝒔𝒕𝒓𝒂𝒕𝒆 − 𝝓𝑴 (𝑴𝒆𝒕𝒂𝒍) ❖ So the forth component for threshold voltage will be
− 𝑸𝑶𝑿 /𝑪𝑶𝑿 .
𝝓𝑮𝑪 = 𝝓𝑭 𝑺𝒖𝒃𝒔𝒕𝒓𝒂𝒕𝒆 − 𝝓𝑭 (𝑮𝒂𝒕𝒆 𝒑𝒐𝒍𝒚𝒔𝒊𝒍𝒊𝒄𝒐𝒏)
❖ So, for zero substrate bias, threshold voltage is given by
❖ For surface inversion, surface potential should change 𝑸𝑩𝑶 𝑸𝑶𝑿
form 𝝓𝑭 to −𝝓𝑭 . So net change will be −𝝓𝑭 − 𝝓𝑭 = 𝑽𝑻𝑶 = 𝝓𝑮𝑪 − 𝟐𝝓𝑭 − −
𝑪𝑶𝑿 𝑪𝑶𝑿

a
− 𝟐𝝓𝑭 .

nd
❖ For non zero substrate bias, threshold voltage is given by
❖ When voltage is applied at gate, it repelled holes deeper
𝑸𝑩 𝑸𝑶𝑿

Fu
inside substrate, and it forms depletion region. This 𝑽𝑻 = 𝝓𝑮𝑪 − 𝟐𝝓𝑭 − −
region has ions which forms offset voltage due to charges 𝑪𝑶𝑿 𝑪𝑶𝑿

g
of ions near the surface. 𝑸𝑩𝑶 𝑸𝑶𝑿 𝑸𝑩 − 𝑸𝑩𝑶

in
𝑽𝑻 = 𝝓𝑮𝑪 − 𝟐𝝓𝑭 − − −
❖ So depletion region charge density at surface inversion 𝑪𝑶𝑿 𝑪𝑶𝑿 𝑪𝑶𝑿

er
(𝝓𝑺 = −𝝓𝑭 ) is given by 𝑸𝑩 − 𝑸𝑩𝑶

ne
𝑽𝑻 = 𝑽𝑻𝑶 −
𝑪𝑶𝑿
𝑸𝑩𝑶 = − 𝟐𝒒𝑵𝑨 𝜺𝑺𝒊 −𝟐𝝓𝑭

gi
En ❖ Here,
❖ If substrate bias is given with 𝑽𝑺𝑩 then depletion region
𝑸𝑩 − 𝑸𝑩𝑶 − 𝟐𝒒𝑵𝑨 𝜺𝑺𝒊
charge density is given by = ( −𝟐𝝓𝑭 + 𝑽𝑺𝑩 − −𝟐𝝓𝑭 )
𝑪𝑶𝑿 𝑪𝑶𝑿
𝑸𝑩 = − 𝟐𝒒𝑵𝑨 𝜺𝑺𝒊 −𝟐𝝓𝑭 + 𝑽𝑺𝑩 ❖ So Threshold voltage is given by
❖ So, the component of voltage which nullify the value will
be −𝑸𝑩 /𝑪𝑶𝑿, where 𝑪𝑶𝑿 is gate oxide capacitance per 𝑽𝑻 = 𝑽𝑻𝑶 + 𝜸( −𝟐𝝓𝑭 + 𝑽𝑺𝑩 − −𝟐𝝓𝑭 )
unit area. ❖ Where, ϒ is substrate bias or 𝟐𝒒𝑵𝑨 𝜺𝑺𝒊
𝜸=
body effect coefficient 𝑪𝑶𝑿
En
gi
nee
rin
g
Fu
nd
a
 VLSI Lecture series
Gradual Channel

a
nd
Fu
Approximation, Drain

g
in
Current Equation &
er
ne
gi
MOSFET Characteristics
En

By Prof. Hitesh Dholakiya

Gradual Channel Approximation in MOSFET

a
nd
𝑽𝑮𝑺 > 𝑽𝑻𝟎

Fu
𝑽𝑫𝑺 small

g
Y=0 Y=L

in
er
Inversion Layer (Channel)

ne
Y

gi
X
En
Depletion Region
 a
nd
❖ 𝑽𝑮𝑺 > 𝑽𝑻𝑶 and 𝑽𝑮𝑫 > 𝑽𝑻𝑶 , to form a channel.
𝒅𝒚

Fu
❖ Threshold voltage 𝑽𝑻𝑶 is assumed to be constant. 𝒅𝑹 = −
𝑾. 𝝁𝒏 . 𝑸𝑰 (𝒀)

g
❖ Channel Voltage 𝑽𝑪 (𝒚) will change with respect to Y. ❖ Channel current density is assumed to be constant, 𝑰𝑫

in
𝑽𝑪 𝒀 = 𝟎 = 𝑽𝑺 = 𝟎 current flows from source to drain. So as per Ohm’s law

er
𝑽𝑪 𝒀 = 𝑳 = 𝑽𝑫𝑺 𝑰𝑫

ne
𝒅𝑽𝑪 = 𝑰𝑫 . 𝒅𝑹 = − . 𝒅𝒚
𝑾. 𝝁𝒏 . 𝑸𝑰 𝒀
❖ Electric field component in Y direction is dominant

gi
compared to X direction, so current flow only confined in
En ❖ Here, y changes from 0 to L and 𝑽𝑪 changes from 0 to 𝑽𝑫𝑪
Y direction. 𝑳 𝑽𝑫𝑺
∴ න 𝑰𝑫 . 𝒅𝒚 = −𝑾. 𝝁𝒏 න 𝑸𝑰 𝒀 . 𝒅𝑽𝑪
❖ Let 𝑸𝑰 (𝒀) is the charge density in channel, 𝟎 𝟎
𝑽𝑫𝑺
𝑸𝑰 (𝒀) = −𝑪𝑶𝑿 𝑽𝑮𝑺 − 𝑽𝑪 𝒀 − 𝑽𝑻𝑶
∴ 𝑰𝑫 . 𝑳 = 𝑾. 𝝁𝒏 . 𝑪𝑶𝑿 න [𝑽𝑮𝑺 −𝑽𝑪 − 𝑽𝑻𝑶 ] . 𝒅𝑽𝑪
❖ Net voltage at source is (𝑽𝑮𝑺 − 𝑽𝑻𝑶 ) maximum and Net 𝟎
voltage at drain is (𝑽𝑮𝑺 − 𝑽𝑫𝑺 − 𝑽𝑻𝑶 ) minimum. So, for dy 𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫 = . 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
thickness, we will calculation incremental resistance dR. 𝟐 𝑳
❖ Here, if consider, 𝒌′ = 𝝁𝒏 . 𝑪𝑶𝑿 , then drain current will be ❖ So for saturation region drain current 𝑰𝑫 will be
𝒌′ 𝑾 𝒌
∴ 𝑰𝑫 = . 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐 ∴ 𝑰𝑫𝑺𝑨𝑻 = 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 (𝑽𝑮𝑺 − 𝑽𝑻𝑶 ) − (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝟐 𝑳 𝟐
𝑾
❖ Here, if consider, 𝐤 = 𝒌′ , then drain current will be 𝒌
𝑳 ∴ 𝑰𝑫𝑺𝑨𝑻 = . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝒌 𝟐
∴ 𝑰𝑫 = 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐 𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫𝑺𝑨𝑻 = . . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
❖ This equation of drain current 𝑰𝑫 is valid in linear region of 𝟐 𝑳

a
nd
MOSFET.

Fu
❖ In saturation region of MOSFET,
∴ 𝑽𝑫𝑺 ≥ 𝑽𝑫𝑺𝑨𝑻 = 𝑽𝑮𝑺 − 𝑽𝑻𝑶

g
in
er
ne
gi
En
VLSI Lecture series

a
nd
Examples on Drain

Fu
g
in
Current Calculation
er
ne
gi
En

By Prof. Hitesh Dholakiya

Engineering Funda
 a
nd
Drain current 𝑰𝑫 is given by

Fu
g
𝝁𝒏 . 𝑪𝑶𝑿 𝑾

in
∴ 𝑰𝑫 = . 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐

er
𝟐 𝑳

ne
𝟒𝟎𝟎 × 𝟏𝟎−𝟒 × 𝟖𝟎𝟎 × 𝟏𝟎−𝟔
× 𝟏. 𝟓 × 𝟐 𝟏. 𝟖 − 𝟏 𝟏 − 𝟏𝟐
gi
∴ 𝑰𝑫 =
𝟐 En
∴ 𝑰𝑫 = 𝟏𝟒. 𝟒 × 𝟏𝟎−𝟔 𝑨
∴ 𝑰𝑫 = 𝟏𝟒. 𝟒 𝝁𝑨
Example 2 : For an n channel MOS transistor with 𝝁𝒏 = 𝟔𝟎𝟎 𝒄𝒎𝟐 /𝑽𝑺𝒆𝒄, 𝑪𝑶𝑿 =
𝟕 × 𝟏𝟎−𝟖 𝑭/𝒄𝒎𝟐 , 𝑾 = 𝟐𝟎𝝁𝒎, 𝐋 = 𝟐𝝁𝒎 and 𝑽𝑻𝑶 = 𝟏𝑽.
Here biasing voltages for drain, Source and substrate are given by 3V, 0V and 0V,
respectively. For drain current to be 1mA, what should be gate bias voltage?
Drain current 𝑰𝑫 is given by

a
nd
𝝁𝒏 . 𝑪𝑶𝑿 𝑾 𝒌

Fu
∴ 𝑰𝑫 = . 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 = . 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐
𝟐 𝑳 𝟐

g
k is given by Drain current 𝑰𝑫 is given by

in
er
𝑾 𝒌

ne
∴ 𝒌 = 𝝁𝒏 . 𝑪𝑶𝑿 . ∴ 𝑰𝑫 = . 𝟐 𝑽𝑮 − 𝑽𝑻𝑶 𝑽𝑫 − 𝑽𝑫 𝟐
𝑳 𝟐
gi
−𝟖 −𝟔
𝟕 × 𝟏𝟎 En 𝟐𝟎 × 𝟏𝟎
∴ 𝒌 = 𝟔𝟎𝟎 × 𝟏𝟎−𝟒 × × 𝟎. 𝟒𝟐
𝟏𝟎 −𝟒 𝟐 × 𝟏𝟎−𝟔 ∴𝟏 = . 𝟐 𝑽𝑮 − 𝟏 𝟑 − 𝟑𝟐
𝟐
∴ 𝒌 = 𝟒. 𝟐 × 𝟏𝟎−𝟒 𝑨/𝑽𝟐
∴ 𝑽𝑮 = 𝟑. 𝟐𝟗 𝑽𝒐𝒍𝒕
∴ 𝒌 = 𝟎. 𝟒𝟐 𝒎𝑨/𝑽𝟐
 a
nd
Fu
For pMOSFET to be in Saturation region Part -1 for pMOSFET

g
∴ 𝑽𝑫𝑺 ≤ 𝑽𝑮𝑺 − 𝑽𝑻𝑶 ∴ (𝟑 − 𝟓) ↔ (𝟎 − 𝟓) − (−𝟏. 𝟓)

in
er
∴ −𝟐 ↔ −(𝟑. 𝟓)

ne
∴ −𝟐 > − 𝟑. 𝟓 (so Linear region)

gi
For nMOSFET to be in Saturation region Part -2 for nMOSFET
En
∴ 𝑽𝑫𝑺 ≥ 𝑽𝑮𝑺 − 𝑽𝑻𝑶 ∴ (𝟑 − 𝟎) ↔ (𝟓 − 𝟎) − (𝟏. 𝟓)
∴ 𝟑 ↔ (𝟑. 𝟓)
∴ 𝟑 < 𝟑. 𝟓 (so Linear region)
VLSI Youtube Playlist
 VLSI Lecture series

a
nd
Fu
Channel Length

g
in
Modulation of MOSFET
er
ne
gi
En

By Prof. Hitesh Dholakiya

Engineering Funda
Outlines
❖ Basics of Channel Length Modulation

a
nd
❖ Channel length Modulation in MOSFET

Fu
❖ Derivation of drain current for channel length modulation

g
in
❖ Characteristics of MOSFET with channel length modulation

er
ne
gi
En
Basics of Channel length Modulation
❖ In saturation region of working with MOSFET, there is channel length

a
nd
Modulation with MOSFET.

Fu
❖ In that channel length will change with respect to drain voltage of

g
MOSFET.

in
er
❖ Channel length will decrease with respect to increase in drain

ne
voltage in saturation region.

gi
En
Channel Length Modulation in MOSFET

a
nd
𝑽𝑮𝑺 > 𝑽𝑻𝟎

Fu
𝑽𝑫 >
= 𝑽𝑫𝑺𝑨𝑻
small

g
∆L

in
L’ L

er
Inversion Layer (Channel)

ne
gi
En Pinch Off Point Pinch Off Point
Depletion Region
 ❖ At pinch off point of channel, channel voltage will be 𝑽𝑫𝑺𝑨𝑻
❖ Gradual channel approximation is only valid in channel,
as per that drain current in deep saturation is given by
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫 (𝒔𝒂𝒕) = . . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝟐 𝑳′
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫 (𝒔𝒂𝒕) = . . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝟐 (𝑳 − ∆𝑳)

a
nd
𝟏 𝝁𝒏 . 𝑪𝑶𝑿 𝑾
❖ Total charge density in channel is given by ∴ 𝑰𝑫 (𝒔𝒂𝒕) = . . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐

Fu
∆𝑳 𝟐 𝑳
𝑸𝑰 (𝒀) = −𝑪𝑶𝑿 𝑽𝑮𝑺 − 𝑽𝑪 𝒀 − 𝑽𝑻𝑶 𝟏−
𝑳
❖ Here,

g
❖ Inversion layer charge at source (Y=0) end is given by

in
𝑸𝑰 (𝒀 = 𝟎) = −𝑪𝑶𝑿 𝑽𝑮𝑺 − 𝑽𝑻𝑶 ∆𝑳 ∝ 𝑽𝑫𝑺 − 𝑽𝑫𝑺𝑨𝑻

er
❖ Inversion layer charge at Drain end (Y=L) end is given by ❖ To simplify this drain current equation, we will take λ

ne
(Channel length modulation coefficient)
𝑸𝑰 (𝒀 = 𝑳) = −𝑪𝑶𝑿 𝑽𝑮𝑺 − 𝑽𝑫𝑺 − 𝑽𝑻𝑶

gi
En ∆𝑳 𝟏
❖ At the edge of saturation 𝑽𝑫𝑺 = 𝑽𝑫𝑺𝑨𝑻 ∴𝟏− = 𝟏 − 𝝀𝑽𝑫𝑺 ⇒ = 𝟏 + 𝝀𝑽𝑫𝑺
𝑳 ∆𝑳
𝑽𝑫𝑺 = 𝑽𝑫𝑺𝑨𝑻 = 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝟏−
𝑳
❖ Inversion layer charge at Drain end (Y=L) in saturation ❖ So drain current is given by
region is given by 𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫 𝒔𝒂𝒕 = . . 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝟐 . (𝟏 + 𝝀𝑽𝑫𝑺 )
𝑸𝑰 (𝒀 = 𝑳) ≈ 𝟎 𝟐 𝑳
❖ Effective channel length in saturation region will become
𝑳′ = 𝑳 − ∆𝑳
 ❖ Drain current is given by
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫 𝒔𝒂𝒕 = . . 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝟐 . (𝟏 + 𝝀𝑽𝑫𝑺 )
𝟐 𝑳

Drain Current

a
nd
Fu
with λ ≠ 0
𝑽𝑮𝑺𝟐 with λ=0

g
in
er
ne
with λ ≠ 0

gi
En 𝑽𝑮𝑺𝟏 with λ=0

Drain Voltage
 VLSI Lecture series

a
nd
Substrate Bias Effect

Fu
g
in
in MOSFET
er
ne
gi
En

By Prof. Hitesh Dholakiya

Engineering Funda
Outlines
❖ Basics of Substrate Bias Effect in MOSFET

a
nd
❖ Substrate Bias Effect with MOSFET characteristics

Fu
❖ Threshold voltage under substrate bias voltage

g
in
❖ Drain Current under substrate bias voltage

er
ne
gi
En
Basics of Substrate Bias Effect
❖ We have studied MOSFET characteristics with substrate bias

a
voltage 𝑽𝑺𝑩 = 𝟎.

nd
Fu
❖ For zero substrate bias voltage, threshold voltage is referred as
𝑽𝑻𝑶 .

g
in
❖ In many digital circuit applications, the source potential of nMOS

er
ne
transistor can be larger values, which results into 𝑽𝑺𝑩 > 𝟎.

gi
❖ In that cases, Threshold voltage will change with respect to 𝑽𝑺𝑩
En
and that leads to change in drain current, it means drain current is a
function of 𝑽𝑺𝑩 , 𝑽𝑮𝑺 and 𝑽𝑫𝑺 .
𝑰𝑫 = 𝒇(𝑽𝑮𝑺 , 𝑽𝑫𝑺 , 𝑽𝑺𝑩 )
Substrate Bias Effect

a
nd
Fu
g
in
er
ne
gi
En
Threshold Voltage under substrate bias voltage
❖ Threshold voltage under substrate bias voltage is given by

a
nd
Fu
𝑽𝑻 (𝑽𝑺𝑩 ) = 𝑽𝑻𝑶 + 𝜸( −𝟐𝝓𝑭 + 𝑽𝑺𝑩 − −𝟐𝝓𝑭 )

g
❖ Where, ϒ is substrate bias or body effect coefficient

in
er
ne
𝟐𝒒𝑵𝑨 𝜺𝑺𝒊
𝜸=

gi
𝑪𝑶𝑿 En
Drain Current under substrate bias voltage
❖ Drain current in linear and saturation region with substrate bias

a
voltage is given by

nd
Fu
𝝁𝒏 . 𝑪𝑶𝑿 𝑾
∴ 𝑰𝑫 (𝒍𝒊𝒏) = . 𝟐 𝑽𝑮𝑺 − 𝑽𝑻 (𝑽𝑺𝑩 ) 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐

g
𝟐 𝑳

in
er
𝝁𝒏 . 𝑪𝑶𝑿 𝑾

ne
∴ 𝑰𝑫 𝒔𝒂𝒕 = . . 𝑽𝑮𝑺 − 𝑽𝑻 (𝑽𝑺𝑩 ) 𝟐 . (𝟏 + 𝝀𝑽𝑫𝑺 )
𝟐 𝑳

gi
En
❖ Where, λ is Channel length Modulation coefficient
VLSI Lecture series

a
nd
MOSFET

Fu
g
in
Capacitances
er
ne
gi
En

By Prof. Hitesh Dholakiya

Engineering Funda
Outlines
❖ Basics of MOSFET Capacitances

a
nd
❖ Structural overview of MOSFET Capacitances

Fu
❖ MOSFET capacitance Model

g
in
❖ MOSFET Capacitances in different regions of MOSFET

er
ne
gi
En
Basics of MOSFET Capacitances
❖ Speed of integrated circuit is limited by Capacitances.

a
nd
❖ These capacitances are not lumped but distributed.

Fu
❖ It’s values can be calculated by three dimensional

g
in
overview of MOSFET.

er
❖ Here, we have already studied 𝑪𝑶𝑿 , which is gate oxide

ne
gi
capacitance, it’s unit is 𝑭ൗ𝑪𝒎𝟐 .
En
𝜺𝑶𝑿
𝑪𝑶𝑿 =
𝒕𝑶𝑿
Structural Overview of MOSFET Capacitances

a
nd
Fu
g
in
er
ne
gi
En
MOSFET Capacitances in different regions
Cut Off region
𝑪𝑮𝑩 = 𝑪𝑶𝑿 𝑾𝑳
𝑪𝑮𝑫 = 𝑪𝑶𝑿 𝑾𝑳𝑫

a
𝑪𝑮𝑺 = 𝑪𝑶𝑿 𝑾𝑳𝑫

nd
Fu
Linear region
𝑪𝑮𝑩 = 𝟎

g
in
𝟏
𝑪𝑮𝑫 = 𝑪𝑶𝑿 𝑾𝑳 + 𝑪𝑶𝑿 𝑾𝑳𝑫

er
𝟐

ne
𝟏
𝑪𝑮𝑺 = 𝑪𝑶𝑿 𝑾𝑳 + 𝑪𝑶𝑿 𝑾𝑳𝑫
𝟐

gi
En
Saturation region
𝑪𝑮𝑩 = 𝟎
𝑪𝑮𝑫 = 𝑪𝑶𝑿 𝑾𝑳𝑫
𝟐
𝑪𝑮𝑺 = 𝑪𝑶𝑿 𝑾𝑳 + 𝑪𝑶𝑿 𝑾𝑳𝑫
𝟑
En
gi
nee
rin
g
Fu
nd
a
En
gi
nee
rin
g
Fu
nd
a
En
gi
nee
rin
g
Fu
nd
a
En
gi
nee
rin
g
Fu
nd
a
En
gi
nee
rin
g
Fu
nd
a
En
gi
nee
rin
g
Fu
nd
a
En
gi
nee
rin
g
Fu
nd
a
En
gi
nee
rin
g
Fu
nd
a
VLSI Lecture series

a
nd
Fu
Resistive Load

g
in
er
Inverter
ne
gi
En

By Prof. Hitesh Dholakiya

Engineering Funda
Outlines
❖ Circuit of resistive load inverter

a
nd
❖ Working of resistive load inverter

Fu
❖ Voltage transfer characteristics of resistive load inverter

g
in
❖ Parameters of resistive load inverter

er
ne
gi
En
Circuit of Resistive load Inverter
𝑽𝑫𝑫

a
nd
R

Fu
g
𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑺

in
er
ne
gi
En
𝑽𝑰𝑵 = 𝑽𝑮𝑺
Working of Resistive load Inverter
❖ Due to capacitance of gate oxide layer, gate
current is zero.

a
nd
❖ So, 𝑰𝑹 = 𝑰𝑫

Fu
𝑰𝑹 ❖ So, Output voltage 𝑽𝑶𝑼𝑻 equation will be
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 − 𝑰𝑹 𝑹

g
in
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 − 𝑰𝑫 𝑹

er
𝑰𝑫

ne
❖ If input is lower voltage (logic 0), then

gi
En inversion layer will not get formed, So Drain
current will be zero
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 (logic 1)
❖ If input is higher voltage (Logic 1), then
inversion layer will get formed, So drain
current will increase, which will decrease
output to logic 0.
 Working of Resistive load Inverter
❖ So, drain current equation will be
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻

a
∴ 𝑰𝑫 =

nd
𝑹

Fu
❖ Here, If MOSFET is there in linear region then 𝑽𝒊𝒏 − 𝑽𝑻𝑶 > 𝑽𝑶𝑼𝑻

g
❖ Drain current 𝑰𝑫 in linear region will be

in
𝒌

er
∴ 𝑰𝑫 = 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝑶 𝑽𝑫𝑺 − 𝑽𝑫𝑺 𝟐
𝟐

ne
𝒌
= 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 𝑽𝑶𝑼𝑻 − 𝑽𝑶𝑼𝑻 𝟐

gi
∴ 𝑰𝑫
𝟐 En
❖ Here, If MOSFET is there in saturation region then 𝑽𝒊𝒏 − 𝑽𝑻𝑶 < 𝑽𝑶𝑼𝑻
𝒌
∴ 𝑰𝑫 = . (𝑽𝑮𝑺 − 𝑽𝑻𝑶 )𝟐
𝟐
𝒌
∴ 𝑰𝑫 = . (𝑽𝑰𝑵 − 𝑽𝑻𝑶 )𝟐
𝟐
Voltage Transfer Characteristics of Resistive load Inverter
𝑽𝑶𝑼𝑻

a
𝑽𝑶𝑯 𝒅𝑽𝑶𝑼𝑻

nd
= −𝟏
𝒅𝑽𝑰𝑵

Fu
g
in
er
ne
gi
En
𝒅𝑽𝑶𝑼𝑻
= −𝟏
𝒅𝑽𝑰𝑵
𝑽𝑶𝑳
𝑽𝑰𝑵
𝑽𝑰𝑳 𝑽𝑰𝑯 𝑽𝑶𝑯
Calculation of 𝑽𝑶𝑯
❖ Input voltage is less, so drain current is zero,
so per
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 − 𝑰𝑫 𝑹

a
∴ 𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫

nd
Fu
g
in
er
ne
gi
En
Calculation of 𝑽𝑶𝑳
❖ Here, 𝑽𝒊𝒏 − 𝑽𝑻𝑶 > 𝑽𝑶𝑼𝑻 , so MOSFET is there in
linear region, so drain current will be
𝒌
∴ 𝑰𝑫 = 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 𝑽𝑶𝑼𝑻 − 𝑽𝑶𝑼𝑻 𝟐

a
𝟐

nd
❖ Drain current is already derived

Fu
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻
∴ 𝑰𝑫 =
𝑹

g
in
❖ From above equation

er
𝑽𝑫𝑫 − 𝑽𝑶𝑳 𝒌

ne
∴ = 𝟐 𝑽𝑫𝑫 − 𝑽𝑻𝑶 𝑽𝑶𝑳 − 𝑽𝑶𝑳 𝟐
𝑹 𝟐

gi
𝟏 𝟐
En
∴ 𝑽𝑶𝑳 𝟐 − 𝟐 𝑽𝑫𝑫 − 𝑽𝑻𝑶 + 𝑽𝑶𝑳 + 𝑽 =𝟎
𝒌𝑹 𝒌𝑹 𝑫𝑫
❖ Solution of this equation is
𝟐
𝟏 𝟏 𝟐𝑽𝑫𝑫
∴ 𝑽𝑶𝑳 = 𝑽𝑫𝑫 − 𝑽𝑻𝑶 + − 𝑽𝑫𝑫 − 𝑽𝑻𝑶 + −
𝒌𝑹 𝒌𝑹 𝒌𝑹
Calculation of 𝑽𝑰𝑳
❖ Here, 𝑽𝒊𝒏 − 𝑽𝑻𝑶 < 𝑽𝑶𝑼𝑻 , so MOSFET is there in
saturation region, so drain current will be
𝒌
∴ 𝑰𝑫 = . (𝑽𝑰𝑵 − 𝑽𝑻𝑶 )𝟐

a
𝟐

nd
❖ Drain current is already derived

Fu
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻
∴ 𝑰𝑫 =
𝑹

g
in
❖ From above equation

er
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻 𝒌

ne
∴ = . (𝑽𝑰𝑵 − 𝑽𝑻𝑶 )𝟐
𝑹 𝟐

gi
❖ If differentiate given equation with respect to 𝑽𝒊𝒏
En
𝟏 𝒅𝑽𝑶𝑼𝑻
∴− . = 𝒌. 𝑽𝑰𝑵 − 𝑽𝑻𝑶
𝑹 𝒅𝑽𝑰𝑵
𝟏
∴ − . (−𝟏) = 𝒌. 𝑽𝑰𝑳 − 𝑽𝑻𝑶
𝑹
𝟏
∴ 𝑽𝑰𝑳 = 𝑽𝑻𝑶 +
𝒌𝑹
Calculation of 𝑽𝑰𝑯
❖ Here, 𝑽𝒊𝒏 − 𝑽𝑻𝑶 > 𝑽𝑶𝑼𝑻 , so MOSFET is there in
linear region, so drain current will be
𝒌
∴ 𝑰𝑫 = 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 𝑽𝑶𝑼𝑻 − 𝑽𝑶𝑼𝑻 𝟐

a
𝟐

nd
❖ Drain current is already derived

Fu
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻
∴ 𝑰𝑫 =
𝑹

g
in
❖ From above equation

er
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻 𝒌

ne
∴ = 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 𝑽𝑶𝑼𝑻 − 𝑽𝑶𝑼𝑻 𝟐
𝑹 𝟐

gi
❖ If differentiate given equation with respect to 𝑽𝒊𝒏
En
𝟏 𝒅𝑽𝑶𝑼𝑻 𝒌 𝒅𝑽𝑶𝑼𝑻 𝒅𝑽𝑶𝑼𝑻
∴− . = 𝟐 𝑽𝑰𝑵 − 𝑽𝑻𝑶 − 𝟐𝑽𝑶𝑼𝑻
𝑹 𝒅𝑽𝑰𝑵 𝟐 𝒅𝑽𝑰𝑵 𝒅𝑽𝑰𝑵
𝟏
∴ 𝑽𝑰𝑳 = 𝑽𝑻𝑶 + 𝟐𝑽𝑶𝑼𝑻 −
𝒌𝑹
𝟖 𝑽𝑫𝑫 𝟏
∴ 𝑽𝑰𝑳 = 𝑽𝑻𝑶 + −
𝟑 𝒌𝑹 𝒌𝑹
Average DC Power consumption
❖ Power consumption is voltage into current.

a
nd
❖ Here duty cycle is 50%, so voltage = 𝑉𝐷𝐷ൗ2

Fu
𝑉𝐷𝐷 −𝑉𝑂𝐿
❖ Here current =

g
𝑅

in
❖ So average DC power dissipation is given by

er
ne
𝑽𝑫𝑫 𝑽𝑫𝑫 − 𝑽𝑶𝑳
∴ 𝑷𝑫𝑪 (𝑨𝒗𝒆𝒓𝒂𝒈𝒆) = ×

gi
En 𝟐 𝑹
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VLSI Lecture series

FinFET Technology
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of FinFET
❖ Structure of FinFET
❖ Double Gate and Tri Gate FinFET
❖ SG FinFET and IG FinFET
❖ Top View of FinFET
❖ Fabrication Process of FinFET
❖ Characteristics of FinFET
❖ Advantages of FinFET
❖ Disadvantages of FinFET
❖ Applications of FinFET
Basics of FinFET
❖ It is Type of Multi Gate MOSFET.
❖ It is widely used over planar CMOS FET.
❖ Fin is channel in between source and drain.
❖ FinFET can have two or four or more Fin in same structure.
❖ It gives following advantages over FET
❑ Area of performance
❑ Lower Leakage power
❑ Low voltage operation
❑ Lower retention voltage for SRAM
❑ It has batter control over current
Structure of FinFET
Double Gate and Tri Gate FinFET
SG and IG FinFET

❖ SG (Short Gate) FinFET. ❖ IG (Insulated Gate) FinFET.

❖ It is 3T FinFET. ❖ It is 4T FinFET.
❖ Front and Back Gates are shorted. ❖ Front and Back Gates are isolated.
❖ Threshold Voltage can not be ❖ Threshold Voltage Vt can be
controlled externally. controlled externally.
❖ Less area occupied. ❖ More area occupied.
Top view of FinFET
Fabrication process of FinFET
❖ Substrate: In fabrication process, 1st lightly doped P
type substrate is fabricated and hard mask is
fabricated over the substrate.
❖ Fin Etch: Then by a highly an isotropic process fins
are formed.
❖ Oxide Deposition : Over Fins oxide layers are
formed to isolate the fins.
❖ Planarization: It is planarized by chemical
mechanical polishing process.
❖ Recess Etch : By this process excess oxide is etched.
❖ Gate Oxide : To isolate the channel from the gate by
thermal oxidation process gate oxide is deposited
over the fins.
❖ Deposition of the Gate : highly doped N+ poly
silicon gate layer is formed and deposited over fins.
 Characteristics of FinFET
Drain
Current Id
❖ Drain Current will increase with respect
to Vgs (Gate source voltage).
❖ Initially, Id will increase with increase in
Vgs = 1.0 Volt
Vds (Drain to source voltage), after that
FinFET enters into saturation region
where Id current will be constant.
Vgs = 0.8 Volt

Vgs = 0.2 Volt Drain Source

voltage Vds
Advantages of FinFET
❖ Lower Power consumption
❖ Operates at low voltage
❖ Operating Speed is higher
❖ Static leakage current is reduced up to 90%
❖ Compact
Disadvantages of FinFET
❖ Fabrication cost is higher then CMOS circuit.
❖ Controlling Fin Depth is difficult.
Applications of FinFET
❖ Used in Microprocessor
❖ Used in Microcontroller
❖ Used in Smart Phone
❖ Used in compact chip
 VLSI Lecture series
a
n d
F u
On Chip Clock i n g
Generation
e r
e
andinDistribution
n g
E By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Clock in Digital Integrated circuits
d a
❖ Primary Clock Generator
u n
❑ Pierce Crystal oscillator
g F
i n
❖ Generation of two non overlapping clocks
r
❖ Clock Distribution
e e
in
❑ H Tree clock distribution Network
g
E n
❑ Three Level Buffered clock distribution Network
❖ Important points of digital clock in VLSI
Basics of Clock in Digital Integrated Circuits
a
❖ Clock signals are the heartbeats of digital systems. So, stability of
d
clock signal is highly important.
u n
F
❖ Ideally, clock signal should have minimum rise time & fall time, it
g
i n
should have specified duty cycles and zero skew.
r
e e
g in
E n Rise Time Fall Time

Skew
Basics of Clock in Digital Integrated Circuits
a
❖ Practically, there is noticeable rise time and fall time, Duty cycles can
d
also vary.
u n
F
❖ In fact, as much as 10% of a machine cycle time us expanded to
g
i n
allow realistic clock skews in large computer system.
r
e
❖ On chip generated clock can be process dependent and unstable.
e
in
❖ As a result, usually separate clock chip which use crystal oscillators
g
n
have been used for high performance VLSI chip.
E
Primary Clock Generator
a
❖ There are many clock generator, primarily we use main three
d
techniques in IC’s.
u n
❑ Pierce clock generator
❑ Ring Oscillator g F
❑ LC Tank oscillator r i n
ee
g in
E n
Pierce Crystal Oscillator
a
❖ In this crystal, series resonant exists.
d
R bias ❖ But
u n
internal series resonant

g F
determines the oscillation frequency.
❖ External load at the terminals has
r i n considerable effect on its frequency
ee and frequency stability.

gin ❖ Higher the series resistance, lower

E n the resonant frequency.

❖ Inverter used to provide voltage
C1 C2
difference.
Ring Oscillator
a
❖ Ring oscillator is classified as :
d
u n
❑ CMOS inverter ring oscillator
❑ Fully differential ring oscillator

g F❑ Voltage controlled ring oscillator

r i n
❖ Here, in figure 3 inverter ring oscillator

ee is shown.

g in ❖ The number of inverter in ring oscillator

must be Odd.

E n ❖ Buffers are needed to drive the load.

❖ Clock frequency is process dependent
and unstable.
 Generation of two non overlapping clock
a
❖ Product of two non overlapping clock is zero at all times.
d
u n
g F
Clk

r i n
e e 𝜙2

g in
E n 𝜙1
Clock Distribution
❖ Clock distribution should be done with minimum skew.
d a
❖ Buffers amplify degraded clock.
u n
F
❖ In order to maintain high fan-out of circuit, buffers should be used in
g
between.
r i n
e e
❖ Uniform delay of clock in different blocks is also equally important.

g in
E n
 H tree clock distribution network
❖ It provides equal delay to all terminals.
d a
u n
g F
r i n
e e
g in
E n
 Three level buffered clock distribution network
❖ Buffers are used to amplify the clock.
d a
u n
g F
r i n
e e
g in
E n
Important points of digital clock in VLSI
❖ Ideally, duty cycle of clock should be 50%.
d a
should not be reduced excessively. u n
❖ To prevent reflection from the network, rise time and fall time of clock
F
❖ The load capacitance should be reduce as much as possible,
g
❑ by reducing fan-out
❑ by reducing interconnection lengthr i n
❑ by GATE capacitance
e e
of IC. g in
❖ Characteristics impedance of clock can be reduced by increasing w/h ratio

E n
❖ Inductive load can be used to cancel effect of parasitic capacitance.
❖ Separation should be maintained between high speed clock lines to avoid
cross talk.
VLSI Lecture series
a
n d
F u
in g
r
Ring eOscillator
e
g i n
E n
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Ring Oscillator
d a
❖ Circuit of Ring Oscillator
u n
❖ Working of Ring Oscillator
g F
r i n
❖ Operating frequency of Ring Oscillator
e e
g in
E n
Basics of Ring Oscillator
a
❖ In ring oscillator we connect NOT gates in ring.
d
u n
❖ Based on feedback signal, it generates clock signal.
F
❖ Number of NOT gates in ring should be ODD.
g
r i n
❖ Here, clock signal is process dependent so clock signal may get
unstable.
e e
in
❖ Buffers are required to drive the load.
g
E n
Ring Oscillator

d a
u n
g F
r i n
ee
g in
E n
VLSI Lecture series
a
n d
F u
in g
e r
ClockinDistribution
e
n g
E By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Clock in Distribution
d a
❖ Clock Distribution
u n
❑ H Tree clock distribution Network
g F
i n
❑ Three Level Buffered clock distribution Network
r
e e
❖ Important points of digital clock in VLSI

g i n
E n
Basics of Clock Distribution
a
❖ In Integrated circuit has many blocks, which should have clock signal
d
as input.
u n
F
❖ For many blocks to feed with clock, we need clock distribution
g
network.
r i n
e
❖ Clock distribution should be done with minimum skew.
e
in
❖ Buffers amplify degraded clock.
g
between. E n
❖ In order to maintain high fan-out of circuit, buffers should be used in

❖ Uniform delay of clock in different blocks is also equally important.

 H tree clock distribution network
❖ It provides equal delay to all terminals.
d a
u n
g F
r i n
e e
g in
E n
 Three level buffered clock distribution network
❖ Buffers are used to amplify the clock.
d a
u n
g F
r i n
e e
g in
E n
Important points of digital clock in VLSI
❖ Ideally, duty cycle of clock should be 50%.
d a
should not be reduced excessively. u n
❖ To prevent reflection from the network, rise time and fall time of clock
F
❖ The load capacitance should be reduce as much as possible,
g
❑ by reducing fan-out
❑ by reducing interconnection lengthr i n
❑ by GATE capacitance
e e
of IC. g in
❖ Characteristics impedance of clock can be reduced by increasing w/h ratio

E n
❖ Inductive load can be used to cancel effect of parasitic capacitance.
❖ Separation should be maintained between high speed clock lines to avoid
cross talk.
VLSI Lecture series
Faults in Integrated
Circuit
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of Faults
❖ Types of Faults
❑ Permanent fault
❑ Non Permanent fault
Basics of Faults in IC
❖ It leads to improper output of IC.
❖ It may give false output in IC or It may reduce speed of IC.
❖ There are basically two types of faults in IC
❑ Permanent Fault
❑ Non Permanent Fault
Permanent Fault
❖ It changes functional behavior permanently.
❖ Mostly it happens due to physical fault.
❖ Examples
❑ Incorrect IC Mask
❑ Wrong Connections in IC’s
❑ PCB heating
Non Permanent Fault
❖ It happens at random moments
❖ It effects system behavior for random time period
❖ It is comparatively difficult to detect.
❖ There are two types
❑ Transient Faults : It is caused by environmental conditions such as humidity,
Pressure, vibrations, α particles etc.
❑ Intermittent Faults : It is caused by non environmental conditions such as
loose connections, Ageing of components etc.
VLSI Lecture series
BIST
(Built In Self Test)
By Prof. Hitesh Dholakiya
Engineering Funda
Outlines
❖ Basics of BIST
❖ Types of BIST
❖ Architecture of BIST
❖ Working of BIST
❖ Issues of designing BIST
❖ Advantages of BIST
❖ Disadvantages of BIST
Basics of BIST
❖ It is technique of designing additional hardware and software into
integrated circuits to allow them to perform self testing.
❖ Aim of BIST technique is to avoid costly use of ATE (Automated Test
Equipment) testing.
❖ As IC’s are getting complex, many blocks are interfaced in IC with
analog and digital ports, in that ATE testing is difficult and costly
service.
❖ BIST is also useful to those blocks of IC which has no direct
connection with external pins.
❖ As IC’s are upgrading, in future conventional testers will no longer be
adequate for the latest and fastest chip.
Types of BIST
❖ Here, I will give basic explanation about two different BIST
1. Logic BIST (LBIST)
2. Memory BIST (MBIST)
Logic BIST (LBIST)
❖ It is designed for testing random logic.
❖ Here we use pseudo random pattern generator to generate random
input pattern.
❖ Multiple Input signature register (MISR) gives response of input
pattern and MISR output indicates defect in the device.
Memory BIST (MBIST)
❖ It is used for testing memories.
❖ It has a circuit that apply, read and compare test patterns.
❖ There are some industry standard for MBIST
❑ The March Algorithm
❑ The checkerboard Algorithm
❑ The varied pattern background Algorithm
 Basic Architecture of BIST
Test

Test Controller ROM

Reference
Normal Signature
Input
Output
MUX

CUT
Response Comparator
Hardware (Circuit Under Test) Signature
Compactor
Pattern
generator

Good/Faulty
Issues of BIST designing
❖ how many faults to be covered
❖ how much chip area occupied by BIST
❖ Test Time
❖ Flexibility by software and hardware
Advantages of BIST
❖ It lowers testing cost
❖ Testing is independent on future technology
❖ better fault coverage
❖ shorter test time
❖ Easier customer support
Disadvantages of BIST
❖ Additional circuit (Silicon area) for BIST testing in IC
❖ Additional Pin required for BIST testing in IC
❖ On chip testing may get failed then how to test it.
VLSI Lecture series

Stuck at Fault
By Prof. Hitesh Dholakiya
Engineering Funda
Stuck at fault
❖ Any terminal may stuck at logic ‘0’ or Logic ‘1’ is referred as stuck at
fault.
❖ At that terminal, it has no dependency on I/P and O/P.
❖ Examples A B Correct Y Actual Y

Stuck at ‘1’ 0 0 0 0
❑ Stuck at logic ‘1’
0 1 0 1
A 1 0 0 0
Y
B 1 1 1 1
A B Correct Y Actual Y
❑ Stuck at logic ‘0’ Stuck at ‘0’ 0 0 0 0
A 0 1 0 0
Y 1 0 0 0
B 1 1 1 0