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DSM Practical 2

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59 views14 pages

DSM Practical 2

Uploaded by

mohammed.ansari
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DSM-Practical-2

(Batch-A1)

Name Ansari Mohammed Shanouf Valijan


UID Number 2021300004
Class FY B.Tech Computer Engineering (Div-A)
Experiment Number 2

Aim:
To design and implement gate level multiplexers/demultiplexers and MSI
multiplexers/demultiplexers.

Equipments Required (if performed offline):


▪ 7404 quad 2 input IC (NOT gate)
▪ 7408 quad 2 input IC (AND gate)
▪ 7411 triple 3 input IC (3 input AND gate)
▪ 74LS21 dual 4 input IC (4 input AND gate)
▪ 7432 quad 2 input IC (OR gate)
▪ 4072 dual 4 input IC (4 input OR gate)
▪ 7400 quad 2 input IC (NAND gate)
▪ 74157 quadruple 1-of-2 data selector/multiplexer
▪ 74153 dual 1-of-4 data selector/multiplexer
▪ 74151 1-of-8 data selector/multiplexer
▪ 74150 16 line to 1 line data selector
▪ 74155 dual 2 line to 4 line decoder/demultiplexer
▪ 74LS138 3 line to 8 line decoder/demultiplexer
▪ 74154 4 line to 16 line decoder/demultiplexer

Software Used:
Proteus 8 by Labcenter Electronics.

Theory:
Multiplexers and demultiplexers are a part of combinational digital circuits. The
combinational digital circuits in general do not have any memory requirements
and feedback is absent in these kinds of circuits. In these circuits, the present
output solely depends on the present input.

Multiplexers: -

A multiplexer is a combinational circuit that consists of many inputs but only one
output. Following are the various names of a multiplexer:
• Many to one circuit
• Parallel to serial data convertor
• Universal circuit
• Data selector

A multiplexer consists of inputs, an output and one or more select lines which
help the circuit in selecting a particular input that will be passed to the output.

Figure-1: Symbol of a multiplexer


In the above figure, ‘a’ and ‘b’ are the inputs whereas ‘q’ is the output and ‘sel’
stands for select line.
If m is the total number of data-line inputs in a multiplexer and n is the number
of select lines, then, m ≤ 𝟐𝒏

Some examples of multiplexer circuits are given below-

2x1 MUX (2:1 MUX)-


This multiplexer consists of 2 inputs say 𝐼0 and 𝐼1 , and a select line say S
If Y is the output, then, Y=𝑆̅𝐼0 +𝑆𝐼1

4x1 MUX (4:1 MUX)-


This multiplexer consists of 4 inputs say 𝐼0 , 𝐼1 , 𝐼2 and 𝐼3 and 2 select lines say
𝑆1 and 𝑆0 where 𝑆0 is the Least significant bit and 𝑆1 is the most significant bit.
If Y is the output, then, Y=𝑆̅1 𝑆̅0 𝐼0 +𝑆̅1 𝑆0 𝐼1 +𝑆1 𝑆̅0 𝐼2 +𝑆1 𝑆0 𝐼3

8x1 MUX (8:1 MUX)-


This multiplexer consists of 8 inputs and 3 select lines. The expression for the
output obtained through this multiplexer can be written in SOP or POS form with
the help of its truth table and accordingly, it can be constructed.

In general, an Nx1 MUX (N:1) MUX will consist of N inputs and 1 output. The
number of select lines will depend on N.

Demultiplexers: -
A demultiplexer circuit consists of many outputs but only one input and one or
more select lines. Following are the various names of a demultiplexer:
• One to many circuit
• Data distributor circuit

The select lines in a demultiplexer circuit help in passing the input to only one of
the output channels available.

Figure-2: Symbol of a demultiplexer


In the above figure, a demultiplexer with 4 outputs and 2 select lines is shown. IN
the same way, a demultiplexer with N outputs can be constructed.

Some examples of demultiplexer circuits are given below-

1x2 DEMUX (1:2 DEMUX)-


This demultiplexer consists of 1 input say I, and 2 outputs say 𝑌0 and 𝑌1
It consists of a select line say S.
The expressions for the output will be as follows: 𝑌0 =𝑆̅𝐼 , 𝑌1 =𝑆𝐼

1x4 DEMUX (1:4 DEMUX)-


This demultiplexer consists of 1 input say I, and 4 outputs say 𝑌0 , 𝑌1 , 𝑌2 and 𝑌3
It also consists of two select lines say 𝑆0 and 𝑆1 .
Here 𝑆0 is the least significant bit while 𝑆1 is the most significant bit.
The expressions for the output will be as follows: 𝑌0 =𝑆̅1 𝑆̅0 𝐼, 𝑌1 =𝑆̅1 𝑆0 𝐼, 𝑌2 =𝑆1 𝑆̅0 𝐼,
𝑌3 =𝑆1 𝑆0 𝐼

1x8 DEMUX (1:8 DEMUX)-


This demultiplexer consists of 1 input and 8 outputs. It also consists of 3 select
lines. The expressions for the output can be written with the help of truth table.

In general, 1xM DEMUX (1:M DEMUX) would consist of M outputs and a single
input. The number of select lines will depend on the value of M.

Multiplexer and demultiplexer circuits can be used to make other combinational


Circuits like full adder, full subtractor, half adder, half subtractor, etc.
Also, higher multiplexer/demultiplexer circuits can be constructed with the help
of lower ones.
For example: A 32x1 MUX can be constructed using two 16x1 MUX
An 8x1 MUX can be constructed using seven 2x1 MUX
A 1x32 DEMUX can be constructed using two 1x16 DEMUX, etc.

Procedure:
I. Start by writing the truth table of the multiplexer/demultiplexer circuit that
is to be designed.
II. Write the expression(s) of the output and accordingly select all the required
equipments that will be needed for the implementation of the required
circuit.
III. Make all the connections will the help of the wire to get the required
expression(s).
IV. Connect logic toggle buttons which will act as data-line inputs as well as
select lines.
V. Connect logic probe to comprehend the output
VI. In cases of making a multiplexer, demultiplexer circuit will the help of ICs,
connect the E(Enable) to the ground in case where E is bubbled. If E is not
bubbled, connect it to a logic toggle button providing it an input of logic ‘1’
so that the circuit becomes functional.
VII. Verify the correctness of the designed circuit with the help of truth table.
Results/Observations:
Multiplexers: -

A] 2x1 MUX

Figure-3: A 2x1 MUX constructed using logic gates

Figure-4: A 2x1 MUX constructed using IC


Truth Table-
Select lines Output
S Y
0 𝐼0
1 𝐼1

B] 4x1 MUX

Figure-5: A 4x1 MUX constructed using logic gates

Figure-6: A 4x1 MUX constructed using IC


Truth Table-
Select lines Output
𝑆1 𝑆0 Y
0 0 𝐼0
0 1 𝐼1
1 0 𝐼2
1 1 𝐼3

C] 8x1 MUX

Figure-7: An 8x1 MUX constructed using logic gates

Figure-8: An 8x1 MUX constructed using IC


Truth Table-
Select lines Output
𝑆2 𝑆1 𝑆0 Y
0 0 0 𝐼0
0 0 1 𝐼1
0 1 0 𝐼2
0 1 1 𝐼3
1 0 0 𝐼4
1 0 1 𝐼5
1 1 0 𝐼6
1 1 1 𝐼7

D] 16x1 MUX

Figure-9: A 16x1 MUX constructed using IC


E] 32x1 MUX

Figure-10: A 32x1 MUX constructed using two 16x1 MUX

F] Full Adder Circuit with the help of two 8x1 MUX

Figure-11: A Full Adder circuit constructed by using two 8x1 MUX


Demultiplexers: -

A] 1x2 DEMUX

Figure-12: A 1x2 DEMUX constructed using logic gates

Truth Table-
Select line Outputs
S 𝑌1 𝑌0
0 0 I
1 I 0

B] 1x4 DEMUX (2x4 Decoder)

Figure-13: A 1x4 DEMUX constructed using logic gates


Figure-14: A 1x4 DEMUX constructed using IC

Truth Table-
Select lines Outputs
𝑆1 𝑆0 𝑌3 𝑌2 𝑌1 𝑌0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0

C] 1x8 DEMUX (3x8 Decoder)

Figure-15: A 1x8 DEMUX constructed using logic gates


Figure-16: A 1x8 DEMUX constructed using IC

Truth Table:
Select lines Outputs
𝑆2 𝑆1 𝑆0 𝑌7 𝑌6 𝑌5 𝑌4 𝑌3 𝑌2 𝑌1 𝑌0
0 0 0 0 0 0 0 0 0 0 I
0 0 1 0 0 0 0 0 0 I 0
0 1 0 0 0 0 0 0 I 0 0
0 1 1 0 0 0 0 I 0 0 0
1 0 0 0 0 0 I 0 0 0 0
1 0 1 0 0 I 0 0 0 0 0
1 1 0 0 I 0 0 0 0 0 0
1 1 1 I 0 0 0 0 0 0 0
D] 1x16 DEMUX (4x16 Decoder)

Figure-17: A 1x16 DEMUX constructed using IC

E] 1x32 DEMUX (5x32 Decoder)

Figure-18: A 1x32 DEMUX constructed using two 1x16 DEMUX


F] Half Adder Circuit with the help of one 1x4 DEMUX

Figure-19: A Half Adder circuit constructed with the help of 1x4 DEMUX

Conclusion:

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