ROHINI COLLEGE OF ENGINEERING AND TECHNOLOGY

ROHINI COLLEGE OF ENGINEERING AND TECHNOLOGY

Accredited by NAAC with A+ Grade
Paulkulam , Kanyakumari District – 629401.
Department of Computer Science and Engineering
CS3351-DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION

CS3351 – DIGITAL PRINCIPLES AND COMPUTER

ORGANIZATION LABORATORY
 ROHINI COLLEGE OF ENGINEERING AND TECHNOLOGY

COURSE OBJECTIVES:
➢ To analyze and design combinational circuits.
➢ To analyze and design sequential circuits
List of Experiments:

1. Verification of Boolean theorems using logic gates.

2. Design and implementation of combinational circuits using gates for arbitrary functions.
3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder circuits
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters
8. Implementation of a Universal Shift register.
9. Simulator based study of Computer Architecture
TOTAL : 30 PERIODS
COURSE OUTCOMES:
At the end of this course, the students will be able to:
➢ CO1 : Design various combinational digital circuits using logic gates
➢ CO2 : Design sequential circuits and analyze the design procedures
 ROHINI COLLEGE OF ENGINEERING AND TECHNOLOGY

INDEX
MARKS FACULTY
S.NO DATE EXPERIMENT NAMES PAGE NO
AWARDED SIGNATURE

10

11

12

13

14
 ROHINI COLLEGE OF ENGINEERING AND TECHNOLOGY

EXPT. NO.:1
DATE:
AIM:

To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each gate
has one or more input and only one output. OR, AND and NOT are basic gates. NAND and
NOR known as universal gates. Basic gates form these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function.
The output is high when both the inputs are high. The output is low level when any one of the
inputs is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output
is high when any one of the inputs is high. The output is low level when both the inputs are
low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The output
is low when the input is high.
NAND GATE:
 ROHINI COLLEGE OF ENGINEERING AND TECHNOLOGY
The NAND gate is a contraction of AND-NOT. The output is high when both inputs
are low and any one of the input is low .The output is low level when both inputs are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are
low. The output is low when one or both inputs are high.

X- OR GATE:
The output is high when any one of the inputs is high. The output is low when both
the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
 ROHINI COLLEGE OF ENGINEERING AND TECHNOLOGY
AND GATE

SYMBOL PIN DIAGRAM

OR GATE
 ROHINI COLLEGE OF ENGINEERING AND TECHNOLOGY

NOT GATE

SYMBOL PIN DIAGRAM

EX-OR GATE

SYMBOL PIN DIAGRAM

 ROHINI COLLEGE OF ENGINEERING AND TECHNOLOGY

2- INPUT NAND GATE

SYMBOL PIN DIAGRAM

3- INPUT NAND GATE

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NOR GATE

Viva Questions:

1. What are logic gates?

2. What is a logic circuit?
3. What is logic design?
4. What is a truth table?
5. What is a positive logic system?
6. What is a negative logic system?
7. What is the maximum number of outputs a logic gate can have?
8. What do you mean by level logic?
9. What is an AND gate?
10. Which gate is called an all or nothing gate? Why?
11. What is an OR-gate?
12. Which gate is called any or all gate? Why?
13. What is a NOT gate?
14. What is an inverter?
15. Which gates can be used as inverters in addition to the NOT gate?

RESULT:

The logic gates are studied and its truth tables are verified.
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EXPERIMENT:2
DESIGN AND IMPLEMENTATION OF CODE CONVERTERS
DATE:

AIM:
To design and verify the truth table of the following code converters
a. Binary to Gray converter & vice versa
b. BCD to Excess-3 & vice versa.

REQUIREMENTS:

S. No. Components / Equipments Specifications Quantity

1. Digital IC trainer --- 1

2. Ex-OR Gate IC7486 2

3. AND , OR and NOT IC7408, IC7432 and IC7404 1 each

THEORY:
Binary to GRAY Converter:
By representing the ten decimal digits with a four bit Gray code, we have another form of BCD
code. The Gray code however can be extended to any number of bits and conversion between binary
code and Gray code is sometimes useful. The following rules apply for conversion:
1. The MSB in the Gray code is the same as the corresponding bit in the binary number.
2. Going from left to right, add each adjacent pair of binary bits to get the next Gray code bit.
Disregard carries.
GRAY to Binary Converter:
To convert from Gray code to binary code, A similar method is used, at there are some differences.
The following rules apply:
1. The MSB in the binary code is the same as the corresponding digit in the Gray code
2. Add each binary digit generated to the gray digit in the next adjacent position Disregard carries.
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TRUTHTABLE FOR BINARY TO GRAY CODE CONVERTER:

Binary input Gray code output

B3 B2 B1 B0 G3 G2 G2 G0
0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0
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K-Map for G3: K-Map for G2:

G3 = B 3 G2=B3+B2

K-Map for G1: K-Map for G0:

G0=B1+B0

Binary to GRAY Logic Diagram :

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TRUTH TABLE FOR GRAY CODE TO BINARY CONVERTOR:

Gray code output Binary input

G3 G2 G2 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1
 lOMoARcPSD|284 453 49

K-Map for B3: K-Map for B2:

B3 = G3

K-Map for B1: K-Map for B0:

GRAY to Binary LOGIC DIAGRAM

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TRUTH TABLE FOR BCD TO EXCESS-3 CONVERTOR:

BCD input Excess – 3 output

B3 B2 B1 B0 G3 G2 G2 G0
0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x X x x

1 0 1 1 x X x x

1 1 0 0 x X x x

1 1 0 1 x X x x

1 1 1 0 x X x x

1 1 1 1 x X x x
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K-Map for E3: K-Map for E2:

E3 = B3 + B2 (B0 + B1)

K-Map for E1: K-Map for E0:

BCD TO EXCESS-3 Convertor Logic Diagram

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TRUTH TABLE FOR EXCESS-3

TO BCD CONVERTOR:

Excess – 3 Input BCD Output

B3 B2 B1 B0 G3 G2 G1 G0
0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1
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K-Map for A: K-Map for B:

A = X1 X2 + X3 X4 X1

K-Map for C: K-Map for D:

EXCESS-3 TO BCD convertor Logic diagram:

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PROCEDURE:

1. Connections are given as per the circuit diagram (Binary to GRAY).

2. Switch on the power supply.
3. Verify the truth table given for different inputs.
4. Repeat the above procedures for other converters.

Viva Questions :
1.What is the need of code converters?
2.What is Gray code?
3.What is the significance of Gray code?
4.What are applications of Gray code?
5.What are weighted codes and Non weighted codes?
6.What is Excess 3 code?
7.What is binary code?
8.Why binary is different from Gray code?
9.What is K Map?
10.What is don’t care condition?

Results:
Thus the truth tables for Binary to Gray, Gray to Binary and BCD to Excess3 converters were
verified.
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EXPERIMENT: DESIGN AND IMPLEMENTATION OF 4 BIT BINARY ADDER /

DATE: SUBTRACTOR USING IC 7483

AIM:
To study the 4 bit binary adder/subtractor using IC7483.

REQUIREMENTS:

S.No. Name of the apparatus Specifications Quantity

1 Digital Trainer kit - 1

2 OR gate IC 7432 1

3 AND gate IC 7408 1

4 Binary Adder / Subtractor IC 7483 2

5 Connecting wires - some

THEORY

The full adder/sub tractors are capable of adding/subtracting only two single digit binary
numbers along with a carry input. But in practice we need to add/subtract binary numbers, which are
much longer than just one bit. To add/subtract two n-bit binary numbers we need to use the n-bit parallel
subtractor/adder.
Binary adder: IC type 7483 is a 4-bit binary parallel adder/subtractor .The two 4-bit input binary
numbers are A1 through A4 and B1 through B4. The sum is obtained from S1 through S4. C0 is the
input carry and C4 the output carry. Test the 4-bit binary adder 7483 by connecting the power supply
and ground terminals. Then connect the four A inputs to a fixed binary numbers such as 1001 and the
B inputs and the input carry to five toggle switches. The five outputs are applied to indicator lamps.
Perform the addition of a few binary numbers and check that the output sum and output carry give the
proper values. Show that when the input carry is equal to 1, it adds 1 to the output sum.
Binary subtractor: The subtraction of two binary numbers can be done by taking the 2’s complement
of the subtrahend and adding it to the minuend. The 2’s complement can be obtained by taking the 1’s

complement and adding. To perform A-B, we complement the four bits of B, add them to the four bits
of A, and add 1 through the input carry. The four XOR gates complement the

bits of B when the mode select M=1(because x Θ 0 = x ) and leave the bits of B unchanged when
M=0(because x Θ 0 = x ) .Thus , when the mode select M is equal to 1, the input carry C0 is equal 1
and the sum output is A plus the 2’s complement of B. when M is equal to 0, the input carry is equal
to 0 and the sum generates A+B.
 lOMoARcPSD|284 453 49

Functional symbol for IC 7483:

Operand1 Operand2

B3 B2 B1 B0 A3 A2 A1 A0

Cout 4 bit IC 7483 Cin

Output

Pin Diagram of IC7483:

 lOMoARcPSD|284 453 49

Circuit Diagram for 4-bit Binary adder/subtractor:

4- BIT BINARY ADDER:

 lOMoARcPSD|284 453 49

4- BIT BINARY SUBTRACTOR

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Set mode M =0 such that the circuit will operate in addition mode.
3. Set the Value of inputs A as 1001 and B as 1001 note the sum and output carry.
4. Repeat the same step in step 3 by keeping M=1 such that circuit will operate in
subtraction mode.
 lOMoARcPSD|284 453 49

Viva Questions:

1. What are arithmetic circuits?

2. What is a half-adder?

3. What is a full-adder?

4. What is the disadvantage of realizing a full-adder using two half-adders?

5. What is a half-subtractor?

6. What is a full-subtractor?

7. Why are subtractor ICs not available?

8. What is a parallel adder?

9. What is the carry propagation delay of a full-adder?

10. What do you mean by cascading of parallel adders? Why is it required?

RESULT:
Thus the 4 bit Binary Adder / Subtractor using IC7483 is been implemented for both additionand subtraction
and the corresponding truth tables are verified.
 lOMoARcPSD|284 453 49

EXPERIMENT:
DESIGN AND IMPLEMENTATION OF BCD ADDER
DATE:

AIM:
To design and implement the BCD adder by using IC7483.

REQUIREMENTS:

S.No. Name of the apparatus Specifications Quantity

1 Digital Trainer kit - 1

2 OR gate IC 7432 1

3 AND gate IC 7408 1

4 Binary Adder / Subtractor IC 7483 2

5 Connecting wires - some

THEORY
The full adder/sub tractors are capable of adding/subtracting only two single digit binary
numbers along with a carry input. But in practice we need to add/subtract binary numbers, which are
much longer than just one bit. To add/subtract two n-bit binary numbers we need to use the n-bit parallel
subtractor/adder.
Binary adder: IC type 7483 is a 4-bit binary parallel adder/subtractor .The two 4-bit input binary
numbers are A1 through A4 and B1 through B4. The sum is obtained from S1 through S4. C0 is the
input carry and C4 the output carry. Test the 4-bit binary adder 7483 by connecting the power supply
and ground terminals. Then connect the four A inputs to a fixed binary numbers such as 1001 and the
B inputs and the input carry to five toggle switches. The five outputs are applied to indicator lamps.
Perform the addition of a few binary numbers and check that the output sum and output carry give the
proper values. Show that when the input carry is equal to 1, it adds 1 to the output sum.
Binary subtractor: The subtraction of two binary numbers can be done by taking the 2’s complement
of the subtrahend and adding it to the minuend. The 2’s complement can be obtained by taking the 1’s
complement and adding. To perform A-B, we complement the four bits of B, add them to the four bits
of A, and add 1 through the input carry. The four XOR gates complement the bits of B when the mode
select M=1(because x Θ 0 = x ) and leave the bits of B unchanged when M=0(because x Θ 0 = x )
.Thus , when the mode select M is equal to 1, the input carry C0 is equal 1 and the sum output is A

plus the 2’s complement of B. when M is equal to 0, the input carry is equal to 0 and the sum
generates A+B.
 lOMoARcPSD|284 453 49

Functional symbol for IC 7483:

Operand1 Operand2

B3 B2 B1 B0 A3 A2 A1 A0
Cout 4 bit IC 7483 Cin

Output

Pin Diagram of IC7483:

 lOMoARcPSD|284 453 49

TRUTH TABLE FOR BCD ADDER:

K MAP

Y = S4 (S3 + S2)
LOGIC DIAGRAM OF BCD ADDER

Downloaded by Devi visalakshi ([email protected])

 lOMoARcPSD|284 453 49

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Set mode CE =0 such that the circuit will operate in addition mode.
3. Set the Value of inputs A as 1001 and B as 1001 note the sum and output carry.

Viva Questions
1. What are arithmetic circuits?

2. What is a half-adder?

3. What is a full-adder?

4. What is the disadvantage of realizing a full-adder using two half-adders?

5. What is a half-subtractor?

6. What is a full-subtractor?

7. Why are subtractor ICs not available?

8. What is a parallel adder?

9. What is the carry propagation delay of a full-adder?

10. What do you mean by cascading of parallel adders? Why is it required?

RESULT:

Thus the BCD Adder using IC7483 is been implemented for and the corresponding truth
tables are verified.
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EXPERIMENT:
DESIGN AND IMPLEMENTATION OF ENCODER
DATE:

AIM:

To construct and verify the 8 X 3 Encoder using logic gates.

REQUIREMENTS:

S. No Components / Equipments Specification Quantity

1. Digital IC trainer kit - 1

2. OR Gate IC7432 3

3. Connecting Wires - Sufficient Numbers

THEORY:

Digital Computers, Microprocessors and other digital systems are binary operated whereas
our language of communication is in decimal numbers and alphabetical characters only. Therefore, the
need arises for interfacing between digital system and human operators. To accomplish this task,
Encoder is used

Logic Diagram:
 lOMoARcPSD|284 453 49

Truth Table:

INPUT OUTPUT

D0 D1 D2 D3 D4 D5 D6 D7 A B C

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

Outputs:
A = D4 + D5 + D6 + D7
B = D2 + D3 + D6 + D7
C = D1 + D3 + D5 + D7
 lOMoARcPSD|284 453 49

PROCEDURE:
1. Construct the circuit as per the diagram
2. Switch on the power supply.
3. Apply the necessary input and observe the outputs to verify the truth table.

Viva Questions

1.Define encoder.
2.What is decimal to BCD Encoder.
3.Draw the general structure of encoder.
4.Write the truth table for octal to binary encoder.
5.Draw the circuit for octal to binary encoder.
6. Write the truth table for 4 bit priority encoder.
7.List the encoder IC’s.
8. What is priority encoder?
9.Design 4 input priority encoder.

RESULTS:

Thus an 8 x 3 encoder is constructed and verified.

 lOMoARcPSD|284 453 49

EXPERIMENT:
DESIGN AND IMPLEMENTATION OF DECODER
DATE:

AIM:
To design, construct the decoder circuits and implement the function F (A,B,C) = ∑(1,2,4,7)
using the decoder ICs and also driver along with seven segment LED display unit and verify the
results.

REQUIREMENTS:

S. No. Components / Equipments Specification Quantity

1. Decoder IC 7447 1

2. Seven Segment Display Common Anode 1

3. Resistors 330Ω 7
4. IC Trainer Kit --- 1
5. Connecting Wires --- Required numbers

THEORY:
The process of taking some type of code and determining what it represents in terms of a
recognizable number or character is called decoding. A decoder is a combinational logic circuit that
performs the decoding function, and produce an output that indicates the (meaning) of the input
code. The decoder is an important part of the system which selects the cells to be read from and
write into. This particular circuit is called a decoder matrix, or simply a decoder, and has a
characteristic that for each of the possible 2n binary input number which can be taken by the n input
cells, the matrix will have a unique one of its 2n output lines selected.

n×2n
n Decoder 2n
Output
Input
 lOMoARcPSD|284 453 49

2 X 4 DECODER:
W0
2×4
X1 W1
Decoder
X2 W2

W3

TRUTH TABLE:

INPUTS OUTPUTS
X2 X1 W0 W1 W2 W3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

LOGIC CIRCUIT DIAGRAM:

1
7408 3 W0

2
1 2
X2 7404 4 7408 6
W1
5
3
7404 4 9
X1 7408 8
W2
10
12
7408 11
W3
13
 lOMoARcPSD|284 453 49

3 X 8 DECODER:

Implementation using decoder. F (A,B,C) = ∑(1,2,4,7)

Inputs Output
B C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
 lOMoARcPSD|284 453 49

Solution:

BCD Decoder
The BCD decoder converts each BCD code (8421) into one of ten possible decimal digit
indications. It is typically referred to as a 1 of 10 or 4 to 10 lines decoder, although other types of decoder
also fall into this category (such as an Execs – 3 decoder). A list of the ten BCD code words and their
corresponding decoding functions is shown in Table (2). Each of these decoding functions is
implemented with NAND gates to provide active LOW outputs, as shown in Fig. (2).

DECIMAL OUTPUTS LOGIC FUNCTION

DIGIT 0 1 2 3 4 5 6 7 8 9 (X)
0 0 1 1 1 1 1 1 1 1 1
D CBA
1 1 0 1 1 1 1 1 1 1 1
D CBA
2 1 1 0 1 1 1 1 1 1 1
DCBA
3 1 1 1 0 1 1 1 1 1 1 DCBA
4 1 1 1 1 0 1 1 1 1 1
DCBA
5 1 1 1 1 1 0 1 1 1 1 DCBA
6 1 1 1 1 1 1 0 1 1 1 DCBA
7 1 1 1 1 1 1 1 0 1 1 DCBA
8 1 1 1 1 1 1 1 1 0 1
 lOMoARcPSD|284 453 49

DCBA
9 1 1 1 1 1 1 1 1 1 0 DCBA
Truth Table of BDC to Decimal Decoder

A
B
740 0
C
0
D B
A
C
A 1
B
C
D

A 7404 D
A
B
C 3
Each

variable and D
A
B its B
complement C
BCD
are 4
INPUT
connected D
to A
appropriate B
C decode gate
C 5

input. D
A
B
C
6

D D
A
B
C 7

D
A
B
C
 lOMoARcPSD|284 453 49

D
A 9
B
C
Logic for BCD Decoder.
 lOMoARcPSD|284 453 49

BCD-to-Seven Segment decoder :

The 7-segment LED display is the most popular display device used in digital systems. To use this
device the data that is in the BCD form has to be changed suitably. For this purpose a BCD to 7-segment
decoder is required. The IC7447 is a BCD to 7-segment pattern converter. . The 7447 converts the four
input bits (BCD) to their corresponding 7-segment codes. The outputs of the 7447 are connected to the 7-
segment display.
A seven segment LED display contains 7 LEDs. Each LED is called a segment and they are
identified as (a, b, c, d, e, f, g) segments.

For example if decimal 9 is to be displayed a, b, c, d, f, g must be 0 and the others must be 1 (For

common anode type display units), if decimal 5 is to be displayed then a, f, g, c, d must be 0 and the others must
be 1.
 lOMoARcPSD|284 453 49

Connection Circuit Diagram:

PROCEDURE:
1. Connect the circuit as per circuit diagram.
2. Apply the inputs to the IC7447(A,B,C&D).
3. Observe the output and verify the result.
 lOMoARcPSD|284 453 49

Viva Questions

1.Define Decoder.
2.Define binary decoder.
3.Draw the general structure of decoder.
4.Write the truth table for 2 to 4 decoder.
5.Draw the circuit for 3 to 8 decoder.
6.What are the applications of decoders.
7.List the decoder IC’s.
8.Design 2x4 decoder using NAND gates.
9.What is the realization of Boolean function using decoder.

RESULT:
Thus the decoder, function implementation using decoder and driver unit along with 7
segment display unit is constructed and the results were verified.
 lOMoARcPSD|284 453 49

EXPERIMENT: DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND

DATE: DEMULTIPLEXER
AIM:
To design and implement multiplexer and demultiplexer using logic gates and implement the
Boolean function using multiplexer ICs.
Boolean function:

F(A,B,C,D) = Σ (0,1,3,4,8,9,15).
REQUIREMENTS :
S.No. Name of the apparatus Specification Quantity
1 Digital Trainer kit - 1

2 OR gate IC7432 1

3 AND gate IC7411 1

4 NOT gate IC7404 1

5 Multiplexer ICs 74150, 74151 / 74154 1

6 Connecting wires - -

THEORY:
Multiplexer:
It has a group of data inputs and a group of control inputs. The control inputs are used to select one of
the data inputs and connected to the output terminal. It selects one information out of many information
lines and directed to a single output line.
Demultiplexer:
Demultiplexers perform the opposite function of multiplexers. They transfer a small number of
information units (usually one unit) over a larger number of channels under the control of selection
signals. Fig shows a 1-line to 2-line Demultiplexer circuit. Construct this circuit; connect an LED to

each of the outputs D0 and D1. Set the select signal S to logic 1 or logic 0, and toggle the input I
between logic 1 and logic 0. Which output followed the input when S = 1 and S = 0.
 lOMoARcPSD|284 453 49

4:1 MULTIPLEXER:

BLOCK DIAGRAM

Circuit Diagram:

Truth Table:

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3
 lOMoARcPSD|284 453 49

1:4 DEMULTIPLEXER:
BLOCK DIAGRAM

Circuit Diagram:

Truth Table:

Selection Lines
OUTPUT V0
S1 S0

0 0 D0=Di

0 1 D1= Di

1 0 D2= Di

1 1 D3= Di
 lOMoARcPSD|284 453 49

PIN DIAGRAM FOR IC 74150:

PIN DIAGRAM FOR IC 74151:

 lOMoARcPSD|284 453 49

TRUTH TABLE:

LOGIC DIAGRAM:
 lOMoARcPSD|284 453 49

PIN DIAGRAM FOR IC 74154:

FUNCTION IMPLEMENTATION :
 lOMoARcPSD|284 453 49

Implement the following function: F(A,B,C,D) = Σ (0,1,3,4,8,9,15).

Design :
D0 D1 D2 D3 D4 D5 D6 D7
A’ 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15

1 1 0 A’ A’ 0 0 A
 lOMoARcPSD|284 453 49

Truth table of the function:

Table 3:

A B C D F(A,B,C,D)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

PROCEDURE:
1. Connections are given as per in the circuit diagram.
2. Inputs are given through the logic switches.
3. Outputs are noted and verified with truth table
Viva Questions
1. Define Multiplexer.
2.How many select lines are there for 12 : 1 MUX ?
3.How many input pins are there in a 2:1 MUX ?
4.How can we convert 4:1 Mux into 2:1 Mux ?
5.How many 2:1 MUX require to make 16:1 MUX ?
6.Define demultiplexer.
7.What are the types of demultiplexers?
8.What are the applications of multiplexer?
9.List out the multiplexer IC’s
10.Differentiate multiplexer and demultiplexer.

RESULT:
Thus the truth table of multiplexer and demultiplexer was studied and verified using logic
gates also the given Boolean function were implemented successfully.
 lOMoARcPSD|284 453 49

EXPERIMENT:
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTER
DATE:

AIM:
To construct and verify the synchronous up/down counters.

REQUIREMENTS:

S. No.Components / Equipments Specification Quantity

1. Digital IC trainer kit ---- 1

2. JK Flip-Flop, AND Gate IC 7473,7408 2,1

3. Connecting wires ---- Sufficient Nos

THEORY:
Synchronous Counter
Clock input is applied simultaneously to all flip-flops. The output of the first FLIP-FLOP is
connected to the input of second FLIP-FLOP and so on.

Design of synchronous counter

Step 1: Find the number of flip-flops required. For an n-bit counter, n- flip-flops is required.
Step 2: Write the count sequence in tabular form.
Step 3: Determine the flip-flop inputs, which must be present for the desired next State from the
present state using excitation table of flip-flops.
Step 4: Prepare K-map for each flip-flop input in terms of flip-flop output as input Variables. Simplify
the K-map and obtain the minimized expressions.
Step 5: Connect the circuit using the flip-flops.
 lOMoARcPSD|284 453 49

CIRCUIT DIAGRAM:
Design of 3-bit synchronous up:

Design of 3-bit synchronous down counter:

Pin Diagram
lOMoARcPSD|284 453 49
 lOMoARcPSD|284 453 49

3 Bit Synchronous UP 3 Bit Synchronous DOWN

Truth Table: Counter Counter

Clock Q2 Q1 Q0 Clock Q2 Q1 Q0

0 0 0 0 0 1 1 1

1 0 0 1 1 1 1 0

2 0 1 0 2 1 0 1

3 0 1 1 3 1 0 0

4 1 0 0 4 0 1 1

5 1 0 1 5 0 1 0

6 1 1 0 6 0 0 1

7 1 1 1 7 0 0 0

PROCEDURE:
1. The connections are made as per the circuit diagram.
2. Switch on the power supply.
3. The input is given at the appropriate terminal and corresponding output is observed and
truth table is verified.

Viva Questions

1.What is counter?
2.State types of counters.
3.What is MOD counter?
4.Define synchronous counter.
5.Define Asynchronous counter.
6.Name two sequential switching circuits.
7.What is meant by programmable counter?
8.List the applications of programmable counter.
9.Draw the state diagram of MOD 10 counter

RESULT:
Thus the counters were constructed and their truth tables verified.
 lOMoARcPSD|284 453 49

EXPERIMENT: IMPLEMENTATION OF SISO, SIPO, PISO AND PIPO SHIFT

DATE: REGISTERS
AIM:
To implement the 4 bit shift register using flip flops and to study the operations in the
following modes.
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in parallel out
(iv) Parallel in serial out
REQUIREMENTS:

S.No. Name of the apparatus Range Quantity

1 Digital Trainer kit 1
2 D Flip Flop IC 7474 2
3 Connecting wires some

THEORY:
SHIFT REGISTER:
A register is a device capable of storing a bit. The data can be serial or parallel. The register can convert
a data from serial to parallel and vice versa shifting then digits to left and right is theimportant
aspect for arithmetic operations,
A register capable of shifting its binary information either to the right or to the left is called a
shift register. An N bit shift register consists of N flip-flops and the gates that control the shift operation.
A shift register can be used in four different configurations depending upon the way in which the data
are entered into and taken out of it. These four configurations are:
a. Serial-input, Serial-output
. b. Parallel-input, Serial-output
c. Serial-input, parallel-output
d. Parallel-Input, parallel-output
The serial input is a single line going to the input of the leftmost flip-flop of the register. The serial
output is a single line from the output of the rightmost flip-flop of the register, so that the bits stored
in the register can come out through this line one at a time. The parallel output consists of N lines, one
for each of the flip-flops in the register, so the information stored in the register can be inspectedthrough
these lines all at once.
 lOMoARcPSD|284 453 49

PIN DIAGRAM:

Logic Diagram for Serial in Serial out:

 lOMoARcPSD|284 453 49

Logic Diagram for Serial in Parallel Out:

Logic Diagram for Parallel In Parallel Out

 lOMoARcPSD|284 453 49

Logic Diagram for Parallel in Serial out

TRUTH TABLE FOR PISO SHIFT REGISTER:

CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

PROCEDURE:
1. The flip-flop is connected using connecting wires as shown in the circuit.
2.The flip flop are then reset to zero internally with the help of reset to set inputs.
3.The bits are shifted in by giving suitable clock input.
4.Thus the truth table is then verified.
Viva questions:
1.Define registers.
2.Define shift registers.
3.What are the types of shift registers?
4.What are the applications of shift registers?
5.What is bidirectional shift registers?
6.What is buffer register?
7.What do you meant by controlled buffer register?
8.What is universal shift register?
9.Draw the circuit for 4 bit universal shift register.

RESULT:
Thus the operation of 4 bit shift register for SISO, SIPO, and PIPO was studied and verified.
 lOMoARcPSD|284 453 49

EXPERIMENT:
IMPLEMENTATION OF MOD-10 RIPPLE COUNTER
DATE:

AIM:
To construct and verify Mod-10 Ripple Counters.
APPARATUS REQUIRED:
S.No. Name of the apparatus SPECIFICATION Quantity

1 Digital Trainer kit 1

2 JK Flip Flop IC 7473 2

3 NAND Gate IC7400 1

4 Connecting wires some

THEORY:
Counters are a group of flip flops connected together to perform counting operation. According
to the way the flip flops are clocked, there are two types of flip flops,
a. Asynchronous Counter
b. Synchronous Counter
In asynchronous counter, the flip flop is clocked by the external clock pulse. Then each
successive flip flop are clock by Q or Q’ output of the previous flip flop. In 4 bit ripple counter, the total
number of states is 16 (24) and this varies from 00002 to 11112 . If the counters are designed with number
of sequence which is less than 2, then those counters are said to be Mod-N counters where N denotes
number of sequence. Thus in Mod-10 counter, total number of states is 10 and number of flip flops are
4. Similarly in Mod-12 counter, total number of states is 12 and number of flip flops are 4.
 lOMoARcPSD|284 453 49

CIRCUIT DIAGRAM OF MOD-10 RIPPLE COUNTERS

PROCEDURE:

1. Verify the flip flop.

2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. By applying the clock pulse, all the input combinations are given and the outputs are
verified with the truth table.

Viva Questions
1. How many natural states will there be in a 4-bit ripple counter?
2. What happens to the parallel output word in an asynchronous binary down counter
whenever a clock pulse occurs?
3. How many flip-flops are required to construct a decade counter?
4. How many different states does a 3-bit asynchronous counter have?
5. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How
many transitional states are required?
6. Define flipflop
7. Define ripple counter.
8. Differentiate asynchronous and synchronous counter

RESULT:
Thus the Mod 10 ripple counter was designed and constructed successfully.
 lOMoARcPSD|284 453 49

EXPERIMENT:
STUDY OF UNIVERSAL SHIFT REGISTER
DATE:
AIM:

To study and verify the load, shift and rotate operation of a 4-bit shift register.
EQUIPMENT/APPARATUS USED:
S. No. Name of the equipment Range/Rating Quantity
1. Digital IC Trainer .... 1
2. IC 74195 ... 1
3. Connecting Wires ...
THEORY:

A register is a group of binary storage cells capable of holding binary information. A group of flip
flops constitutes a register, since each flip-flop can work as a binary cell. An n-bit register, has n flip-flops
and is capable of holding n-bits of information. In addition to flip-flops a register can have a combinational
part that performs data-processing tasks.

Shift Register: A register capable of shifting its binary contents either to the left or to the right is called a
shift register. The shift register permits the stored data to move from a particular location to some other
location within the register. Registers can be designed using discrete flip-flops (S- R, J-K, and D-type). The
data in a shift register can be shifted in two possible ways: (a) serial shifting and (b) parallel shifting. The
serial shifting method shifts one bit at a time for each clock pulse in a serial manner, beginning with either
LSB or MSB. On the other hand, in parallel shifting operation, all the data (input or output) gets shifted
simultaneously during a single clock pulse. Hence, we may say that parallel shifting operation is much
faster than serial shifting operation.

8- bit Universal Shift Register: IC 74195 is a 4-bit TTL MSI having both serial/parallel input and
serial/parallel output capability. The pinout diagram of IC 74195 is shown in Figure 1.
 lOMoARcPSD|284 453 49

When the SH / LD input is LOW, the data on the parallel inputs, i.e., A, B, C, and D are entered
synchronously on the positive transition of the clock. When SH / LD is HIGH, the stored data will shift
right (QA to QD) synchronously with the clock. J and K are the serial inputs to the first stage of the register
(QA); QD can be used for getting a serial output data. The active low clear is asynchronous.
 lOMoARcPSD|284 453 49

Example:
Right Shift Operation: :Input data: 1011
Clock QA QB QC QD
0 1 0 1 1
1 0 1 0 1
2 0 0 1 0
3 0 0 0 1
4 0 0 0 0
1 0 0 1 1 0 0 1

0 1 0 0 1 1 0 0
PROCEDURE:
1. Load data using parallel loading
2. Use clock 1(9)
3. Mode Control 6 OFF (0) connect logic input switch
4. Serial input 1 OFF (0) connect logic input switch
5. Press the clock button

Example:
Rotate Right Operation: Input data: 1011

Clock QA QB QC QD
0 1 0 1 1
1 1 1 0 1
2 1 1 1 0
3 0 1 1 1
4 1 0 1 1
 lOMoARcPSD|284 453 49

1 0 1 1 0 0 0 1

PROCEDURE:

1. Load data using parallel loading

2. Use clock 1(9)
3. Mode Control 6 OFF (0) connect logic input switch
4. Serial input 1 connects to the QD logic output switch
5. Press the clock button

Viva questions
1. What do you mean by serial data?
2. What do you mean by parallel data?
3. What do you mean by serial data transfer?
4. What is a single bit register?
5. What is a register?
6. What do you mean by the storage capacity of a register?
7. What do you mean by loading a register?
8. What are the types of loading the registers?
9. What is serial loading?
10. What is parallel loading?

RESULT:
Thus the 4-bit Universal Shift Register was studied successfully.
 lOMoARcPSD|284 453 49

EXPERIMENT:
DATE:
simulator based study of computer architecture

A computer architecture simulator is a program that simulates

the execution of computer architecture.

Computer architecture simulators are used for the following purposes:

 Lowering cost by evaluating hardware designs without building

physical hardware systems.
 Enabling access to unobtainable hardware.
 Increasing the precision and volume of computer performance
data.
 Introducing abilities that are not normally possible on real
hardware such as running code backwards when an error is
detected or running in faster-than-real time.

Categories

Computer architecture simulators can be classified into many different

categories depending on the context.

 Scope: Microarchitecture simulators model

the microprocessor and its components. Full-system simulators
also model the processor, memory systems, and I/O devices.
 Detail: Functional simulators, such as instruction set simulators,
achieve the same function as modeled components. They can be
simulated faster if timing is not considered. Timing simulators
are functional simulators that also reproduce timing. Timing
simulators can be further categorized into digital cycle-accurate
and analog sub-cycle simulators.
 lOMoARcPSD|284 453 49

 Workload: Trace-driven simulators (also called event-driven

simulators) react to pre-recorded streams of instructions with
some fixed input. Execution-driven simulators allow dynamic
change of instructions to be executed depending on different
input data.

Full-system simulators

A full-system simulator is execution-driven architecture simulation at

such a level of detail that complete software stacks from real systems can
run on the simulator without any modification. A full system simulator
provides virtual hardware that is independent of the nature of the host
computer. The full-system model typically includes processor
cores, peripheral devices, memories, interconnection buses,
and network connections. Emulators are full system simulators that
imitate obsolete hardware instead of under development hardware.

The defining property of full-system simulation compared to

an instruction set simulator is that the model allows real device
drivers and operating systems to be run, not just single programs. Thus,
full-system simulation makes it possible to simulate individual computers
and networked computer nodes with all their software, from network
device drivers to operating systems, network stacks, middleware, servers,
and application programs.

Full system simulation can speed the system development process by

making it easier to detect, recreate and repair flaws. The use of multi-core
processors is driving the need for full system simulation, because it can be
extremely difficult and time-consuming to recreate and debug errors
without the controlled environment provided by virtual hardware. [1] This
also allows the software development to take place before the hardware is
ready,[2] thus helping to validate design decisions.
 lOMoARcPSD|284 453 49

Cycle-accurate simulator

A cycle-accurate simulator is a computer program that simulates

a microarchitecture on a cycle-by-cycle basis. In contrast an instruction
set simulator simulates an instruction set architecture usually faster but
not cycle-accurate to a specific implementation of this architecture; they
are often used when emulating older hardware, where time precision is
important for legacy reasons. Often, a cycle-accurate simulator is used
when designing new microprocessors – they can be tested, and
benchmarked accurately (including running full operating system, or
compilers) without actually building a physical chip, and easily change
design many times to meet expected plan.

Cycle-accurate simulators must ensure that all operations are executed in

the proper virtual (or real if it is possible) time – branch prediction, cache
misses, fetches, pipeline stalls, thread context switching, and many other
subtle aspects of microprocessors.

Viva questions

1.Define computer architecture

2.What are the three categories of computer architecture?

3.What are some of the components of a microprocessor?
4.What is MIPS?
5.What are the different hazards?
6.What is pipelining?
7.What is a cache?
8.What are the types of memory?
 lOMoARcPSD|284 453 49

Aim: - Implementation of 4-bit parallel adder, using 7483 IC.

EXPERIMENT:
DATE:
4 Bit Parallel Adder

Apparatus:-

1. Digital Trainer Kit.

2. IC 7483

3. Connecting Wires

Theory:-

Adder: - An adder is a logic circuit which adds two or three bits at a

time and give sum andcarry as the result.

Parallel Adder:-
A n-bit parallel adder can be constructed using number of full adders
circuit connected inparallel the carry output of each is connected to the
carry input of the next higher-order adder. Since all the bits of the
augends and addend are fed into the adder circuits simultaneously
and the additions in each position are known as parallel adder.

A3 A2 A1
A0 → Augends bitsB3 B2 B1 B0→ Addend bitsS3 S2 S1 S0 → Sum
bits

LOGIC DIAGRAM OF BCD ADDER

 lOMoARcPSD|284 453 49

Pin diagram of IC 7483

Procedure:-
1 .Conn ect grou nd and Vcc to 7483 IC fro m tr aine r kit th rough pat ch cords.
2. Conn ect in puts A0, A1, A2, A3 a nd B0, B1, B2, B3 to logi c in
put swi tches.
3. Connect carry in from pin no.13 to ground so that
carry input (CY1) will be logic ‘0’state.
4. Connect S0, S1, S2, S3 and carry out (CY0) from pin nos. 9, 6, 2, 15
and 14 to the outputdisplay.5.V e rif y truth tabl es fo r diff erent
combin ations of in puts.

TRUTH TABLE:-
The Truth table operation of the 4-bit Parallel Adder is shown below:

INPUT OUTPUTS
S
A0 A1 A2 A3 B0 B1 B2 B3 CY1 S0 S1 S2 S3 CY0
0 0 0 1 0 1 0 1 1 1 1 0 0 1
1 0 0 0 1 1 1 0 0 0 0 0 0 1

Result:-

For various combinations of selected input lines, observed the LED output
and verified the truth table.
 lOMoARcPSD|284 453 49

ROHINI COLLEGE OF ENGINEERING AND

TECHNOLOGY
Accredited by NAAC with A+ Grade
Paulkulam , Kanyakumari District – 629401.
Department of Computer Science and Engineering
CS3351-DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION
VIVA Questions and Answers

1) What is the difference between Latch And Flip-flop?

The difference between latches and Flip-flop is that the latches are level triggered and
flip-flops are edge triggered. In latches level triggered means that the output of the
latches changes as we change the input and edge triggered means that control signal
only changes its state when goes from low to high or high to low.

Latches are fast whereas flip-flop is slow.

2) What is the binary number system?

The system which has a base 2 is known as the binary system and it consists of only two
digits 0 and 1.

3) State the De Morgan's Theorem?

De Morgan's Theorem stated two theorems:

1.The complement of a product of two numbers is the sum of the complements of those
numbers.

(A. B)' = A' + B'

Truth Table:

2. The complement of the sum of two numbers is equal to the product of the complement
of two numbers.

(A + B)' = A'B'

Truth Table:
 lOMoARcPSD|284 453 49

4) Define Digital System?

Digital systems are the system that processes a discrete or digital signal.

5) What is meant by a bit?

Bits are the binary digits like 0 and 1.

6) What is the best Example of Digital system?

Digital Computer.

7) How many types of number system are there?

There are four types of number system:

1. Decimal Number System.

2. Binary Number System.
3. Octal Number System.
4. Hexadecimal Number System.

8) What is a Logic gate?

The basic gates that make up the digital system are called a logic gate. The circuit that
can operate on many binary inputs to perform a particular logic function is called an
electronic circuit.

9) What are the basic Logic gates?

There are three basic logic gates-

1. AND gate.
2. OR gate.
3. NOT gate.

10) Which gates are called as Universal gate and what are its
advantages?
 lOMoARcPSD|284 453 49

The Universal gates are NAND and NOR. The advantages of these gates are that they can
be used for any logic calculation.

11) What are the applications of the octal number system?

The applications of the octal number system are as follows:

1. For the efficient use of microprocessors.

2. For the efficient use of digital circuits.
3. It is used to enter binary data and display of information.

12) What are the fundamental properties of Boolean algebra?

The basic properties of Boolean algebra are:

1. Commutative Property.
2. Associative Property.
3. Distributive Property.

13) What are Boolean algebra and Boolean expression?

14) What is meant by K-Map or Karnaugh Map?

K-Map is a pictorial representation of truth table in which the map is made up of cells,
and each term in this represents the min term or max term of the function. By this
method, we can directly minimize the Boolean function without following various steps.

15) Name the two forms of Boolean expression?

The two forms of Boolean expression are:

1. Sum of products (SOP) form.

2. The Product of sum (POS) form.

16) What are Minterm and Maxterm?

A minterm is called Product of sum because they are the logical AND of the set of
variables and Maxterm are called sum of product because they are the logical OR of the
set of variables.
 lOMoARcPSD|284 453 49

17) Write down the Characteristics of Digital ICs?

The characteristics of digital ICs are -

1. Propagation delay.
2. Power Dissipation.
3. Fan-in.
4. Fan-out.
5. Noise Margin.

18) What are the limitations of the Karnaugh Map?

The limitations of Karnaugh Map are as follows:

1. It is limited to six variable maps which means more than six variable involving
expressions are not reduced.
2. These are useful for only simplifying Boolean expression which is represented I
standard form.

19) What are the advantages and disadvantages of the K-Map

Method?
The advantages of the K-Map method are as follows-

1. It is an excellent method for simplifying expression up to four variables.

2. For the logical simplification, it gives us a visual method.
3. It is suitable for both SOP and POS forms of reduction.
4. It is more suitable for classroom teachings on logic simplification.

The disadvantages of the K-Map method are as follows:

1. It is not suitable when the number of variables exceeds more than four.
2. For Computer reduction, it is not suitable.
3. We have to take while entering the numbers in the cell-like 0, 1 and don't care terms.

20) What are the advantages and disadvantages of Quine-MC

Cluskey method?
21) Define Pair, Quad, and Octet?
Pair: Two adjacent cell of karnaugh map is called as Pair. It cancels one variable in a K-
Map simplification.

Quad: A Pair of Four adjacent pairs in a karnaugh map is called a quad. It cancels two
variables in a K-Map simplification.
 lOMoARcPSD|284 453 49

Octet: A Pair of eight adjacent pair in a karnaugh map is called an octet. It cancels four
variables in a K-map simplification.

22) Define Fan-in and Fan-out?

Fan-in- The Fan-in of the gate means that the number of inputs that are connected to
the gate without the degradation of the voltage level of the system.

Fan-out- The Fan-out is the maximum number of same inputs of the same IC family that
a gate can drive maintaining its output levels within the specified limits.

23) Write the definition of the Duality Theorem?

Duality Theorem states that we can derive another Boolean expression with the existing
Boolean expression by:

1. Changing OR operation (+ Sign) to AND operation (. Dot Sign) and vice versa.
2. Complimenting 0 and 1 in the expression by changing 0 to 1 and 1 to 0 respectively.

24) What is Half-Adder?

Half-adder is the circuits that perform the addition of two bits. It has two inputs A and
B and two outputs S (sum) and C (carry). It is represented by XOR logic gate and an AND
logic gate.

Truth Table of Half adder:

25) What is Full-Adder?

Full-adder is the circuits that perform the addition of three bits. It has three inputs A, B
and a carry bit. Full adders are represented with AND, OR and XOR logic gate.
 lOMoARcPSD|284 453 49

Truth Table of Full-Adder

26) What is power dissipation?

Period time is the electrical energy used by the logic circuits. It is expressed in milliwatts
or nanowatts.

Power dissipation = Supply voltage * mean current taken from the supply.

27) What is a Multiplexer?

The multiplexer is a digital switch which combines all the digital information from
several sources and gives one output.

28) What are the applications of Multiplexer (MUX)?

The applications of the multiplexer are as follows:

1. It is used as a data selector from many inputs to get one output.

2. It is used as A/D to D/A Converter.
3. These are used in the data acquisition system.
4. These are used in time multiplexing system.
 lOMoARcPSD|284 453 49

29) What is a Demultiplexer?

The demultiplexer is a circuit that receives the input on a single line and transmits this
onto 2n possible output line. A Demultiplexer of 2n outputs has n select lines, which are
used to select which output line is to be sent to the input. The demultiplexer is also called
as Data Distributor.

30) What are the applications of Demultiplexer?

The applications of the demultiplexer are as follows:

1. It is used in the data transmission system with error detection.

2. It is used as a decoder for the conversion of binary to decimal.
3. It is used as a serial to parallel converter.

31) What are the differences between Combinational Circuits and

Sequential Circuits?
The differences between combinational and sequential circuits are as follows:

S.No Combinational Circuits Sequential Circuits

1. These are faster in speed. These are slower.

2. These are easy to design. These are difficult to design.

3. The clock input is not required. The clock input is required.

4. In this, the memory units are not required. In this, the memory units are required to stor
of inputs.

5. Example: Mux, Demux, encoder, decoder, adders, Example: Shift registers, counters.
subtractors.

32) Define Rise Time?

Rise time is the time that is required to change the voltage level from 10% to 90%.

33) Define fall time?

Fall time is the time that is required to change the voltage level from 90% to 10%.
 lOMoARcPSD|284 453 49

34) Define Setup time?

The minimum time that is required to maintain the constant voltage levels at the
excitation inputs of the flip-flop device before the triggering edge of the clock pulse for
the levels to be reliably clocked in the flip flop is called the Setup time. It is denoted as
tsetup.

35) Define Hold time?

The minimum time at which the voltage level becomes constant after triggering the
clock pulse in order to reliably clock into the flip flop is called the Hold time. It is denoted
by thold.

36) What is the difference between Synchronous and

Asynchronous Counters?
The difference between Synchronous and Asynchronous Counters are as follows:

S.No Asynchronous Counters Synchronous Counters

1. These are low-speed Counters. These are high-speed Counters.

2. The Flip flops of these counters are not clocked In these counters, the flip-flops are clocke
simultaneously.

3. Simple logic circuits are there for more number of states. Complex logic circuits are there when t
increases.

37) What are the applications of Flip-Flops?

The applications of flip-flops are:

1. Flip-flops are used as the delay element.

2. These are used for Data transfer.
3. Flip-flops are used in Frequency Division and Counting.
4. Flip-Flops are used as the memory element.

38) What is the difference between D-latch and D Flip-flop?

 lOMoARcPSD|284 453 49

D-latch is level sensitive whereas flip-flop is edge sensitive. Flip-flops are made up of
latches.

39) What are the applications of Buffer?

Applications of buffer are as follows:

1. Buffer helps to introduce small delays.

2. Buffer helps for high Fan-out.
3. Buffer are used to eliminate cross talks.