Electrical Engineering Dept.

COME321: Computer Organization

(Fall 2024)
Dr. Eng. Ghada Abozaid

[email protected]
 BASIC COMPUTER
ORGANIZATION AND DESIGN
Agenda

 5.6 Memory Reference Instructions

 5.7 Input-Output and Interrupt

 5.8 Complete Computer Description

 5.9 Design of Basic Computer

 5.10 Design of Accumulator Logic

 Basic Computer Instructions

• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation

Instructions
BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off Instructions
Determine The Type of Instruction
Start
SC  0

AR  PC T0

IR  M[AR], PC  PC + 1 T1

Decode Opcode in IR(12-14), T2

AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I
T3 T3 T3
T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute
memory-reference T4
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr. Instruction Cycle
Common Bus System
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR
E
ALU AC 4
LD INR CLR
INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus Registers
 Memory Reference Instructions
MR Instructions

Operation
Symbol Decoder Symbolic Description
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1

-Memory cycle is assumed to be short enough to complete in a CPU cycle

- The execution of MR instruction starts with T4

 Memory Reference Instructions

AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC

ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E

LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0

STA: Store AC
D3T4: M[AR]  AC, SC  0

MR Instructions
Memory Reference Instructions

BUN: Branch Unconditionally

D4T4: PC  AR, SC  0

BSA: Branch and Save Return Address

M[AR]  PC, PC  AR + 1

Memory, PC, AR at time T4 Memory, PC after execution

20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory
Memory Reference Instructions

BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

MR Instructions
Flowchart For Memory Reference Instructions

Memory-reference instruction

LDA
AND ADD STA

D T D T D T D T3 4
0 4 1 4 2 4
M[AR]  AC
DR  M[AR] DR  M[AR] DR  M[AR]
SC  0

D T D T D T
0 5 1 5 2 5
AC  AC DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

MR Instructions
Flowchart For Memory Reference Instructions

Memory-reference instruction

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5 T 5 D6 T 5

PC  AR DR  DR + 1
SC  0
D6 T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0

MR Instructions
 INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer

• Input-Output Configuration
Input-output Serial Computer
terminal communication registers and
interface
flip-flops
Receiver
Printer interface OUTR FGO

INPR Input register - 8 bits AC

OUTR Output register - 8 bits
FGI Input flag - 1 bit Transmitter
FGO Output flag - 1 bit Keyboard interface INPR FGI
IEN Interrupt enable - 1 bit Serial Communications Path
Parallel Communications Path
-When a key is struck in the keyboard.
- The terminal sends and receives serial information
-The serial info. from the keyboard is shifted an 8 bit
alphanumeric code into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the computer.
I/O and Interrupt
 PROGRAM CONTROLLED DATA TRANSFER
-- CPU -- -- I/O Device --
/* Input */ /* Initially FGI = 0 */ loop: If FGI = 1 goto loop
loop: If FGI = 0 goto loop
INPR  new data, FGI  1
AC  INPR, FGI  0

/* Output */ /* Initially FGO = 1 */ loop: If FGO = 1 goto loop

loop: If FGO = 0 goto loop consume OUTR, FGO  1
OUTR  AC, FGO  0
FGO=1
FGI=0
Start Output
Start Input

FGI  0 AC  Data

yes yes
FGI=0 FGO=0
no no

AC  INPR OUTR  AC

FGO  0
yes More
Character yes More
Character
no
END no
END I/O and Interrupt
INPUT-OUTPUT INSTRUCTIONS
Input-Output Instructions (OP-code =111, I = 1)
15 12 11 0
1 1 1 1 I/O operation

D7IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off
PROGRAM-CONTROLLED INPUT/OUTPUT
• Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware
Input

LOOP, SKI DEV

BUN LOOP
INP DEV

Output
LOOP, LDA DATA
LOP, SKO DEV
BUN LOP
OUT DEV
I/O and Interrupt
 INTERRUPT INITIATED INPUT/OUTPUT
- Open communication only when some data has to be passed --> interrupt.

- The I/O interface, instead of the CPU, monitors the I/O device.

- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU

- Upon detecting an interrupt, the CPU stops momentarily the task

it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.

* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions

- when cleared, the computer cannot be interrupted
 FLOWCHART FOR INTERRUPT CYCLE
R = Interrupt f/f
Instruction cycle =0 =1 Interrupt cycle
R

Fetch and decode Store return address

instructions in location 0
M[0]  PC

Execute =0
IEN
instructions
=1 Branch to location 1
PC  1
=1
FGI
=0
=1 Indirect BUN 0
FGO IEN  0
=0 R0
R1

- The interrupt cycle is a HW implementation of a branch

and save return address operation.
- At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine
- The instruction that returns the control to the original
program is "indirect BUN 0"
I/O and
REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE
Memory
Before interrupt After interrupt cycle
0 0 256
1 0 BUN 1120 PC = 1 0 BUN 1120

Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program

1 BUN 0 1 BUN 0

Register Transfer Statements for Interrupt Cycle

- R F/F  1 if IEN (FGI + FGO)T0T1T2
 T0T1T2 (IEN)(FGI + FGO): R  1

- The fetch and decode phases of the instruction cycle

must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
I/O and Interrupt
 COMPLETE COMPUTER DESCRIPTION
Flowchart of Operations
start
SC  0, IEN  0, R  0

=0(Instruction =1(Interrupt
R
Cycle) Cycle)
R’T0 RT0
AR  PC AR  0, TR  PC
R’T1 RT1
IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0
R’T2 RT2
AR  IR(0~11), I  IR(15) PC  PC + 1, IEN  0
D0...D7  Decode IR(12 ~ 14) R  0, SC  0

=1(Register or I/O) D7 =0(Memory Ref)

=1 (I/O) =0 (Register) =1(Indir) =0(Dir)

I I

D7IT3 D7I’T3 D7’IT3 D7’I’T3

Execute Execute AR <- M[AR] Idle
I/O RR
Instruction Instruction
Execute MR D7’T4
Instruction

Description
COMPLETE COMPUTER DESCRIPTION
Microoperations

Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
Indirect D7IT3: AR  M[AR]
Interrupt
T0T1T2(IEN)(FGI + FGO): R1
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
Memory-Reference
AND D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
ADD D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0
LDA D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA D3T4: M[AR]  AC, SC  0
BUN D4T4: PC  AR, SC  0
BSA D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if(DR=0) then (PC  PC + 1),
SC  0

Description
COMPLETE COMPUTER DESCRIPTION
Microoperations

Register-Reference
D7IT3 = r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC
CME rB8: E  E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: If(AC(15) =0) then (PC  PC + 1)
SNA rB3: If(AC(15) =1) then (PC  PC + 1)
SZA rB2: If(AC = 0) then (PC  PC + 1)
SZE rB1: If(E=0) then (PC  PC + 1)
HLT rB0: S0

Input-Output D7IT3 = p (Common to all input-output instructions)

IR(i) = Bi (i = 6,7,8,9,10,11)
p: SC  0
INP pB11: AC(0-7)  INPR, FGI  0
OUT pB10: OUTR  AC(0-7), FGO  0
SKI pB9: If(FGI=1) then (PC  PC + 1)
SKO pB8: If(FGO=1) then (PC  PC + 1)
ION pB7: IEN  1
IOF pB6: IEN  0
Description
 DESIGN OF BASIC COMPUTER(BC)
Hardware Components of BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops(Status):
I, S, E, R, IEN, FGI, and FGO
Decoders: a 3x8 Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC

Control Logic Gates

- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit
Design of Basic Computer
 CONTROL OF REGISTERS AND MEMORY
Address Register; AR
Scan all of the register transfer statements that change the content of AR:
R’T0: AR  PC LD(AR)
R’T2: AR  IR(0-11) LD(AR)
D’7IT3: AR  M[AR] LD(AR)
RT0: AR  0 CLR(AR)
D5T4: AR  AR + 1 INR(AR)

LD(AR) = R'T0 + R'T2 + D'7IT3

CLR(AR) = RT0
INR(AR) = D5T4

12 12
From bus AR To bus
D'7
I
LD Clock
T3
T2 INR
CLR
R
T0
D
T4

Design of Basic Computer

 CONTROL OF FLAGS

IEN: Interrupt Enable Flag

pB7: IEN  1 (I/O Instruction)
pB6: IEN  0 (I/O Instruction)
RT2: IEN  0 (Interrupt)

p = D7IT3 (Input/Output Instruction)

D
7
p
I J IEN
Q
B7
T3

B6
K
R
T2

Design of Basic Computer

CONTROL OF COMMON BUS

x1
x2 S2
Multiplexer
x3
Encoder S1 bus select
x4
x5 inputs
x6 S0
x7

selected
x1 x2 x3 x4 x5 x6 x7 S2 S1 S0 register
0 0 0 0 0 0 0 0 0 0 none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory

For AR D4T4: PC  AR
D5T5: PC  AR

x1 = D4T4 + D5T5

Design of Basic Computer

 DESIGN OF ACCUMULATOR LOGIC
Circuits associated with AC 16
Adder and
16 16 16
From DR logic AC
8 circuit To bus
From INPR

LD INR CLR Clock

Control
gates

All the statements that change the content of AC

D0T5: AC  AC  DR AND with DR
D1T5: AC  AC + DR Add with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7)  INPR Transfer from INPR
rB9: AC  AC Complement
rB7 : AC  shr AC, AC(15)  E Shift right
rB6 : AC  shl AC, AC(0)  E Shift left
rB11 : AC  0 Clear
rB5 : AC  AC + 1 Increment
Design of AC Logic
 CONTROL OF AC REGISTER

Gate structures for controlling

the LD, INR, and CLR of AC

From Adder 16 16 To bus

and Logic AC
D0 AND LD Clock
T5 INR
D1 ADD CLR
D2 DR
T5
p INPR
B11
r COM
B9
SHR
B7
SHL
B6
INC
B5
CLR
B11 Design of AC Logic
ALU (ADDER AND LOGIC CIRCUIT)

One stage of Adder and Logic circuit

DR(i)
AC(i)

AND

Ci ADD LD
FA Ii J Q
DR AC(i)
C i+1

INPR K
From
INPR
bit(i)
COM

SHR
AC(i+1)
SHL
AC(i-1)

Design of AC Logic
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