Massachusetts Institute of Technology

Department of Electrical Engineering and Computer Science

6.012
Microelectronic Devices and Circuits
Spring 2007
February 28, 2007 - Homework #3
Due - March 9, 2007
_____________________________________________________________

Problem 1

The device drawn below is biased as shown, and a capacitance-voltage (C-V)

measurement is taken. The area of the device is 10-6 cm2. Assume the electrostatic
potential in the n+ silicon region, φn+=550mV.

A plot of (1/C)2 as a function of the DC voltage, V, where C is the capacitance is shown

below. The device is in reverse bias. The slope, S, is -4.8 * 1026 F-2 V-1.
NOTE: The polarity of the DC source is now shown correctly.
 a) Derive an expression for the doping, Na, in the p-type region in terms of the slope
S, shown in the plot, and other known parameters (e.g. constants like q εSi, the
device area).
b) Assume now that Na is 1016 cm-3. Estimate the DC voltage V’ where the slope of
the plot of (1/C)2 vs. voltage changes, as seen in the graph.

C jO × A ⎛ 1 ⎞
2
1−V
φB φ −V
a) C j (V ) = ⎯→⎜
⎯ ⎟ = = 2 B2
⎜C ⎟ C jO × A
2 2
φ B × C jO × A 2
1− V ⎝ j ⎠
φB
−1 q × ε Si × N a
Slope, S = C jO =
φ × C 2jO × A 2
2
B 2 × φB
−2
Na =
A × q × ε Si × S
2

Plugging in the numbers, we find Na=2.5 x 1016 cm-3. The numerical answer is not
necessary.

b) The slope will change when the 1 micron wide p-type region is completely depleted,
i.e., xd=1 micron.

x d (V ) = x dO × 1 − V '
φB

φ B = φ n + − φ p = .55 − (− .36) = 0.91V

 2 × ε Si × φ B
x dO = = 3.44 × 10 −5 cm
q × Na

xd 10 −4 cm
= 1−V '
x dO φ B = 3.44 × 10 −5 cm = 2.91

Solving for V`, we find

V ' = −6.8V

Problem 2

A metal-oxide-semiconductor (MOS) device is pictured below. Tox is 15nm. Assume

φn+=0.55V, and that Na in the p region is 1017 cm-3.

a) Find the threshold voltage of this device.

b) What applied bias leads to a sheet charge density in the inversion layer, QN, of -
10-6 C/cm2?
c) What is the value of Eox, the field in the oxide, when the charge on the gate, QG=
10-6 C/cm2?

a) The threshold voltage is the VGB applied to make the potential at x=0 equal to -φp.

First find the flatband voltage, VFB.

V FB = −(φ gate − φbulk ) = −(.55 + .42) = −0.97V

VT = VFB − 2φ p + 1 × 2 × q × ε Si × N a × (− 2φ p )
C ox
C ox =
ε SiO 2 = 2.3 × 10 −7 F
t ox cm 2

Plugging these values into the threshold voltage equation:

VT = 0.58V

b) Above threshold, we know how to relate the inversion charge, QN, to the applied gate
to bulk voltage through the following equation.

− 10 −6 C
Q N = −C ox (VGB − VT ) ⎯
⎯→VGB = 0.58V − cm 2 = 4.9V
2.3 × 10 −7 F 2
cm

c) We can use Gauss’s law to find the magnitude of the electric field in the oxide.

QG
E ox =
ε SiO 2 = 2.9 × 10 cm
6V

Problem 3

Shown below is a capacitance-voltage plot for an MOS capacitor. The gate is n+,
therefore you can assume its potential is 550mV. The silicon dioxide thickness is 15nm,
and the body is doped with some concentration of acceptors, Na.

a) Determine the threshold voltage, VT, and the flatband voltage, VFB, on the C-V
plot.
b) Specify the range of voltages where the MOS capacitor is in inversion, depletion,
and accumulation.
c) Calculate the doping concentration in the body, Na, from the given information
d) Now assume the gate is doped p+, so the potential of the gate is -550mV. Sketch
the C-V, labeling VT and VFB.
a) By looking at the shape of the C-V, we know that -.91V is the flatband voltage, and
-0.067V is the threshold voltage. Since our substrate is p-type, as we go to voltages more
positive than VT, we will be balancing the positive charge on the gate with free electrons
in the inversion layer. As we go to voltages more negative than VFB, we will be
balancing negative charge on the gate with free holes in the accumulation layer.

b) Accumulation: V ≤ −0.91V , Depletion: − 0.91V < V < −0.067V

Inversion: V ≥ −0.067V

c) We can most easily calculate the doping concentration from the flatband voltage.

⎛ ⎛ ⎛N ⎞ ⎞ ⎞⎟
V FB = −(φ gate − φ bulk ) = −⎜ .55V − ⎜⎜ − 60mV × log⎜⎜ a ⎟⎟ ⎟ = −0.91V
⎟
⎜ ⎝ ni ⎠ ⎠ ⎟⎠
⎝ ⎝
N a = 1016 cm −3

d) By changing the gate from n+ to p+, we change the gate’s potential from 550mV to -
550mV. That results in a translation of the C-V 1100mV to the right.

Problem 4

It is sometimes useful in analog circuits to use a transistor biased in triode as a voltage

controlled resistor. Use the following parameters to design a p-channel MOSFET with a
resistance of 100KΩ.
µpCox=25µA/V2 VTp= -1V VGS=-1.2V VBS=0V

a) If the device has a width of 10µm, what is the necessary length?

b) What is the necessary width to get a 10KΩ resistor, if the length is 5µm?
a) When the MOSFET is in the linear region, it behaves like a voltage controlled resistor.
The resistance of a PMOSFET in the linear region can be written as:

1
R=
µ p × C ox × × (VSG + VTp )
W
L

Now, we can solve for the length to achieve a resistance of 100KΩ.

1
100 KΩ = ⎯→ L = 5µm
⎯
µ 10
25 A × × (VSG − 1)
V2 L

b) We will use the same equation and solve for the width.

1
10 KΩ = ⎯→ W = 100 µm
⎯
25 µA × × (VSG − 1)
W
V2 5

Problem 5

Hafnium dioxide (HfO2, ε= 25) is an attractive replacement for silicon dioxide as a gate
dielectric due to its high dielectric constant.

Consider an n-channel MOSFET. The channel length, L = 2µm, the width, W = 30µm,
the electron mobility is µn = 300 cm2V-1s-1 and the substrate doping is Na = 1017cm-3.
Assume the gate is n+ silicon, so its potential is 550mV.

a) What thickness of HfO2 is needed for VTn = 0.5 V?

b) Find the backgate effect parameter, γn for the hafnium dioxide gate insulator
thickness from (a).
c) If I=5µA, what is VGS? Assume saturation. What is the minimum drain voltage
to ensure saturation?

a) First calculate the flatband voltage.

V FB = −(φ gate − φbulk ) = −(.55V − (− .42V )) = −0.97V

VT = 0.5V = V FB − 2φ p + 1 × 2 × q × ε Si × N a × (− 2φ p )
C ox
ε HfO 2
C ox =
t ox
Plugging in the known quantities and solving for tox:
tox=85 nanometers

b)
2 × ε Si × q × N a
γn =
C ox

ε HfO 2 2.21 × 10 −12 F

C ox = = cm = 2.6 × 10 −7 F
t ox −7
85 × 10 cm cm 2

2 × ε Si × q × N a
γn = = 0.687V 1 / 2
C ox

c) The drain current equation for an NMOSFET in saturation is shown below.

1 W
× × µ n × C ox × (VGS − VT )
2
Id =
2 L

If Id is 5µA, we can solve for VGS.

1 30
5µA = × × 300 × 2.6 × 10 −7 (VGS − 0.5) ⎯
2
⎯→VGS = 0.59V
2 2

To ensure saturation, the drain source voltage, VDS, must be greater than or equal to
VDS,SAT=VGS-VT=.09V. Therefore, the minimum drain source voltage to ensure
saturation is 0.09V.