Chapter 2

Introduction to Logic Circuits

x = 0 x = 1

(a) Two states of a switch

(b) Symbol for a switch

Figure 2.1. A binary switch.

 S
Battery x Light

(a) Simple connection to a battery

S
Power
supply x Light

(b) Using a ground connection as the return path

Figure 2.2. A light controlled by a switch.

 S S
Power x1
supply x2 Light

(a) The logical AND function (series connection)

x1

Power
supply S Light

x2

(b) The logical OR function (parallel connection)

Figure 2.3. Two basic functions.

 S

X1
S
Power
supply S X3 Light

X2

Figure 2.4. A series-parallel connection.

 R

Power
supply x S Light

Figure 2.5. An inverting circuit.

Figure 2.6. A truth table for the AND and OR operations.
Figure 2.7. Three-input AND and OR operations.
 x1
x2
x1
x1 ⋅ x2 x1 ⋅ x2 ⋅ … ⋅ xn
x2

xn

(a) AND gates

x1
x2
x1
x1 + x2 x1 + x2 + … + xn
x2

xn

(b) OR gates

x x

(c) NOT gate

Figure 2.8. The basic gates.
x
1
x
2 f = (x + x ) ⋅ x
x 1 2 3
3

Figure 2.9. The function from Figure 2.4.

Figure 2.10. An example
of logic networks.
Figure 2.11. An example of a logic circuit.
Figure 2.12. Addition of binary numbers.
Figure 2.13. Proof of DeMorgan’s theorem in 15a.
(a) Constant 1 (b) Constant 0

x x x x

(c) Variablex (d) x

Figure 2.14. The

x y x y Venn diagram
representation.
(e) x ⋅ y (f) x + y

x y
x y
z

(g) x ⋅ y (h) x ⋅ y + z
 x y x y

z z

(a) x (d) x ⋅ y

x y x y

z z

(b) y + z (e) x ⋅ z

x y x y

z z

(c) x ⋅ ( y + z) (f) x ⋅ y + x ⋅ z

Figure 2.15. Verification of the distributive property

x (y + z) = x y + x z
Figure 2.17. Proof of the distributive property 12b.
Figure 2.18. Proof of DeMorgan’s theorem 15a.
Figure 2.19. A function to be synthesized.
 x1
x2

(a) Canonical sum-of-products

x1
f
x2

(b) Minimal-cost realization

Figure 2.20. Two implementations of the function in Figure 2.19.

Figure 2.21. A bubble gumball factory.
Figure 2.22 Three-variable minterms and maxterms.
Figure 2.23. A three-variable function.
 x2

f
x3
x1

(a) A minimal sum-of-products realization

x1
x3
f

x2

(b) A minimal product-of-sums realization

Figure 2.24. Two realizations of a function in Figure 2.23.

 x1
x2
x1
x1 ⋅ x2 x1 ⋅ x2 ⋅ … ⋅ xn
x2

xn

(a) NAND gates

x1
x2
x1
x1 + x2 x1 + x2 + … + xn
x2

xn

(b) NOR gates

Figure 2.25. NAND and NOR gates.

 x1
x1 x1
x2 x2
x2

(a) x1 x2 = x1 + x2

x1
x1 x1
x2 x2
x2

(b) x1 + x2 = x1 x2

Figure 2.26. DeMorgan’s theorem in terms of logic gates.

 x1 x1
x2 x2
x3 x3
x4 x4
x5 x5

x1
x2
x3
x4
x5

Figure 2.27. Using NAND gates to implement a sum-of-products.

 x1 x1
x2 x2

x3 x3
x4 x4
x5 x5

x1
x2

x3
x4
x5

Figure 2.28. Using NOR gates to implement a product-of sums.

 x1

x2 f

x3

(a) POS implementation

x1

x2 f

x3

(b) NOR implementation

Figure 2.29 NOR-gate realization of the function in Example 2.11.

 x1

f
x2

x3

(a) SOP implementation

x1

f
x2

x3

(b) NAND implementation

Figure 2.30. NAND-gate realization of the function in Example 2.10.

Figure 2.31. Truth table for a three-way light control.
 f

x1
x2
x3
(a) Sum-of-products realization

x3
x2
x1

Figure 2.32. Implementation

of the function in Figure 2.31.
(b) Product-of-sums realization
s x1 x 2 f (s, x1, x2)
000 0
s f (s, x1, x2)
001 0
0 x1
010 1
1 x2
011 1
100 0 (d) More compact truth-table representation
101 1
110 0
111 1

(a)Truth table

x1 s

f x1 0
f
s x2 1
x2

(b) Circuit (c) Graphical symbol

Figure 2.33. Implementation of a multiplexer.

Figure 2.36. The logic circuit for a multiplexer.
Figure 2.37. Verilog code for the circuit in Figure 2.36.
 module example2 (x1, x2, x3, x4, f, g, h);
input x1, x2, x3, x4;
output f, g, h;

and (z1, x1, x3);

and (z2, x2, x4);
or (g, z1, z2);
or (z3, x1, ~x3);
or (z4, ~x2, x4);
and (h, z3, z4);
or (f, g, h);

endmodule

Figure 2.38. Verilog code for a four-input circuit.

Figure 2.39. Logic circuit for the code in Figure 2.38.
Figure 2.40. Using the continuous assignment to specify the circuit in
Figure 2.36.
 module example4 (x1, x2, x3, x4, f, g, h);
input x1, x2, x3, x4;
output f, g, h;

assign g = (x1 & x3) | (x2 & x4);

assign h = (x1 | ~x3) & (~x2 | x4);
assign f = g | h;

endmodule

Figure 2.41. Using the continuous assignment to specify the circuit in

Figure 2.39.
Figure 2.42. Behavioral specification of the circuit in Figure 2.36.
Figure 2.43. A more compact version of the code in Figure 2.42.
Figure 2.44. A logic circuit with two modules.
Figure 2.45. Verilog specification of the circuit in Figure 2.12.
Figure 2.46. Verilog specification of the circuit in Figure 2.34.
Figure 2.47. Hierarchical Verilog code for the circuit in Figure 2.44.
Figure 2.48 The function f (x1, x2, x3) = Σ m(0, 2, 4, 5, 6).
 x1 x2 x1
x2
0 0 m0 0 1
0 1 m1 0 m0 m2
1 0 m2
1 m1 m3
1 1 m3

(a) Truth table (b) Karnaugh map

Figure 2.49. Location of two-variable minterms.

 x1
x2
0 1
0 1 0
f = x2 + x1
1 1 1

Figure 2.50. The function of Figure 2.19.

 x1 x2 x3
x1x2
0 0 0 m0 x3
00 01 11 10
0 0 1 m1
0 m0 m2 m6 m4
0 1 0 m2
0 1 1 m3 1 m1 m3 m7 m5
1 0 0 m4
1 0 1 m5 (b) Karnaugh map
1 1 0 m6
1 1 1 m7

(a) Truth table

Figure 2.51. Location of three-variable minterms.

Figure 2.52. Examples of three-variable Karnaugh maps.
 x1
x1x2
x3x4
00 01 11 10
00 m0 m4 m12 m8

01 m1 m5 m13 m9
x4
11 m3 m7 m15 m11
x3
10 m2 m6 m14 m10

x2

Figure 2.53. A four-variable Karnaugh map.

Figure 2.54. Examples of four-variable Karnaugh maps.
 x1x2 x1x2
x3x4 x3x4
00 01 11 10 00 01 11 10
00 00 1

01 1 1 01 1 1

11 1 1 11 1 1

10 1 1 10 1 1

x5 = 0 x5 = 1

f 1 = x1x3 + x1x3x4 + x1x2x3x5

Figure 2.55. A five-variable Karnaugh map.

 x1x2
x3
00 01 11 10
0 1 1 0 0

1 1 1 1 0

x1 x2x3

Figure 2.56. Three-variable function f (x1, x2, x3) = Σ m(0, 1, 2, 3, 7).

 x1x2
x3x4
00 01 11 10
00 x1x2x4

01 1 1 x2x3x4

11 1 1 1

10 1 1 1 1 x3x4

x1x3 x2x3

Figure 2.57. Four-variable function f ( x1,…, x4) =

Σ m(2, 3, 5, 6, 7, 10, 11, 13, 14).
 x1x2
x3x4
00 01 11 10
x3x4
00 1 1 1 1
x1x2x3
01 1
x1x2x4
11 1 1 x1x3x4

10 1 x1x2x3

x1x2x4

Figure 2.58. The function f ( x1,…, x4) =

Σ m(0, 4, 8, 10, 11, 12, 13, 15).
 x1 x2
x3 x4
00 01 11 10

00 1 1 x 1 x3 x4

01 1 1 x 2 x3 x 4

11 1 1 x 1 x3 x 4

10 1 1
x 2 x3 x 4

x1 x2 x4 x1 x 2 x4
x1 x 2 x3 x 1 x2 x3

Figure 2.59. The function f ( x1,…, x4) =

Σ m(0, 2, 4, 5, 10, 11, 13, 15).
 x1x2
x3
00 01 11 10
0 1 1 0 0 ( x1 + x3)

1 1 1 1 0

( x1 + x2)

Figure 2.60. POS minimization of f (x1, x2, x3) = Π M(4, 5, 6).

 x1 x2
x3x4
00 01 11 10

00 0 0 0 0 ( x3 + x4)

01 0 1 1 0
( x2 + x3)
11 1 1 0 1

10 1 1 1 1

( x1 + x2 + x3 + x4)

Figure 2.61. POS minimization of f ( x1,…, x4) =

Π M(0, 1, 4, 8, 9, 12, 15).
 x x
x3x4 1 2 x1x2
00 01 11 10 x3x4
00 01 11 10
00 0 1 d 0 ( x2 + x3)
00 0 1 d 0
x2 x3
01 0 1 d 0
01 0 1 d 0
11 0 0 d 0
11 0 0 d 0 ( x3 + x4)
10 1 1 d 1 x3 x4
10 1 1 d 1

(a) SOP implementation (b) POS implementation

Figure 2.62. Two implementations of the function f ( x1,…, x4) =

Σ m(2, 4, 5, 6, 10) + D(12, 13, 14, 15).
Figure 2.63. Using don’t-care
minterms when displaying
BCD numbers.
 x1 x2
x3 x4
00 01 11 10
00 1 1 x2
01 1 1 1 x3
x4
11 1 1 f1
x1
10 1 1
x3

(a) Function f 1
x1
x1 x2 x3
x3 x4
00 01 11 10 f2
x2
00 1 1 x3
x4
01 1 1

11 1 1 1 (c) Combined circuit for f 1 and f 2

10 1 1

(b) Function f 2

Figure 2.64. An example of multiple-output synthesis.

 x1x2 x1x2
x3x4 x3 x4
00 01 11 10 00 01 11 10
00 00

01 1 1 1 01 1 1 1

11 1 1 1 11 1 1 1

10 1 10 1

(a) Optimal realization of f 3 (b) Optimal realization of f 4

x1
x1x2 x1x2
x3x4 x3 x4 x4
00 01 11 10 00 01 11 10
x1 f3
00 00
x2
01 1 1 1 01 1 1 1 x4

11 1 1 1 11 1 1 1 x1
x2
10 1 10 1
x3
(c) Optimal realization of f 3 and f 4 together
x4 f4
x2
x4

(d) Combined circuit for f 3 and f 4

Figure 2.65. Another example of multiple-output synthesis.

 x1 x2 x1 x2

x3 x3

(a) Function A (b) Function B

x1 x2 x1 x2

x3 x3

(c) Function C (d) Function f

Figure 2.66. The Venn diagrams for Example 2.23.

Figure 2.67. Karnaugh
maps for Example 2.26.
Figure 2.68. Karnaugh maps
for Example 2.27.
Figure 2.69. A K-map that represents the function in Example 2.28.
Figure 2.70. The logic circuit for Example 2.29.
Figure 2.70. Verilog code for Example 2.29.
Figure 2.72. The circuit for Example 2.30.
Figure 2.73. Verilog code for Example 2.30.
 x3
x3

x1 x2 x1 x2

x4 x4

(a) (b)

Figure P2.1. Two attempts to draw a four-variable Venn diagram.

 m0 x4

x1 x2 x1 x2

m1
x3 m2 x

Figure P2.2. A four-variable Venn diagram.

x1 1
0

x2 1
0

x3 1
0

f 1
0

Time

Figure P2.3. A timing diagram representing a logic function.

x1 1
0

x2 1
0

x3 1
0

f 1
0

Time

Figure P2.4. A timing diagram representing a logic function.

 x1
x3
x4
x1
x3
x4
x1
x2 f
x3
x1
x2 Figure P2.5. Circuit for
x3 problem 2.78.
x4
x2
x4

x3
g
x1
x4
x1
x4