22nm FDSOI Technology for Emerging Mobile,

Internet-of-Things, and RF Applications

R.Carter1, J.Mazurier2, L.Pirro2, J-U.Sachse1, P.Baars1, J.Faul1, C.Grass1, G.Grasshoff1, P.Javorka1, T.Kammler1,
A.Preusse1, S.Nielsen1, T.Heller1, J.Schmidt1, H.Niebojewski2, P-Y.Chou1, E.Smith1, E.Erben1, C.Metze1, C.Bao1,
Y.Andee2, I.Aydin2, S.Morvan2, J.Bernard2, E.Bourjot2, T.Feudel1, D.Harame1, R.Nelluri1, H.-J.Thees1, L.M-Meskamp1,
J.Kluth1, R.Mulfinger1, M.Rashed1, R.Taylor1, C.Weintraub1, J.Hoentschel1, M.Vinet2, J.Schaeffer1, and B.Rice1
1
GLOBALFOUNDRIES Fab1 LLC & Co. KG, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany. Email: [email protected]
2
CEA-LETI Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France

Abstract—22FDXTM is the industry's first FDSOI technology double-patterning steps required at the 16/14nm FinFET
architected to meet the requirements of emerging mobile, technology nodes. Approximately 75% of the process steps
Internet-of-Things (IoT), and RF applications. This platform are common with the 28nm platform enabling high yield
achieves the power and performance efficiency of a 16/14nm capability. The gate-first High-K Metal Gate (HKMG)
FinFET technology in a cost effective, planar device integration is used to ensure a low cost process flow [3]. A
architecture that can be implemented with ~30% fewer typical cross-section of nFET and pFET devices is shown in
masks. Performance comes from a second generation FDSOI Fig.1. All active devices are built on SOI whereas passive
transistor, which produces nFET (pFET) drive currents of devices and select active devices, such as LDMOS, are
910μA/µm (856μA/µm) at 0.8V and 100nA/µm Ioff. For conventionally formed in the bulk substrate (Fig.2). In
ultra-low power applications, it offers low-voltage operation addition to the introduction of FDSOI substrates, new process
down to 0.4V Vmin for 8T logic libraries, as well as 0.62V and modules are introduced to support back-bias capability,
0.52V Vmin for high-density and high-current bitcells, ultra- passive device fabrication, enhanced device performance and
low leakage devices approaching 1pA/µm Ioff, and body- technology scale factor (Fig.3). The introduction of a SiGe
biasing to actively trade-off power and performance. channel for pFET devices by the condensation technique [4]
Superior RF/Analog characteristics to FinFET are achieved and SOI thickness <7nm enable high DC drive currents. A
including high fT/fMAX of 375GHz/290GHz and post STI hybrid etch process is used to form back gate
260GHz/250GHz for nFET and pFET, respectively. The contacts and enable the implementation of devices and tap-
high fMAX extends the capabilities to 5G and milli-meter wave cells in the bulk substrate (Fig.4). Dual in-situ doped epi
(>24GHz) RF applications. processes (Si:P and SiGe:B) are formed in combination with a
low-k spacer to ensure highly doped source/drain regions
I. INTRODUCTION while maintaining low gate-to-drain capacitance (critical for
Rising manufacturing costs and emerging applications RF applications). Technology CPP is scaled without adding
requiring unparalleled energy efficiency are driving the need extra masking steps relative to the 28nm Front-End-of-Line.
for new semiconductor device solutions. For the first time, Dual patterning techniques are used to scale M1/M2 pitch,
an increase in the cost per die is observed with the leading to a logic/SRAM die scaling of 0.72x/0.83x relative to
introduction of 16/14nm FinFET technologies due to the 28nm Poly/SiON technology node.
increased process complexity and mask count. Cost sensitive
IoT and mobile applications are driving new requirements B. Device Performance
such as increased integration, advanced power management, Device construction utilizes either flip well (SLVT/LVT
and high performance RF and analog. devices) or conventional well (RVT/HVT devices) to enable a
The Fully Depleted Silicon-On-Insulator (FDSOI) multiple VT device suite. In the so called flip well
transistor architecture has inherent electrostatic control construction, nFET devices are located on n-type back gates
benefits and very low mismatch capability [1,2], making it a and pFET devices are located on p-type back gates. This
powerful option to fulfil those requirements while keeping configuration is well suited for forward back biasing (FBB),
process cost and complexity low. This paper presents the i.e. increasing performance. In contrast, the conventional well
process architecture, baseline device and yield performance, construction enables the reduction of Ioff leakage by using
the benefits of back-bias in power management, as well as key reverse back biasing to raise the VT. Three gate lengths (20,
platform features of a new FDSOI technology based on 22nm 24, 28nm) are available for each of the four offered VT
design rules. flavors. Devices are measured at back gate voltages from 0V
to 1V (Fig.5). A coupling factor |dVT/dVB| of 75mV/V is
II. TECHNOLOGY OVERVIEW reported. IDS/Ioff DC performance for nFET and pFET devices
A. Process Architecture are reported at Vdd=0.8V (Figs.6-7). IDS=910μA/μm and
The 22nm FDSOI architecture provides maximum die 856μA/μm at Ioff=100nA/μm are achieved with L=20nm and
scaling relative to 28nm while minimizing the expensive W=0.17μm for nFET and pFET, respectively. The FBB

U.S. Government work not protected by U.S. copyright IEDM16-27

2.2.1
 impact is also reported. Extremely low A∆VT mismatch values B. Ultra Low Power
of 1.2/1.4 mV·µm for nFET/pFET are demonstrated (Fig.8). Due to the superior electrostatic properties, circuit
The results on coupling factor, device performance, and VT functionality on logic test vehicles is demonstrated down to a
mismatch are in line with previously reported data for high minimum operating voltage of 0.38V for nominal back gate
performance FDSOI transistors [1,5]. Standard cell based ring voltages (Fig.13). The plot shows Vmin read outs for two
oscillators have been investigated using logic test vehicles different libraries (8-track and 12-track height) resulting in
(Fig.9a and Fig.9b). Frequency vs. static and dynamic leakage similar Vmin values ~150-300mV lower than 28nm reference
were measured for Vdd=0.7, 0.8, and 0.9V. At Vdd=0.8V, libraries. A further reduction is possible by utilizing the
matched ring oscillator frequency to Vdd=0.9V can be inherent technology capability of back gate biasing, thus
obtained by forward biasing the back gate (Fig.9a). This is ensuring a certain gate overdrive at low Vdd operation due to
achieved with only a slight increase in static leakage, while the corresponding VT reduction.
dynamic leakage is reduced by 10%. By utilizing the inherent
capability of back-bias, optimization in standard cells can be C. RF Integration
realized resulting in circuit level performance on a par with The use of a planar technology and gate first HKMG
FinFETs. Recent ARM simulations comparing FDSOI to integration enables flexible layouts with lower resistances and
FinFET have shown the benefit of back-bias, where product capacitances compared to FinFET technology. The capability
performance matches FinFET and in some use cases there is a of the technology for RF applications is highlighted in Fig.14.
power-performance advantage with 22nm FDSOI [6]. fT values of 375GHz and 260GHz are reported on thin oxide
Frequencies and static power consumption were also nFET and pFET devices. fMAX values of 290GHz and
measured for Vdd=0.6 and 0.8V (Fig.9b). At Vdd=0.6V a 250GHz have also been achieved. This is the first time that
similar ring oscillator frequency to Vdd=0.8V can be obtained RF performance is reported for both nFET and pFET devices
by biasing the back gate up to ~ 1.2V. in FDSOI. These fMAX values make the technology capable of
spanning the full suite of RF applications including 5G and
C. SRAM mmWave (>24GHz), an application space that FinFET
A full suite of embedded SRAM bitcells is offered, technology is extremely challenged to meet due to inherent
inclusive of both 6-transitor single port and 8-transistor two parasitics. Low-frequency noise (LFN) is measured on similar
port bitcells. The suite spans from high-density (HD) to ultra- devices (Fig.15). The measured flat-band voltage power
spectrum density (SVg) at 100 Hz is 550·10-15 V2·μm2/Hz for
low Vmin across a wide range of leakage, performance and
nFET and pFET (0V back bias is applied). With a 2V forward
operating voltages. FDSOI technology provides excellent back bias, there is no penalty (and slight benefit in the 1/f
control on sources of VT mismatch, such as random dopant noise performance). The values are on a par with the ITRS2.0
fluctuations, due to elimination of channel doping. As a result, target (550·10-15 V2·μm2/Hz).
SRAMs are able to achieve a competitive A∆VT of 1.46mV·µm
for nFET and 1.49mV·um for pFET devices. The low A∆VT IV. CONCLUSION
values enable a 95% limited yield (LY) Vmin of 0.62V (0.52V) An industry first 22FDXTM platform demonstrating
at 25°C without the use of any design assist on a HD (High benchmark yield and performance designed for RF, low
Current) bitcell (Fig.10 shows Vmin of HD bitcell). power, and low leakage applications is presented. The use of
D. Test Product Yield forward back-bias achieves matched frequency at lower Vdd
and in turn lower active power. The benefits of back-bias can
Besides achieving benchmark device performance and be further realized at the product level where simulations have
Vmin SRAM yield, the technology has been implemented on shown comparable power-performance of 22nm FDSOI to
test products showing high yield capability. A yield FinFETs. Low off state leakage, 0.4V logic operation, high
comparison between 22nm FDSOI and a high volume 28nm fT/fMAX performance, and low cost manufacturing make the
production process is shown in Fig.11. As can be seen, 22nm technology a compelling offering to meet emerging markets in
FDSOI is already achieving yield levels matching the mobile, IoT, and RF.
reference production technology.
ACKNOWLEDGMENT
III. PLATFORM FEATURES
The authors gratefully acknowledge the contributions of the
A. Ultra Low Leakage GLOBALFOUNDRIES development and operations teams in Fab1, Fab8, and
Gate Induced Drain Leakage (GIDL) is a key parameter to Fab10, the design enablement organization, and CEA-LETI.
achieve low off-state leakage current. In that context, the REFERENCES
SiGe channel can be swapped with Si in order to reduce the [1] J. Mazurier et al., “On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM
leakage floor of the pFET devices (band gap of Si is larger Cells”, TED 2011.
[2] O. Weber et al., “14nm FDSOI Technology for High Speed and Energy Efficient Applications”,
than for SiGe compound materials). By doing so a GIDL VLSI 2014.
reduction of more than 10x is demonstrated (inset in Fig.12b). [3] S. Krishnan et al., “A Manufacturable Dual Channel (Si and SiGe) High-K Metal Gate CMOS
Technology with Multiple Oxides for High Performance and Low Power Applications”, IEDM
Off-state currents <3pA/µm for Vdd=0.8V at room temperature 2011, p. 634.
[4] K. Cheng et al., “High Performance Extremely Thin SOI (ETSOI) Hybrid CMOS with Si Channel
are achieved (Fig.12). Further Ioff reduction can be obtained NFET and Strained SiGe Channel PFET”, IEDM 2012, p. 419.
through process optimization and reverse back bias. [5] O. Weber et al., “14nm FDSOI Upgraded Device Performance for Ultra-Low Voltage Operation”,
VLSI 2015.
[6] W. Abbey.,“Realize the Potential of FDSOI”, SOI Consortium, FDSOI Symposium, San Jose 2016.

IEDM16-28
2.2.2
 Substrate + Dual Gate Silicide
SiGe channel Oxide Protect

Silicide
STI Gate Stack (self-aligned)
(gate first)

Contact
HYBRID Gate
(Well Taps) Patterning M1/M2
(80nm pitch)

Wells Dual Epi BEOL

Fig.1. Typical cross-section of nFET and Fig.2. 22nm FDSOI offers a complete Fig.3. Schematic process flow. Marked
pFET transistors. device suite. All active transistors are built process modules are unique to 22nm
on SOI whereas most of the passive FDSOI whereas all other modules are
devices are built in bulk. copied directly from a mature 28nm high-k
metal gate platform.

Fig.4. Cross-section showing co-integration Fig.5. Typical transfer characteristics for nFET and pFET devices formed in flip-well
of devices on bulk and SOI. (SLVT) and conventional-well (RVT) for |Vbg|=0V and 1V. A coupling factor of
75mV/V is demonstrated.

Fig.6. IDS/Ioff for nFET at Vdd=0.8V for Fig.7. IDS/Ioff for pFET at Vdd=0.8V for Fig.8. Mismatch measured on SLVT
L=20nm and W=0.17µm. Vbg=0V except L=20nm and W=0.17µm. Vbg=-0.8V devices for various L and W dimensions.
for nSLVT where Vbg=0V and Vbg=0.8V except for pSLVT where Vbg=-0.8V and Very low A∆VT are reported (1.2mV.µm
(FBB) were used. Wide Ioff range in Vbg=-1.6V (FBB) were used. Wide Ioff for nFET and 1.4mV.µm for pFET).
between 1nA/µm and 100nA/µm is range in between 1nA/µm and 100nA/µm
demonstrated by the full device suite. is demonstrated by the full device suite.

IEDM16-29
2.2.3
 Fig.9. a) Dynamic current versus frequency for Vdd=0.7V, 0.8V and 0.9V. Empty symbols Fig.10. Vmin cumulative distribution for
reports Vdd=0.8V with FBB. The corresponding static current is reported in the inset. b) HD 0.110μm2 bitcell. 95% LY Vmin of
Ring oscillator data for 0.6V and 0.8V. For each Vdd back gate voltages |Vbg| were varied 0.62V at 25ºC without the use of any
from 0 up to 2V. design assist.

Fig.11. Test product logic yield comparison Fig.12. Ultra low leakage devices reaching down to single digit pA/µm off currents.
between 28nm HKMG and 22nm FDSOI. Vdd=0.8V, a) nFET; b) pFET. Inset in Fig.12b: GIDL reduction by replacing SiGe channel
material with Si.

Fig.13. Vmin capability <0.4V achieved and Fig.14. fT and fMAX versus VG on nFET and Fig.15. 1/f noise measurement on 22nm
~150-300mV lower compared to 28nm pFET devices. fT/fMAX=375/290GHz for FDSOI thin oxide nFET and pFET devices
reference libraries. nFET and fT/fMAX=260/250GHz for pFET. with forward back bias.

IEDM16-30
2.2.4