SHARDA UNIVERSITY

SCHOOL OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRICAL AND ELECTRONICS
ENGINEERING

A LAB REPORT ON PLC AND SCADA

BY

NAME: SHIVAM KUMAR

SYSTEM ID: 2023469597
PROGRAMME: MTECH EEE (INDUSTRIAL AUTOMATION)

SUBMITTED TO

Dr. C MOHAN (Assistant professor SUSET)

April 2, 2024
Experiment No.1 LADDER DIAGRAM PROGRAM FOR DIGITAL LOGICS

Aim: To develop a PLC program that operates as AND/OR Logic

Requirement:

1 I0.0: Input A push button

2 I0.1: Input B push button

3 O0.0: Output

Theory:

Ladder logic is a programming language that is used to program a Programmable Logic

Controller (PLC). It is a graphical programming language that expresses logic operations
with symbolic notation using ladder diagrams.

The microprocessors found in PLCs and personal computers operate on the binary logic, having
two possible states:

 True or False
 High or Low
 1 or 0

In a PLC, binary events are expressed symbolically using ladder logic in the form of a normally
open contact (NO) and normally closed contact (NC).

The event associated with a normally open contact (NO) can be TRUE or FALSE. When
the event is TRUE the logic flow moves to the next logic expression, like the current flow in
an electric circuit when a switch is turned on.
The event associated with a normally closed contact (NC) can be TRUE or FALSE also.
The result of the normally closed contact (NC) is basically the opposite state of an event
that occurs. So, if PLC input A is FALSE the result will be TRUE. And vice versa when
PLC input A is TRUE the result will be FALSE.

AND Logic
The AND function examines multiple PLC inputs and has one resulting output. If we translate an
AND function into a ladder diagram, we can express it symbolically in the form of two PLC
inputs A and B using normally open (NO) contacts and a PLC output Y using a relay coil. The
output is only TRUE when both Inputs are TRUE.

Figure 1 AND Logic in PLC Ladder Diagram

OR Logic

The OR function examines multiple PLC inputs and has one resulting output. If we translate an
OR function into a ladder diagram, we can express it symbolically in the form of two PLC inputs
A and B using normally open contacts (NO) and a PLC output Y using relay coil.

However, the inputs are placed in the rung in what is known as a branch, equivalent to a parallel
connection in an electric circuit. The output is then connected in line with the rung. The output is
TRUE when at least one input is TRUE.

Figure 2 OR logic in PLC Ladder Diagram

RESULT

In AND logic, when the first button is pressed the contact I0.0 (N-O) becomes N-C. Likewise the
second button becomes N-C when it was pressed, the rung goes true and the coil O0.0 becomes
energized. The output coil is only energized when both buttons are at N-C states. Reverting
either button to N-O states puts the output in false state, and hence de-energizes it.

Figure 3. Ladder Diagram of an AND Logic of an output coil

The PLC digital OR logic operate just like a parallel electrical switch. When either input A or B
is pressed the contacts becomes N-C, the rung goes true and the coil O0.0 becomes energized.
The output coil is only energized when at least one of the buttons are at N-C states.

Figure 4. Ladder Diagram of an OR Logic of an output coil

Experiment No.2: LADDER DIAGRAM PROGRAM FOR LATCH CIRCUIT

Aim: To develop a PLC program that would latch the output coil

Requirement:

1 I0.0: START (ON) push button

2 I0.1: STOP (OFF) push button

3 M0.0: Output energize coil.

4 M0.0 (CONTACT): latch of output coil M0.0

Theory:

The latch is used to keep an output active even when the input is turned off. It is a self-
maintaining circuit in that, after being energized, it maintains that state until another input is
received.

In logic control, circuits that are characteristic of the previous conditions are frequently required.
The output is latched in this series by using the output contact itself, so even if the input changes,
the output condition remains constant. The input A serves as start button that when pressed will
allow the rung to be true since input B is at N-C. the coil is energized and the contact Y is
latched so that even after the input A ceases the coil is maintained in its energized state.
 Figure 5 PLC Latch Ladder Diagram

RESULT

As soon as start push button is pressed, the contact I0.0 (N-O) becomes N-C. As the N-C contact
I0.1 is already true (because of the normally closed push button in physical connections), the
rung goes true and the coil M0.0 becomes energized. When the start push button is released the
coil will remain energized.

Figure 6. Ladder Diagram of a Latch of an output coil

As the coil M0.0 gets energized, the latched contact of this coil which is represented as M0.0 (N-
O) becomes N-C and the logic passes through this rung and the coil remains ON even if the start
push button is released.

Stopping the process entails having to simply press the stop push button. Due to pressing of stop
push button, the contact I0.1 becomes N-O (normally open) and rung logic goes false, which in
turn de-energizes the coil Q0.0 and de-energized the coil contact.
Experiment No.3 LADDER DIAGRAM PROGRAM USING PLC’s TIMER

Aim: To Develop a Latch Using Timer

Requirements:

1 I0.0: START (ON) push button

2 ON-Delay Timer set to a preset value of 5 and timer base 1 Second

3 Timer output Contact O0.1

4 I0.1: STOP (OFF) push button

5 Q0.0: output energize coil

6 Q0.0 (CONTACT): latch of output coil Q0.0

Theory:

An ON-delay timer is a type of time delay used to control the activation of a circuit by delaying
the initiation of current flow. ON-delay timers are typically used in applications where it is
important to ensure that a circuit is not activated until after a certain amount of time has elapsed.
When an input is supplied, the timer counts up to a specified period of time in seconds before
energizing the coil Q.
 Figure 7 Waveform of ON Delay Timer

RESULT
In this scheme ON Delay timer was introduced. As soon as start push button I0.0 is pressed, the
contact I0.0 (N-O) becomes N-C and the ON delay timer starts. Following the start condition,
the timer took 5 seconds to enable the DN coil and subsequently energize the output coil. The
preset value signifies the length of the delay in seconds.
The coil remains energized until the I0.0 button is pushed, after which the coil will become de-
energized.
Figure 8 Simulation PLC Timer Delay
Experiment No.4 LADDER DIAGRAM PROGRAM USING PLC’s COUNTER

Aim: To Develop a Ladder Diagram using PLC Counter

Requirements:

1 I0.0: START (ON) push button

2 Up Counter set to a preset value of 5

3 Timer output Contact O0.1

4 I0.1: STOP (OFF) push button

5 Q0.0: output to energize coil

6 Q0.0 (CONTACT): latch of output coil Q0.0

Theory:

A PLC counter is a function block that counts up or down until it reaches a limit and then sets the
output. Counters are used in PLC programming to measure how many times an event has
happened in a process or how many times a product has been produced. Counters operate like
relay counters, but they do not need to be connected to wires to operate.
RESULT
Experiment No.5 LADDER DIAGRAM PROGRAM USING ARITHMETIC FUNCTIONS

Aim: To Develop a Ladder Diagram using PLC Arithmetic functions

1 I0.0: START (ON) push button

2 Three Up Counters set to a preset value of 5

3 ADD function block

4 RESET push button

Theory

In PLC programming, the ADD function is a basic arithmetic operation used to perform addition.
It adds two or more input values together and produces a single output value, which is the sum of
the inputs. This function is commonly used in industrial automation applications to perform
calculations, keep track of quantities, or control processes.

The add instruction has three operands. Two operands hold the source data (Source A and Source
B), which are added together. Both sources can be registers, or one source can be a register while
the other one is a number. The third operand is the destination, which holds the sum of Source A
and Source B.

When rung conditions are true, this output instruction adds Source A to Source B and stores the
result at the destination address. Source A and Source B can either be values or addresses that
contain values, however, Source A and Source B cannot both be constants.
RESULT