Single-Chip Baseband Signal Processor for

Software-Defined Radio

V Seiichi Nishijima V Miyoshi Saito V Iwao Sugiyama

(Manuscript received September 30, 2005)

Reconfigurable processor technology offers a way to couple significant hardware

performance improvements with realtime software signal processing. This technolo-
gy enables software-defined radio (SDR) to be realized on a system-on-a-chip (SoC)
platform. In this paper, we describe an SDR SoC LSI that is suitable for use in pro-
grammable wireless communication systems. The LSI has two advanced features.
First, the hybrid architecture consists of reconfigurable signal processors and accel-
erator circuits. These accelerators are parametric circuits essential for baseband
processing. Second, the reconfigurable processing elements have a cluster structure
that improves the mapping efficiency and minimizes the processing time. We also
describe a prototype SDR system that uses this LSI to perform software-defined
IEEE802.11a and 11b communications.

1. Introduction ture and features of this LSI and a prototype sys-

For mobile communication systems beyond tem for future smart SDR systems.
the third generation, it will be necessary to real-
ize a smart wireless terminal that can operate 2. Features of SDR LSI
under several communication systems. Software- 2.1 Hybrid architecture
defined radio (SDR) is a progressive technology Although the flexibility of reconfigurable
for realizing this goal. An SDR system features processors inevitably produces redundancy, we
multiple standards, multiple bands, seamless reduced the area and power consumption of the
mode/band transitions, and software programma- LSI by using the accelerator modules.
bility.1) A variety of SDR prototypes have been The LSI has a hybrid architecture contain-
demonstrated that use FPGAs, DSPs, and general- ing reconfigurable processors5) and accelerator
purpose reconfigurable processors.2)-4) We have modules. Common functions of the major
developed a single-chip solution for the baseband wireless standards, for example, fast-Fourier-
signal processing of an SDR system. This SDR transformation, forward-error-correction, and
SoC LSI (SDR LSI, hereafter) integrates several finite impulse response (FIR) filtering, are inte-
accelerator modules that can be applied for dif- grated into the accelerators using a parametric
ferent wireless standards and highly effective and structure.
powerful reconfigurable processing cores.5) This Figure 1 shows the block diagram of the LSI.
single-chip solution will make it possible to pro- The LSI consists of three reconfigurable signal
duce small size radio terminals that have better processors (RSPs), three accelerators, and five
flexibility and programmability than hardware additional hardware circuits. These blocks are
solutions. In this paper, we present the architec- connected using crossbar type data networks and

240 FUJITSU Sci. Tech. J., 42,2,p.240-247(April 2006)

 S. Nishijima et al.: Single-Chip Baseband Signal Processor for Software-Defined Radio

To other circuits
CPU
Reference clock PLL Clock ARM946 SRAM DMAC Memory
Memory
16 KB controller
generator AHB BUS

GPIO signal APB BUS

Bridge
UART signal
IRQ signal Interrupt External IRC GPIO UART TIMER
controller IRC Bridge Bus controller Control signal

Control Bus
Synchronization

Sample timing
transmission
Pilot symbol

FFT/IFFT
ADC/DAC

recovery

interface
FIR filter
interface

MAC
PSM
RSP

RSP

RSP

FEC
ADC
MAC
DAC
Output

Input

Expansion I/O Expansion I/O

Crossbar data network Crossbar data network Crossbar data network

Figure 1
Block diagram of SDR LSI.

controlled by a central processing unit (CPU). calculator, and arctangent tables. These macro
By changing the network configuration, elements are more effective for reducing the
programs of the reconfigurable processors, and latency.
accelerator parameters, the LSI can be The RSP cluster has a sequencer for config-
reconfigured to operate with many wireless uring the PEs and the networks between PEs.
communication systems. This sequencer reduces the number of PEs that
are needed for signal processing. Figures 3 (a),
2.2 RSPs 3 (b), and 3 (c) show an example of cyclic recon-
The RSPs provide the core features of pow- figuration using this sequencer. The data
erful processing and high flexibility. In this work, processing flow in Figure 3 (a) shows the process-
we used a coarse-grained RSP designed by ing flow for four inputs and outputs and eight
Fujitsu. This RSP has the advantages of a processing steps using 30 PEs. Figures 3 (b) and
short latency and an area-effective mapping 3 (c) show the data processing flow for cyclic
architecture.5) reconfiguration. The sequencer alternates oper-
Figure 2 shows the structure of the RSP. To ation between the odd and even sequences. As
reduce the operation latency, the RSP is designed shown in these figures, cyclic reconfiguration
to minimize the physical data transfer delay enables signal processing to be performed using
between each processor element (PE) by dividing half of the PE resources required for ordinary data
a large PE array into small reconfigurable logic processing. Therefore, this architecture makes the
cores called clusters. The RSP also includes mapping more area-effective.
macro elements that contain a divider, square-root

FUJITSU Sci. Tech. J., 42,2,(April 2006) 241

S. Nishijima et al.: Single-Chip Baseband Signal Processor for Software-Defined Radio

Input from crossbar data network

16-bit × 4 channels
RSP
Cluster

Cluster 1 Cluster 5 PE PE

Sequencer
PE PE
Cluster 2 Cluster 6
PE PE

Cluster 3 Cluster 7
PE PE

Macro
Cluster 4
elements

Networks

Output to crossbar data network

16-bit × 4 channels
PE: Processing element

Figure 2
Structure of reconfigurable signal processor (RSP).

Sequencer

1 1 1 1
Odd state
Data from networks 3 3 3 3

Cluster 5 5 5 5
1 1 1 1 Even state
7 7 7 7
2 2 2
Sequencer
1/2 1/2 1/2 1/2
3 3 3 3

4 4 4 4 Odd state 3/4 3/4 3/4 3/4

5 5 5 5 5/6 5/6 5/6 5/6

Even state
6 6 6
7/8 7/8 7/8 7/8
Sequencer
7 7 7 7
PE
8 8 8 8 2 2 2
Odd state
4 4 4 4
Data to networks
6 6 6
Even state
8 8 8 8

(a) Data processing flow (b) Flow mapping of PEs (c) PE behavior

Figure 3
Example of cyclic reconfiguration using sequencer.

242 FUJITSU Sci. Tech. J., 42,2,(April 2006)

 S. Nishijima et al.: Single-Chip Baseband Signal Processor for Software-Defined Radio

2.3 Programmable state machine parametric processing needed to cover the mod-
The major wireless communication systems ern mobile-wireless communication systems.
require a state transition unit to control their Table 1 summarizes the functions of the
communications state transitions. To realize a accelerators.
software-defined state flow controller, we imple- The FFT module executes 2n-point FFT and
mented a programmable, scalable state machine inverse FFT, where n is 6 to 13. This covers the
in the SDR LSI. 64 points of IEEE802.11a and the 2048 and 8192
Figure 4 shows the structure of the program- points of IEEE802.16x (WiMAX) and future
mable state machine (PSM). The PSM consists of digital broadcasting standards.
16 state memories, 27 input events, and 27 out- The Viterbi module decodes signals that are
put events. The conditions and flow of state encoded with any set of the three generator-poly-
transitions are defined and programmed in the nomial types (G0, G1, G2) shown in Table 1. The
state memories for each wireless communication constraint lengths can be set to 7 and 9, and the
system. Figure 5 shows an example mapping coding rates are 1/2 and 1/3. These parameter
of the state flow of the IEEE802.11a and ranges are suitable for the IEEE802.11a, 11b,
IEEE802.11b standards. With this mapping, a W-CDMA, and WiMAX standards.
radio system is realized using 9 states and 15 The programmable flip-flop-array module
events. operates as a scrambler/descrambler, CRC circuit,
The PSM has an extensible structure so the or convolution encoder, depending on the array
LSI can control the state transitions of multi-chip combination setting. The FIR module covers up
systems. This feature is described in Section 2.5. to 32 filter taps.

2.4 Accelerators 2.5 Multi-chip expansion and optimized

The common processing functions are crossbar networks
performed using four types of accelerators: a fast Although the LSI can be used as a single-
Fourier transform (FFT), FIR, Viterbi decoder, and chip solution for the baseband processing of SDR
32-stage programmable flip-flop-array module. systems, we added a feature for expanding its I/O
These accelerator modules can perform the terminals from the crossbar data networks. This

State memories (16 states) State Event

S00
S01 Stop
S00 Wait
S06
S15
Tx Idle Sync Decode Demod Reset
S08 S01 S02 S03 S04 S07
Condition and flow
of state transition
Error
S05
State
Input events transition Output events
27 controller 27

Figure 5
Figure 4 Example mapping of state flow of IEEE802.11a and
Programmable state machine (PSM). IEEE802.11b standards.

FUJITSU Sci. Tech. J., 42,2,(April 2006) 243

S. Nishijima et al.: Single-Chip Baseband Signal Processor for Software-Defined Radio

Table 1
Function of accelerators.
Function Parameters
FFT/IFFT 2 points. n is 6 to 13.
n

Polynomial generators: G0=1 to 777 (octal)

G1=1 to 777 (octal)
Viterbi decoder G2=1 to 777 (octal)
Constraint lengths: 7 and 9
Coding rates: 1/2 and 1/3
Polynomial generators: X15+X14+1,
Scrambler/ X7+X6+1,
descrambler X7+X4+1

Programmable CRC 8to 32-bit CRC

flip-flop-array
Polynomial generators: G0=1 to 777 (octal)
G1=1 to 777 (octal)
Convolution
G2=1 to 777 (octal)
encoder
Constraint lengths: 7 and 9
Coding rates: 1/2 and 1/3

FIR filter Number of filter taps: Up to 32

80 0.04
feature enables multi-chip processing so the Optimum point
70

Flexibility per area (mm–2)

system can be adapted to future wireless commu-
60 0.03
nication methods that require more processing
Area (mm2)

50
power. The I/Os can be expanded to two pairs of 40 0.02
three 16-bit data channels with a maximum trans- 30
fer rate of 4.8 Gb/s. This high transfer rate will 20 0.01
be sufficient for most wireless communication 10
systems. 0 0
0 1 2 3 4 5 6 7 8
The signal networks between each module Number of blocks
in the LSI must have a wide bandwidth. The data
Figure 6
network in the LSI consists of four 16-bit cross-
Calculated crossbar area versus number of crossbar
bar channels with a maximum transfer rate of blocks.
6.4 Gb/s. Because the full-channel crossbar
occupies a large area of the LSI, we divided it into
three blocks based on an optimization calculation the core area, while the other processing circuits,
(Figure 6). including the SRAM, occupy the remaining area.
A photograph of the chip is shown in Figure 7.
3. Specifications and evaluation The chip is mounted on a 1156-pin flip chip ball
board grid array (FCBGA) package. Other specifications
The SDR LSI integrates 774 PEs, which op- of the LSI are summarized in Table 2.
erate at a maximum clock speed of 160 MHz and We constructed an evaluation board for this
a peak performance of 103 GOPS. The control LSI (Figures 8 and 9). The board contains two
CPU operates at 66 MHz, while the accelerators SDR LSIs and three FPGAs. One of the FPGAs is
and other signal processing units operate at a used to interconnect the two SDR LSIs, and the
maximum of 100 MHz. The PEs occupy 75% of other two perform media access control (MAC) and

244 FUJITSU Sci. Tech. J., 42,2,(April 2006)

 S. Nishijima et al.: Single-Chip Baseband Signal Processor for Software-Defined Radio

Flash memory and SDRAM

Tx (DAC) Rx (ADC) SDR LSI
Accelerators
CPU
Crossbar data networks

Cluster Cluster

Cluster Cluster

RSP RSP RSP

Cluster Cluster

Cluster Cluster
Analog interface External interface
Tx: Transmitter, Rx: Receiver
RSP: Reconfigurable Signal Processor
Figure 8
Figure 7 Evaluation board.
SDR LSI chip.

Table 2
SDR chip specifications.
CPU ARM946
Internal memory 370 KB
External memory Flash (16 MB), SDRAM (256 MB)
I/O for control GPIO, UART, IRQ interface, control bus
Power supply 1.2 V (I/O: 2.5 V)
ARM: 66 MHz
Clock speed Accelerator circuits: Up to 100 MHz
Reconfigurable signal processors: Up to 160 MHz
Bit width of crossbar data networks 16-bit × 4 channels
Bit width of expansion I/O 16-bit × 3 channels
Package 1156-pin FCBGA
Performance of RSPs Up to 103 GOPS
Number of processing elements 774
FFT/IFFT
Viterbi decoder
Accelerators Scrambler/descrambler
CRC
Convolution encoder
FIR filter

FUJITSU Sci. Tech. J., 42,2,(April 2006) 245

S. Nishijima et al.: Single-Chip Baseband Signal Processor for Software-Defined Radio

External controller
Data signal Configuration programs

Source clock External interface

To other chips
FPGA
for
board control

FPGA
for
MAC
Analog signal Analog interface

DAC FPGA
SDR LSI for SDR LSI
ADC connection

Control bus

Flash
SDRAM
memory

Figure 9
Block diagram of evaluation board.

Table 3
Specifications of evaluation board.
Number of SDR LSIs 2
Peak performance 103 GOPS × 2
Number of FPGAs 3
External interfaces 16-bit parallel I/O, RS232C
Power supply 24 V
Board size Width: 35 cm, Length: 25 cm
Download time per wireless system 20 ms
Number of downloadable wireless systems Up to 7
Reconfiguration time 5 ms

board control. in these cases. Using these example configura-

Up to seven configuration programs of the tions on the board, we confirmed that these
SDR can be stored in the flash memory on the systems worked well with maximum throughputs
board or downloaded from the external control- of 43.0 Mb/s. The time needed for reconfiguration
ler. The download time for configuration is 20 ms between these two standards was about 5 ms.
for each wireless system. The other specifications
are summarized in Table 3. 4. Conclusion
We have developed example configurations We have developed a baseband signal pro-
for the IEEE 802.11a and IEEE 802.11b standards cessing LSI for SDR systems. The LSI consists of
to demonstrate SDR operation on the board. The reconfigurable signal processors, parametric
usage of resources was evaluated to one SDR LSI accelerators, a programmable state machine, and

246 FUJITSU Sci. Tech. J., 42,2,(April 2006)

 S. Nishijima et al.: Single-Chip Baseband Signal Processor for Software-Defined Radio

supplemental hardware circuits. Because the LSI References

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Acknowledgements on Circuits/System, Computers and Communica-
We thank all the experts of the SDR LSI tion (ITC-CSCC), vol.2, 2005, p.805-806.
5) M. Saito, H. Fujisawa, N. Ujiie, and H. Yoshizawa:
development team for their professional support Cluster Architecture for Reconfigurable Signal
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National Institute of Information and Communi-
cations Technology of Japan.

Seiichi Nishijima, Fujitsu Ltd. Iwao Sugiyama, Fujitsu Ltd.

Mr. Nishijima received the B.S. and M.S. Mr. Sugiyama received the B.S. degree
degrees in Electronics Engineering from in Physics from Tokyo University of Sci-
Hiroshima University, Higashi-Hiroshima, ence, Tokyo, Japan in 1984. He joined
Japan in 1999 and 2001, respectively. Fujitsu Ltd., Kawasaki, Japan in 1984.
He joined Fujitsu Ltd., Kawasaki, Japan Since February 2004, he has been
in 2001, where he has been research- researching and developing a next-gen-
ing and developing LSI for software eration platform for mobile wireless de-
defined radio (SDR). He is a member vices and systems.
of the Institute of Electronics, Informa-
tion and Communication Engineers
(IEICE) of Japan.

Miyoshi Saito, Fujitsu Ltd.

Mr. Saito received the B.S. and M.S.
degrees in Physics from Tokyo Institute
of Technology, Tokyo, Japan in 1987 and
1989, respectively. He joined Fujitsu
Ltd., Kawasaki, Japan in 1989, where
he has been researching and develop-
ing quantum electron devices,
high-speed DRAMs, embedded proces-
sors, wireless baseband LSIs, and
reconfigurable devices. He is a mem-
ber of the Institute of Electrical and Electronics Engineers (IEEE)
and the Association for Computing Machinery (ACM).

FUJITSU Sci. Tech. J., 42,2,(April 2006) 247